... | ... | @@ -42,58 +42,29 @@ differentiates the board executions. |
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## Specifications
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Parameter</strong></td>
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<td><strong>Value</strong></td>
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</tr>
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<tr class="even">
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<td><strong>Form-factor</strong></td>
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<td>FMC, LPC connector</td>
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</tr>
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<tr class="odd">
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<td><strong>WorldFIP connector</strong></td>
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<td>Micro Sub-D 9 pins</td>
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</tr>
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<tr class="even">
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<td><strong>WorldFIP interface</strong></td>
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<td><a href="https://www.ohwr.org/project/cern-fip/wikis/FielDrive">FielDrive</a> + <a href="https://www.ohwr.org/project/cern-fip/wikis/FieldTR">FieldTR</a> (Alstom)</td>
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</tr>
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<tr class="odd">
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<td><strong>Bus speed</strong></td>
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<td>31.25k, 1M, 2.5M, 5M (different executions of hardware)<br />
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Note that the 5M version is supported by the hw but is has not been tested and is not supported by the current gw/sw/lib</td>
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</tr>
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<tr class="even">
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<td><strong>External sync. input</strong></td>
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<td>Optional sync of the WorldFIP start of macrocycle; LEMO 0 connector; TTL; Software selectable 50 Ohms termination</td>
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</tr>
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<tr class="odd">
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<td><strong>Front panel LEDs</strong></td>
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<td>FMC TX ACT : at the end of a macrocycle there has been no transmission failure<br />
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FMC TX ERR: at the end of a macrocycle transmission errors have been detected<br />
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FMC RX ACT: at the end of a macrocycle there has been no reception failure<br />
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FMC RX ERR: at the end of a macrocycle reception errors have been detected<br />
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FMC SYNC ACT: application expects sync pulse and it is receiving it successfully<br />
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FMC SYNC ERR: application expects sync pulse which it is not arriving<br />
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SPEC GREEN: blinking using the 100 MHz clock<br />
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SPEC RED: PCIe reset</td>
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</tr>
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<tr class="even">
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<td><strong>Test points</strong></td>
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<td>Four through hole test points (TP) next to the FMC connector<br />
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TP1: connected to FielDrive RXD<br />
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TP2: connected to FielDrive TXD<br />
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TP3: connected to Mock Turtle led&dbg reg bit 8<br />
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TP4: connected to Mock Turtle led&dbg reg bit 9</td>
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</tr>
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<tr class="odd">
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<td><strong>Power Consumption</strong></td>
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<td>200 mA</td>
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</tr>
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</tbody>
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</table>
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|**Parameter**|**Value**|
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|----|----|
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|**Form-factor**|FMC, LPC connector|
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|**WorldFIP connector**|Micro Sub-D 9 pins|
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|**WorldFIP interface**|[FielDrive](https://www.ohwr.org/project/cern-fip/wikis/FielDrive) + [FieldTR](https://www.ohwr.org/project/cern-fip/wikis/FieldTR) (Alstom)|
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|**Bus speed**|31.25k, 1M, 2.5M, 5M (different executions of hardware)
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Note that the 5M version is supported by the hw but is has not been tested and is not supported by the current gw/sw/lib|
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|**External sync. input**|Optional sync of the WorldFIP start of macrocycle; LEMO 0 connector; TTL; Software selectable 50 Ohms termination|
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|**Front panel LEDs**|FMC TX ACT : at the end of a macrocycle there has been no transmission failure
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FMC TX ERR: at the end of a macrocycle transmission errors have been detected
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FMC RX ACT: at the end of a macrocycle there has been no reception failure
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FMC RX ERR: at the end of a macrocycle reception errors have been detected
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FMC SYNC ACT: application expects sync pulse and it is receiving it successfully
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FMC SYNC ERR: application expects sync pulse which it is not arriving
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SPEC GREEN: blinking using the 100 MHz clock
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SPEC RED: PCIe reset|
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|**Test points**|Four through hole test points (TP) next to the FMC connector
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TP1: connected to FielDrive RXD
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TP2: connected to FielDrive TXD
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TP3: connected to Mock Turtle led&dbg reg bit 8
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TP4: connected to Mock Turtle led&dbg reg bit 9|
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|**Power Consumption**|200 mA|
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-----
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... | ... | @@ -138,96 +109,32 @@ designer - CERN |
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## Project Status
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Date</strong></td>
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<td><strong>Event</strong></td>
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</tr>
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<tr class="even">
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<td>10-2014</td>
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<td>Schematics work started</td>
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</tr>
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<tr class="odd">
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<td>12-2014</td>
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<td>Schematics ready for layout</td>
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</tr>
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<tr class="even">
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<td>01-2015</td>
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<td>Board layout done at CERN by DEM</td>
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</tr>
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<tr class="odd">
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<td>01-2015</td>
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<td>[Layout review](LayoutReviewJan2015)</td>
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</tr>
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<tr class="even">
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<td>02-2015</td>
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<td>Layout modification ready</td>
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</tr>
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<tr class="odd">
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<td>02-2015</td>
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<td>First brainstorm about gateware and firmware</td>
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</tr>
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<tr class="even">
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<td>03-2015</td>
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<td>Production files finalised, 3 prototypes ordered</td>
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</tr>
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<tr class="odd">
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<td>04-2015</td>
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<td>Designer Matthieu Cattin †</td>
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</tr>
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<tr class="even">
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<td>04-2015</td>
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<td>3 assembled prototypes received, 5 empty PCBs available</td>
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</tr>
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<tr class="odd">
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<td>07-2015</td>
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<td>One board tested that sent and received WorldFIP data. ADC not tested.</td>
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</tr>
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<tr class="even">
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<td>02-2016</td>
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<td>Production Test program being written by a company. ADC testing is part of it.</td>
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</tr>
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<tr class="odd">
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<td>10-2016</td>
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<td>[Schematics review for V2](SchReviewOct2016)</td>
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</tr>
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<tr class="even">
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<td>12-2016</td>
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<td>[Layout review for V2](LayoutReviewDec2016)</td>
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</tr>
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<tr class="odd">
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<td>01-2017</td>
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<td><strong>Hardware V3</strong> ready for production; ADC diagnostics removed based on high production and maintenance costs.</td>
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</tr>
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<tr class="even">
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<td>20-01-2017</td>
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<td>Ordered 15 V3 prototype cards.</td>
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</tr>
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<tr class="odd">
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<td>28-03-2017</td>
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<td>15 V3 prototype cards received; validated and they are ok!</td>
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</tr>
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<tr class="even">
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<td>17-07-2017</td>
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<td>Long runs of V3 boards in the lab and in CHARM</td>
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</tr>
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<tr class="odd">
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<td>06-09-2017</td>
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<td>Production of 130 v4 masterFIP boards started, to be available by early December 2017</td>
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</tr>
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<tr class="even">
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<td>16-05-2018</td>
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<td>Reception of 100 v4 masterFIP boards for TS1 installations</td>
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</tr>
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<tr class="odd">
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<td>13-07-2018</td>
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<td>Reception of 500 v4 masterFIP boards</td>
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</tr>
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</tbody>
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</table>
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|**Date**|**Event**|
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|----|----|
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|10-2014|Schematics work started|
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|12-2014|Schematics ready for layout|
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|01-2015|Board layout done at CERN by DEM|
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|
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|01-2015|[Layout review](LayoutReviewJan2015)|
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|02-2015|Layout modification ready|
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|02-2015|First brainstorm about gateware and firmware|
|
|
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|03-2015|Production files finalised, 3 prototypes ordered|
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|04-2015|Designer Matthieu Cattin †|
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|04-2015|3 assembled prototypes received, 5 empty PCBs available|
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|07-2015|One board tested that sent and received WorldFIP data. ADC not tested.|
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|02-2016|Production Test program being written by a company. ADC testing is part of it.|
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|10-2016|[Schematics review for V2](SchReviewOct2016)|
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|12-2016|[Layout review for V2](LayoutReviewDec2016)|
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|01-2017|**Hardware V3** ready for production; ADC diagnostics removed based on high production and maintenance costs.|
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|20-01-2017|Ordered 15 V3 prototype cards.|
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|28-03-2017|15 V3 prototype cards received; validated and they are ok!|
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|17-07-2017|Long runs of V3 boards in the lab and in CHARM|
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|06-09-2017|Production of 130 v4 masterFIP boards started, to be available by early December 2017|
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|16-05-2018|Reception of 100 v4 masterFIP boards for TS1 installations|
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|13-07-2018|Reception of 500 v4 masterFIP boards|
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-----
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*Matthieu Cattin, Eva Gousiou, Erik van der Bij, 3 September 2018*
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