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Added 4-layer PCB authored by Erik van der Bij's avatar Erik van der Bij
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...@@ -25,8 +25,9 @@ too. ...@@ -25,8 +25,9 @@ too.
- One of the inputs is capable of driving a global clock net in the - One of the inputs is capable of driving a global clock net in the
carrier's FPGA. carrier's FPGA.
- Inputs and outputs protected against +15V pulses with a pulse width - Inputs and outputs protected against +15V pulses with a pulse width
of up to 10us @ of up to 10us @ 50Hz.
50Hz. - 4-layer
PCB
## Block diagram ## Block diagram
![](/uploads/2d0b0f455ea9fd3936c518b4d07a6173/block_diagram.jpg) ![](/uploads/2d0b0f455ea9fd3936c518b4d07a6173/block_diagram.jpg)
...@@ -138,7 +139,7 @@ Removed "withstands output shorted" spec: it works but is out of spec ...@@ -138,7 +139,7 @@ Removed "withstands output shorted" spec: it works but is out of spec
----- -----
Tom Wlostowski, Erik van der Bij - 24 July 2014 Tom Wlostowski, Erik van der Bij - 31 July 2014
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