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@@ -11,19 +11,20 @@ dio\_small.jpg
 
 ## Functional specifications
 
-  - 5 input/output ports (Lemo 00 connectors)
+  - 5 input/output ports with independently programmable direction (Lemo
+    00 connectors).
   - Output levels: LVTTL, capable of driving +2.5 V over a 50-Ohm load.
-    At power-up the outputs are in Hi-Z state (V2 and higher)
+    At power-up the outputs are in Hi-Z state.
   - Input levels: any logic standard from Vih = 1 V to Vih = 5 V
     (programmable threshold)
   - Output Rise/fall times: max. 2 ns
-  - Input bandwidth: 200 MHz
+  - I/O bandwidth: 200 MHz
   - Programmable 50-Ohm input termination in each channel
   - LVDS I/O on the carrier side
   - One of the inputs is capable of driving a global clock net in the
     carrier's FPGA
-  - Inputs protected against +15V pulses with a pulse width of up to
-    10us @
+  - Inputs and outputs protected against +15V pulses with a pulse width
+    of up to 10us @
 50Hz
 
 ## Block diagram