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@@ -2,16 +2,21 @@
 
 ## Functional specifications
 
-  - 5 TTL-compatible I/Os.
+  - 5 input/output ports (Lemo 00 connectors)
+  - Output levels: LVTTL, capable of driving +3.3 V over a 50-Ohm load.
+    At power-up the outputs should be in Hi-Z state.
+  - Input levels: any logic standard from Vih = 1 V to Vih = 5 V
+    (programmable threshold).
+  - Output Rise/fall times: max. 2 ns
+  - Input bandwidth: min. 200 MHz
   - Programmable 50-Ohm input termination in each channel.
-  - External inputs need to be protected against +15V pulses with a
-    pulse width of at least 10us @ 50Hz (with protection diodes if
-    possible).
+  - LVDS I/O on the carrier side.
+  - One of the inputs shall be capable of driving a global clock net in
+    the carrier's FPGA.
+  - Inputs need to be protected against +15V pulses with a pulse width
+    of at least 10us @ 50Hz (with protection diodes if possible).
   - Need to withstand a continuous short-circuit on all the outputs at
     the same time.
-  - Output standard: 50 Ohm TTL drivers (with 2V/ns or faster rising
-    edges). At power-up the default output state is low, with no
-    glitches.
 
 ## Project Status