| ... | @@ -16,16 +16,16 @@ dio\_small.jpg |
... | @@ -16,16 +16,16 @@ dio\_small.jpg |
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- Output levels: LVTTL, capable of driving +2.5 V over a 50-Ohm load.
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- Output levels: LVTTL, capable of driving +2.5 V over a 50-Ohm load.
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At power-up the outputs are in Hi-Z state.
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At power-up the outputs are in Hi-Z state.
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- Input levels: any logic standard from Vih = 1 V to Vih = 5 V
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- Input levels: any logic standard from Vih = 1 V to Vih = 5 V
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(programmable threshold)
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(programmable threshold).
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- Output Rise/fall times: max. 2 ns
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- Output Rise/fall times: max. 2 ns.
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- I/O bandwidth: 200 MHz
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- I/O bandwidth: 200 MHz.
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- Programmable 50-Ohm input termination in each channel
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- Programmable 50-Ohm input termination in each channel.
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- LVDS I/O on the carrier side
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- LVDS I/O on the carrier side.
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- One of the inputs is capable of driving a global clock net in the
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- One of the inputs is capable of driving a global clock net in the
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carrier's FPGA
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carrier's FPGA.
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- Inputs and outputs protected against +15V pulses with a pulse width
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- Inputs and outputs protected against +15V pulses with a pulse width
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of up to 10us @
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of up to 10us @
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50Hz
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50Hz.
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## Block diagram
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## Block diagram
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| ... | @@ -124,7 +124,7 @@ Removed "withstands output shorted" spec: it works but is out of spec |
... | @@ -124,7 +124,7 @@ Removed "withstands output shorted" spec: it works but is out of spec |
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
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<td>25-10-2012</td>
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<td>25-10-2012</td>
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<td>Review of V2-0 planned.</td>
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<td><a href="Review20121025">Review</a> of V2-0.</td>
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</tr>
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</tr>
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</tbody>
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</tbody>
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</table>
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</table>
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| ... | | ... | |
