... | ... | @@ -34,7 +34,7 @@ set references. The 8 outputs are TTL level. |
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|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>Comparator input levels</td>
|
|
|
<td>±10V</td>
|
|
|
<td>±5V</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>Comparators to FPGA</td>
|
... | ... | @@ -42,23 +42,23 @@ set references. The 8 outputs are TTL level. |
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>FMC to carrier interface</td>
|
|
|
<td>Low pin count</td>
|
|
|
<td>Low pin count (LPC)</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>Input impedance</td>
|
|
|
<td>High-impedance or 50 Ohm (selectable)</td>
|
|
|
<td>Supported Vadj</td>
|
|
|
<td>1.8V and 2.5V</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>Comparator Output Rise/fall times</td>
|
|
|
<td>150ps</td>
|
|
|
<td>Input impedance</td>
|
|
|
<td>High-impedance or 50 Ohm (selectable)</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>Programmable threshold</td>
|
|
|
<td>From 10V to -10V using DAC with 5mV precision</td>
|
|
|
<td>From 5V to -5V using DAC with 5mV precision</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>Digital Outputs</td>
|
|
|
<td>TTL 5V line driver</td>
|
|
|
<td>TTL line driver 50Ohm</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>DAC resolution</td>
|
... | ... | @@ -70,7 +70,7 @@ set references. The 8 outputs are TTL level. |
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>Insulation</td>
|
|
|
<td>Output isolated contacts</td>
|
|
|
<td>Output isolated contact</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
... | ... | @@ -129,20 +129,20 @@ set references. The 8 outputs are TTL level. |
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>15-10-2015</td>
|
|
|
<td>Final review process</td>
|
|
|
<td><strong><span class="Foreseen"></span></strong> Final review process</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>01-11-2015</td>
|
|
|
<td>Schematics sent to CERN design office for PCB layout and production of two samples</td>
|
|
|
<td><strong><span class="Foreseen"></span></strong> Schematics sent to CERN design office for PCB layout and production of two samples</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>01-01-2016</td>
|
|
|
<td>Reception of PCB samples and tests</td>
|
|
|
<td><strong><span class="Foreseen"></span></strong> Reception of PCB samples and tests</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
|
|
|
-----
|
|
|
|
|
|
27 July 2015
|
|
|
12 October 2015
|
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|