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# FMC DIO 10i 8o I/O module
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FmcDIO10i8o is an I/O card in FMC form-factor. It's 10 inputs use fast
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differential comparators (propagation delay \< 1 ns) with 12-bit DAC to
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set references. The 8 outputs are TTL level.
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## Functional specifications
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Parameter</strong></td>
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<td><b> Value </b></td>
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</tr>
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<tr class="even">
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<td>Inputs</td>
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<td>10 high speed inputs and comparators</td>
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</tr>
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<tr class="odd">
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<td>Outputs</td>
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<td>8 TTL</td>
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</tr>
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<tr class="even">
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<td>Number of comparators</td>
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<td>20 (2 per input channel)</td>
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</tr>
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<tr class="odd">
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<td>Comparator reference</td>
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<td>20 (1 per comparator)</td>
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</tr>
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<tr class="even">
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<td>Comparator input bandwidth</td>
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<td>100MHz</td>
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</tr>
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<tr class="odd">
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<td>Comparator input levels</td>
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<td>±10V</td>
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</tr>
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<tr class="even">
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<td>Comparators to FPGA</td>
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<td>LVDS, 1 pair per channel</td>
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</tr>
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<tr class="odd">
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<td>FMC to carrier interface</td>
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<td>Low pin count</td>
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</tr>
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<tr class="even">
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<td>Input impedance</td>
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<td>High-impedance or 50 Ohm (selectable)</td>
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</tr>
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<tr class="odd">
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<td>Comparator Output Rise/fall times</td>
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<td>150ps</td>
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</tr>
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<tr class="even">
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<td>Programmable threshold</td>
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<td>From 10V to -10V using DAC with 5mV precision</td>
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</tr>
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<tr class="odd">
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<td>Digital Outputs</td>
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<td>TTL 5V line driver</td>
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</tr>
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<tr class="even">
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<td>DAC resolution</td>
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<td>12bits</td>
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</tr>
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<tr class="odd">
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<td>Sampling rate</td>
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<td>166kHz</td>
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</tr>
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<tr class="even">
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<td>Insulation</td>
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<td>Output isolated contacts</td>
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</tr>
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</tbody>
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</table>
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-----
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## Project information
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- Official production documentation: "EDMS EDA-xxxxx"
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- [Software](Software)
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- [Frequently Asked Questions](FAQ)
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- [Users](Users)
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-----
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## Contacts
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### Commercial producers
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- none yet
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### Project
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- Simon Andre J Uyttenhove \<simon.uyttenhove@cern.ch\>
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- Pieter Van Trappen \<pieter.van.trappen@cern.ch\>
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-----
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## Project Status
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Date</strong></td>
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<td><b> Event </b></td>
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</tr>
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<tr class="even">
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<td>02-06-2015</td>
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<td>First ideas for the I/O card.</td>
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</tr>
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<tr class="odd">
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<td>27-07-2015</td>
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<td>Creation of Open Hardware project, selection of connector and fast comparator.</td>
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</tr>
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<tr class="even">
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<td>04-09-2015</td>
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<td>Design specification: Bandwidth, I/O levels, DAC choice</td>
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</tr>
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<tr class="odd">
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<td>08-09-2015</td>
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<td>First schematics and reviewing process</td>
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</tr>
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<tr class="even">
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<td>22-09-2015</td>
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<td>Second draw of the schematics and reviewing process</td>
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</tr>
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<tr class="odd">
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<td>15-10-2015</td>
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<td>Final review process</td>
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</tr>
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<tr class="even">
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<td>01-11-2015</td>
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<td>Schematics sent to CERN design office for PCB layout and production of two samples</td>
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</tr>
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<tr class="odd">
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<td>01-01-2016</td>
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<td>Reception of PCB samples and tests</td>
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</tr>
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</tbody>
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</table>
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-----
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27 July 2015
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