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FMC DEL 1ns 4cha
Commit ddc48d05 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl/testbench: use GN4124 BFM from gn4124-core repo

parent bffde3f5
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Showing with 509 additions and 283 deletions
hdl/testbench/spec_wr_top/Manifest.py
View file @ ddc48d05
......@@ -3,18 +3,18 @@ action = "simulation"
target = "xilinx"
vcom_opt="-mixedsvvh l"
fetchto = "../../ip_cores"
include_dirs = ["gn4124_bfm",
"../../include",
include_dirs = ["../../include",
"../../ip_cores/general-cores/modules/wishbone/wb_spi/",
"../../ip_cores/general-cores/sim/",
"../../ip_cores/gn4124-core/hdl/sim/gn4124_bfm/",
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/"]
syn_device = "xc6slx45t"
sim_tool = "modelsim"
sim_top = "main"
top_module = "main"
files = ["main.sv","buildinfo_pkg.vhd"]
files = ["main.sv","buildinfo_pkg.vhd","../../syn/spec/sourceid_spec_fine_delay_top_pkg.vhd"]
modules = {"local": ["../../top/spec", "gn4124_bfm"]}
modules = {"local": ["../../top/spec", "../../ip_cores/gn4124-core/hdl/sim/gn4124_bfm/" ]}
#try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
......
hdl/testbench/spec_wr_top/main.sv
View file @ ddc48d05
......@@ -3,7 +3,8 @@
`include "simdrv_defs.svh"
`include "regs/fd_main_regs.vh"
`include "regs/simple_debug_recorder_regs.vh"
`include "vhd_wishbone_master.svh"
`include "gn4124_bfm.svh"
const uint64_t BASE_WRPC = 'h00c0000;
const uint64_t BASE_FINEDELAY = 'h0010000;
......@@ -136,101 +137,6 @@ class FineDelayDev extends IBusDevice;
endclass // FineDelayDev
/* -----\/----- EXCLUDED -----\/-----
`define ADDR_SDER_CSR 4'h0
`define SDER_CSR_START_OFFSET 0
`define SDER_CSR_START 32'h00000001
`define SDER_CSR_STOP_OFFSET 1
`define SDER_CSR_STOP 32'h00000002
`define SDER_CSR_FORCE_OFFSET 2
`define SDER_CSR_FORCE 32'h00000004
`define SDER_CSR_TRIG_SEL_OFFSET 3
`define SDER_CSR_TRIG_SEL 32'h000000f8
`define SDER_CSR_TRIG_EDGE_OFFSET 8
`define SDER_CSR_TRIG_EDGE 32'h00000100
`define SDER_CSR_TRIGGERED_OFFSET 9
`define SDER_CSR_TRIGGERED 32'h00000200
`define SDER_CSR_TRIG_PRE_SAMPLES_OFFSET 10
`define SDER_CSR_TRIG_PRE_SAMPLES 32'h03fffc00
`define ADDR_SDER_MEM_ADDR 4'h4
`define SDER_MEM_ADDR_ADDR_OFFSET 0
`define SDER_MEM_ADDR_ADDR 32'h0000ffff
`define ADDR_SDER_TRIG_POS 4'h8
`define SDER_TRIG_POS_POS_OFFSET 0
`define SDER_TRIG_POS_POS 32'h0000ffff
`define ADDR_SDER_MEM_DATA 4'hc
`define SDER_MEM_DATA_DATA_OFFSET 0
`define SDER_MEM_DATA_DATA 32'hffffffff
-----/\----- EXCLUDED -----/\----- */
class DebugRecorderDev extends IBusDevice;
function new(CBusAccessor bus, uint64_t base);
super.new(bus, base);
endfunction // new
task automatic configure(int trig_in, int trig_edge, int pre_samples);
uint32_t csr;
csr = (trig_in << `SDER_CSR_TRIG_SEL_OFFSET);
if(trig_edge)
csr|=`SDER_CSR_TRIG_EDGE;
csr |= (pre_samples << `SDER_CSR_TRIG_PRE_SAMPLES_OFFSET);
write32(`ADDR_SDER_CSR, csr);
endtask // configure
task automatic run();
uint32_t csr;
read32(`ADDR_SDER_CSR, csr);
csr |= `SDER_CSR_START;
write32(`ADDR_SDER_CSR, csr);
endtask // run
task automatic readout();
uint32_t csr, pos, mdata, mtag;
int i;
$error("RDS");
forever begin
read32(`ADDR_SDER_CSR, csr);
$display("trig CSR %x", csr);
if( csr & `SDER_CSR_TRIGGERED)
break;
#5us;
end
csr |= `SDER_CSR_STOP;
write32(`ADDR_SDER_CSR, csr);
$display("Readout!");
read32(`ADDR_SDER_TRIG_POS, pos);
$display("Trig pos: %x", pos);
for(i=0;i<10;i++)
begin
write32(`ADDR_SDER_MEM_ADDR, 2*i);
read32(`ADDR_SDER_MEM_DATA, mdata);
write32(`ADDR_SDER_MEM_ADDR, 2*i+1);
read32(`ADDR_SDER_MEM_DATA, mtag);
$display("pos %d %x %x", i, mdata, mtag);
end
endtask // readout
endclass // FineDelayDev
......@@ -249,12 +155,10 @@ module main;
wire clk_sys;
wire rst_sys_n;
wire t_wishbone_master_out sim_wb_in;
wire t_wishbone_master_in sim_wb_out;
IGN4124PCIMaster i_gn4124 ();
spec_fine_delay_top
#(.g_simulation(1)
)
......@@ -274,28 +178,33 @@ module main;
.fmc0_fd_tdc_start_p_i(tdc_start),
.fmc0_fd_tdc_start_n_i(~tdc_start),
.fmc0_fd_pll_status_i(1'b1),
.sim_wb_i(sim_wb_in),
.sim_wb_o(sim_wb_out)
// `GENNUM_WIRE_SPEC_PINS_V2(I_Gennum)
.gn_rst_n_i (i_gn4124.rst_n),
.gn_p2l_clk_n_i (i_gn4124.p2l_clk_n),
.gn_p2l_clk_p_i (i_gn4124.p2l_clk_p),
.gn_p2l_rdy_o (i_gn4124.p2l_rdy),
.gn_p2l_dframe_i (i_gn4124.p2l_dframe),
.gn_p2l_valid_i (i_gn4124.p2l_valid),
.gn_p2l_data_i (i_gn4124.p2l_data),
.gn_p_wr_req_i (i_gn4124.p_wr_req),
.gn_p_wr_rdy_o (i_gn4124.p_wr_rdy),
.gn_rx_error_o (i_gn4124.rx_error),
.gn_l2p_clk_n_o (i_gn4124.l2p_clk_n),
.gn_l2p_clk_p_o (i_gn4124.l2p_clk_p),
.gn_l2p_dframe_o (i_gn4124.l2p_dframe),
.gn_l2p_valid_o (i_gn4124.l2p_valid),
.gn_l2p_edb_o (i_gn4124.l2p_edb),
.gn_l2p_data_o (i_gn4124.l2p_data),
.gn_l2p_rdy_i (i_gn4124.l2p_rdy),
.gn_l_wr_rdy_i (i_gn4124.l_wr_rdy),
.gn_p_rd_d_rdy_i (i_gn4124.p_rd_d_rdy),
.gn_tx_error_i (i_gn4124.tx_error),
.gn_vc_rdy_i (i_gn4124.vc_rdy),
.gn_gpio_b ()
);
IVHDWishboneMaster Host
(
.clk_i (DUT.clk_sys_62m5),
.rst_n_i (DUT.rst_sys_62m5_n));
assign sim_wb_in = Host.out;
assign Host.in = sim_wb_out;
assign clk_sys = DUT.clk_sys_62m5;
assign rst_sys_n = DUT.rst_sys_62m5_n;
......@@ -306,13 +215,11 @@ module main;
CBusAccessor acc ;
FineDelayDev fd;
DebugRecorderDev rec;
acc = Host.get_accessor();
acc = i_gn4124.get_accessor();
fd = new(acc, BASE_FINEDELAY);
rec = new(acc, BASE_FINEDELAY + 'h180 * 4);
while (!rst_sys_n)
@(posedge clk_sys);
......@@ -333,20 +240,12 @@ module main;
fd.set_idelay_taps(20);
#10us;
$stop;
// rec.configure(4, 0, 100);
// rec.run();
acc.read('h1000, rval );
// fd.pll_readl('h1f, tmp);
// $error("done");
$display("R1000 = %x", rval );
// rec.readout();
$stop;
end
......
hdl/testbench/spec_wr_top/wave.do
View file @ ddc48d05
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/clk_ref_0_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/clk_ref_180_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/clk_sys_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/clk_dmtd_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/rst_n_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dcm_reset_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dcm_locked_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/trig_a_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tdc_cal_pulse_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tdc_start_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dmtd_fb_in_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dmtd_fb_out_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dmtd_samp_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/led_trig_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/ext_rst_n_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/pll_status_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/acam_d_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/acam_d_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/acam_d_oen_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/acam_emptyf_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/acam_alutrigger_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/acam_wr_n_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/acam_rd_n_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/acam_start_dis_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/acam_stop_dis_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/spi_cs_dac_n_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/spi_cs_pll_n_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/spi_cs_gpio_n_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/spi_sclk_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/spi_mosi_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/spi_miso_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/delay_len_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/delay_val_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/delay_pulse_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tm_link_up_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tm_time_valid_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tm_cycles_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tm_utc_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tm_clk_aux_lock_en_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tm_clk_aux_locked_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tm_clk_dmtd_locked_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tm_dac_value_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tm_dac_wr_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/owr_en_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/owr_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/i2c_scl_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/i2c_scl_oen_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/i2c_scl_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/i2c_sda_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/i2c_sda_oen_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/i2c_sda_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/fmc_present_n_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/idelay_inc_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/idelay_cal_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/idelay_ce_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/idelay_rst_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/idelay_busy_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/wb_adr_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/wb_dat_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/wb_dat_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/wb_sel_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/wb_cyc_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/wb_stb_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/wb_we_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/wb_ack_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/wb_stall_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/wb_irq_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tdc_seconds_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tdc_cycles_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tdc_frac_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tdc_valid_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/outx_seconds_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/outx_cycles_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/outx_frac_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/outx_valid_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dbg_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tag_frac
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tag_coarse
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tag_utc
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tag_dbg
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tag_valid
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/rbuf_mux_ts
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/rbuf_mux_valid
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/rbuf_mux_valid_masked
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/rbuf_in_ts
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/rbuf_source
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/rbuf_valid
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/rbuf_mux_d
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/rbuf_mux_q
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/master_csync_p1
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/master_csync_utc
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/master_csync_coarse
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/rst_n_sys
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/rst_n_ref
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tsbcr_read_ack
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/fid_read_ack
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/irq_rbuf
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/irq_sync
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/channels
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/chx_delay_idle
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/cnx_out
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/cnx_in
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/slave_in
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/slave_out
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/regs_fromwb
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/regs_towb_csync
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/regs_towb_spi
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/regs_towb_tsu
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/regs_towb_rbuf
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/regs_towb_local
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/regs_towb_dmtd
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/regs_towb
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/owr_en_int
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/owr_int
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dbg_acam
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/gen_cal_pulse
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/cal_pulse_mask
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/cal_pulse_trigger
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tm_dac_val_int
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tcr_rd_ack
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tag_valid_masked
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dmtd_pattern
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/csync_pps
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tdc_cal_pulse
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dmtr_in_rd_ack
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dmtr_out_rd_ack
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/pwm_count
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/pwm_out
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/spi_cs_dac_n
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/spi_cs_pll_n
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/spi_cs_gpio_n
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/spi_mosi
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dmtd_tag_stb
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dbg_tag_in
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dbg_tag_out
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/iodelay_ntaps
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/iodelay_cnt
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/iodelay_div
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/iodelay_tick
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/iodelay_cal_done
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/iodelay_cal_in_progress
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/iodelay_n_taps_load_refclk_p
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/iodelay_busy_synced
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/iodelay_latch_reset
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/clk_125m_pllref_p_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/clk_125m_pllref_n_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/clk_20m_vcxo_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/clk_125m_gtp_n_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/clk_125m_gtp_p_i
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add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_rst_n_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_p2l_clk_n_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_p2l_clk_p_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_p2l_rdy_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_p2l_dframe_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_p2l_valid_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_p2l_data_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_p_wr_req_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_p_wr_rdy_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_rx_error_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_l2p_clk_n_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_l2p_clk_p_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_l2p_dframe_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_l2p_valid_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_l2p_edb_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_l2p_data_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_l2p_rdy_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_l_wr_rdy_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_p_rd_d_rdy_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_tx_error_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_vc_rdy_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_gpio_b
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/fmc0_scl_b
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add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/fmc0_prsnt_m2c_n_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/onewire_b
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/spi_sclk_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/spi_ncs_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/spi_mosi_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/spi_miso_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/pcbrev_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/led_act_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/led_link_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/button1_n_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/uart_rxd_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/uart_txd_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/plldac_sclk_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/plldac_din_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/pll25dac_cs_n_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/pll20dac_cs_n_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_txp_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_txn_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_rxp_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_rxn_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_mod_def0_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_mod_def1_b
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_mod_def2_b
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_rate_select_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_tx_fault_i
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add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_los_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_a_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_ba_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_cas_n_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_ck_n_o
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add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_cke_o
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add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_ldm_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_ldqs_n_b
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_ldqs_p_b
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_odt_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_ras_n_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_reset_n_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_rzq_b
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_udm_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_udqs_n_b
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_udqs_p_b
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_we_n_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_dma_clk_i
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add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_dma_wb_cyc_i
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add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_dma_wb_sel_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_dma_wb_we_i
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_dma_wb_dat_i
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add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_dma_wb_dat_o
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add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/clk_dmtd_125m_o
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/clk_62m5_sys_o
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add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/clk_125m_ref_o
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add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wrs_rx_data_o
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add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/tm_tai_o
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add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/therm_id_wack
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/therm_id_rack
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/fmc_i2c_re
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/fmc_i2c_wt
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/fmc_i2c_rt
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/fmc_i2c_tr
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/fmc_i2c_wack
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/fmc_i2c_rack
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/flash_spi_re
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/flash_spi_wt
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/flash_spi_rt
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/flash_spi_tr
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/flash_spi_wack
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/flash_spi_rack
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/dma_re
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/dma_wt
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/dma_rt
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/dma_tr
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/dma_wack
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/dma_rack
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/vic_re
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/vic_wt
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/vic_rt
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/vic_tr
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/vic_wack
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/vic_rack
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/buildinfo_rack
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/buildinfo_re
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/wrc_regs_re
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/wrc_regs_wt
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/wrc_regs_rt
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/wrc_regs_tr
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/wrc_regs_wack
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/wrc_regs_rack
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/reg_rdat_int
add wave -noupdate -group Devs /main/DUT/inst_spec_base/inst_devs/rd_ack1_int
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/clk_sys_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/clk_dmtd_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/clk_ref_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/clk_aux_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/clk_ext_mul_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/clk_ext_mul_locked_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/clk_ext_stopped_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/clk_ext_rst_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/clk_ext_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/pps_ext_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/rst_n_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/dac_hpll_load_p1_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/dac_hpll_data_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/dac_dpll_load_p1_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/dac_dpll_data_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_ref_clk_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_tx_data_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_tx_k_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_tx_disparity_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_tx_enc_err_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_rx_data_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_rx_rbclk_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_rx_k_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_rx_enc_err_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_rx_bitslide_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_rst_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_rdy_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_loopen_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_loopen_vec_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_tx_prbs_sel_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_sfp_tx_fault_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_sfp_los_i
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add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_lpc_stat_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_lpc_ctrl_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy8_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy8_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy16_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy16_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/led_act_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/led_link_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/scl_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/scl_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/sda_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/sda_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/sfp_scl_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/sfp_scl_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/sfp_sda_o
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add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/btn2_i
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add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/spi_ncs_o
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add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/uart_txd_o
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add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/wb_stb_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/wb_ack_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/wb_err_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/wb_rty_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/wb_stall_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/aux_adr_o
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add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_snk_adr_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_snk_dat_i
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add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_snk_cyc_i
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add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_src_adr_o
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add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_src_cyc_o
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add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_src_err_i
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add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/txtsu_frame_id_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/txtsu_ts_value_o
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add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/tm_time_valid_o
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add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/tm_cycles_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/pps_csync_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/pps_valid_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/pps_p_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/pps_led_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/rst_aux_n_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/link_ok_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/aux_diag_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/aux_diag_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/rst_wrc_n
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/rst_net_n
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/rst_net_resync_ref_n
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/rst_net_resync_ext_n
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/rst_net_resync_dmtd_n
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/rst_net_resync_rxclk_n
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/rst_net_resync_txclk_n
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/s_pps_csync
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/pps_valid
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ppsg_link_ok
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ppsg_wb_in
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ppsg_wb_out
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_rx_clk
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_tx_clk
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/spll_wb_in
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/spll_wb_out
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_txtsu_port_id
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_txtsu_frame_id
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_txtsu_ts_value
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_txtsu_ts_incorrect
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_txtsu_stb
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_txtsu_ack
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_led_link
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_rst
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/mnic_mem_data_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/mnic_mem_addr_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/mnic_mem_wr_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/mnic_txtsu_ack
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/mnic_txtsu_stb
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/dpram_wbb_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/periph_slave_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/periph_slave_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/sysc_in_regs
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/sysc_out_regs
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/secbar_master_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/secbar_master_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/cbar_slave_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/cbar_slave_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/cbar_master_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/cbar_master_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_wb_in
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_wb_out
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/hpll_auxout
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/dmpll_auxout
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/clk_ref_slv
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/clk_rx_slv
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/s_dummy_addr
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/softpll_irq
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/lm32_irq_slv
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_wb_in
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_wb_out
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/minic_wb_in
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/minic_wb_out
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_src_out
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_src_in
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_snk_out
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_snk_in
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/mux_src_out
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/mux_src_in
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/mux_snk_out
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/mux_snk_in
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/mux_class
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/spll_out_locked
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/dac_dpll_data
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/dac_dpll_sel
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/dac_dpll_load_p1
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/clk_fb
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/out_enable
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1471987790 fs} 0}
configure wave -namecolwidth 150
WaveRestoreCursors {{Cursor 1} {25805352090 fs} 0}
configure wave -namecolwidth 339
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
......@@ -160,4 +487,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {1167510930 fs} {3176489070 fs}
WaveRestoreZoom {24701267760 fs} {27643595600 fs}
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