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FMC DEL 1ns 4cha
Commit be2a5d7b authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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rtl: expose g_fmc_slot_id parameter in component declaration

parent fbf84871
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hdl/rtl/fine_delay_pkg.vhd
View file @ be2a5d7b
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN -- Company : CERN
-- Created : 2011-08-24 -- Created : 2011-08-24
-- Last update: 2019-03-21 -- Last update: 2019-10-15
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -356,7 +356,8 @@ package fine_delay_pkg is ...@@ -356,7 +356,8 @@ package fine_delay_pkg is
g_simulation : boolean := false; g_simulation : boolean := false;
g_with_direct_timestamp_io : boolean := false; g_with_direct_timestamp_io : boolean := false;
g_interface_mode : t_wishbone_interface_mode; g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity); g_address_granularity : t_wishbone_address_granularity;
g_fmc_slot_id : integer := 0);
port ( port (
clk_ref_0_i : in std_logic; clk_ref_0_i : in std_logic;
clk_ref_180_i : in std_logic; clk_ref_180_i : in std_logic;
......
hdl/syn/svec/Manifest.py
View file @ be2a5d7b
board = "svec"
target = "xilinx" target = "xilinx"
action = "synthesis" action = "synthesis"
fetchto = "../../ip_cores" syn_device = "xc6slx150t"
syn_grade = "-3"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900" syn_package = "fgg900"
syn_top = "svec_top" syn_top = "svec_top"
syn_project = "svec_fine_delay.xise" syn_project = "svec_fine_delay.xise"
syn_tool="ise" syn_tool = "ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
files = [
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/svec",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
svec_base_ucf = ['wr', 'led', 'gpio']
#files = [ "wrc-release.ram" ] ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
modules = { "local" : [ "../../top/svec", "../../platform" ] }
hdl/syn/svec/svec_fine_delay.xise
View file @ be2a5d7b
...@@ -15,648 +15,920 @@ ...@@ -15,648 +15,920 @@
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/> <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files> <files>
<file xil_pn:name="../../rtl/fd_spi_dac_arbiter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../platform/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="125"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_spartan6_icon.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_spartan6_ila.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../platform/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="116"/> <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="146"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="151"/> <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="135"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="136"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="84"/> <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="95"/> <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="138"/> <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="152"/> <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file> </file>
<file xil_pn:name="../../top/svec/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="147"/> <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file> </file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/rtl/vme64x_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="118"/> <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="63"/> <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="55"/> <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/> <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="112"/> <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/vme64x-core/hdl/rtl/xvme64x_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="145"/> <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="115"/> <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="36"/> <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../rtl/fd_reset_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="154"/> <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
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<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="153"/> <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
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<file xil_pn:name="../../ip_cores/vme64x-core/hdl/rtl/vme_irq_controller.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="141"/> <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_metadata/xwb_metadata.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="83"/> <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
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<file xil_pn:name="../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="82"/> <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
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<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="98"/> <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
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<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
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<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/> <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
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<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../platform/fd_ddr_pll.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
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<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
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<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="228"/>
<association xil_pn:name="Implementation" xil_pn:seqID="228"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="229"/>
<association xil_pn:name="Implementation" xil_pn:seqID="229"/>
</file>
<file xil_pn:name="../../ip_cores/svec/hdl/syn/common/svec_base_led.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="230"/>
</file>
<file xil_pn:name="../../ip_cores/svec/hdl/syn/common/svec_base_common.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="231"/>
</file>
<file xil_pn:name="../../ip_cores/svec/hdl/syn/common/svec_base_wr.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="232"/>
</file>
<file xil_pn:name="../../top/svec/svec_top.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="233"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC"> <file xil_pn:name="../../ip_cores/svec/hdl/syn/common/svec_base_gpio.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="234"/>
</file> </file>
</files> </files>
...@@ -724,8 +996,8 @@ ...@@ -724,8 +996,8 @@
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/> <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/> <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
...@@ -773,7 +1045,7 @@ ...@@ -773,7 +1045,7 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|svec_top|rtl" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|svec_top|arch" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../top/svec/svec_top.vhd" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top File" xil_pn:value="../../top/svec/svec_top.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/svec_top" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/svec_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
...@@ -791,9 +1063,6 @@ ...@@ -791,9 +1063,6 @@
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
...@@ -845,7 +1114,6 @@ ...@@ -845,7 +1114,6 @@
<property xil_pn:name="Package" xil_pn:value="fgg900" xil_pn:valueState="non-default"/> <property xil_pn:name="Package" xil_pn:value="fgg900" xil_pn:valueState="non-default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/> <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/> <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
...@@ -953,7 +1221,6 @@ ...@@ -953,7 +1221,6 @@
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
...@@ -976,14 +1243,18 @@ ...@@ -976,14 +1243,18 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2019-03-21T10:11:58" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2019-10-15T19:03:10" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="744678E6738EAE810F46A2D7D6BC0BB9" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A742620B6A2C3C8714987C2A56A0A68D" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties> </properties>
<bindings> <bindings>
<binding xil_pn:location="/svec_top" xil_pn:name="../../ip_cores/svec/hdl/syn/common/svec_base_led.ucf"/>
<binding xil_pn:location="/svec_top" xil_pn:name="../../ip_cores/svec/hdl/syn/common/svec_base_common.ucf"/>
<binding xil_pn:location="/svec_top" xil_pn:name="../../ip_cores/svec/hdl/syn/common/svec_base_wr.ucf"/>
<binding xil_pn:location="/svec_top" xil_pn:name="../../top/svec/svec_top.ucf"/> <binding xil_pn:location="/svec_top" xil_pn:name="../../top/svec/svec_top.ucf"/>
<binding xil_pn:location="/svec_top" xil_pn:name="../../ip_cores/svec/hdl/syn/common/svec_base_gpio.ucf"/>
</bindings> </bindings>
<libraries/> <libraries/>
...@@ -996,6 +1267,8 @@ ...@@ -996,6 +1267,8 @@
<!-- project is analyzed based on files automatically identified as --> <!-- project is analyzed based on files automatically identified as -->
<!-- include files. --> <!-- include files. -->
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles> </autoManagedFiles>
</project> </project>
hdl/top/svec/Manifest.py
View file @ be2a5d7b
files = [ "synthesis_descriptor.vhd", "svec_top.vhd", "svec_top.ucf", "bicolor_led_ctrl.vhd", "bicolor_led_ctrl_pkg.vhd" ] files = ["svec_top.vhd", "svec_top.ucf"]
fetchto = "../../ip_cores" fetchto = "../../ip_cores"
modules = { modules = {
"local" : ["../../rtl", "../../platform" ], "local" : [
"git" : [ "git://ohwr.org/hdl-core-lib/wr-cores.git", "../../rtl",
"git://ohwr.org/hdl-core-lib/vme64x-core.git" ] "../../platform",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores",
"../../ip_cores/wr-cores/board/svec",
"../../ip_cores/vme64x-core",
"../../ip_cores/svec",
"../../ip_cores/ddr3-sp6-core"
]
} }
hdl/top/svec/svec_top.ucf
View file @ be2a5d7b
#=============================================================================== # <ucfgen_start>
# IO Location Constraints
#===============================================================================
#----------------------------------------
# VME interface
#----------------------------------------
NET "vme_write_n_i" LOC = R1;
NET "vme_rst_n_i" LOC = P4;
#NET "vme_sysclk_i" LOC = P3;
NET "vme_retry_oe_o" LOC = R4;
NET "vme_retry_n_o" LOC = AB2;
NET "vme_lword_n_b" LOC = M7;
NET "vme_iackout_n_o" LOC = N3;
NET "vme_iackin_n_i" LOC = P7;
NET "vme_iack_n_i" LOC = N1;
NET "vme_ga_i[5]" LOC = M6;
NET "vme_dtack_oe_o" LOC = T1;
NET "vme_dtack_n_o" LOC = R5;
NET "vme_ds_n_i[1]" LOC = Y7;
NET "vme_ds_n_i[0]" LOC = Y6;
NET "vme_data_oe_n_o" LOC = P1;
NET "vme_data_dir_o" LOC = P2;
NET "vme_berr_o" LOC = R3;
NET "vme_as_n_i" LOC = P6;
NET "vme_addr_oe_n_o" LOC = N4;
NET "vme_addr_dir_o" LOC = N5;
NET "vme_irq_n_o[6]" LOC = R7;
NET "vme_irq_n_o[5]" LOC = AH2;
NET "vme_irq_n_o[4]" LOC = AF2;
NET "vme_irq_n_o[3]" LOC = N9;
NET "vme_irq_n_o[2]" LOC = N10;
NET "vme_irq_n_o[1]" LOC = AH4;
NET "vme_irq_n_o[0]" LOC = AG4;
NET "vme_ga_i[4]" LOC = V9;
NET "vme_ga_i[3]" LOC = V10;
NET "vme_ga_i[2]" LOC = AJ1;
NET "vme_ga_i[1]" LOC = AH1;
NET "vme_ga_i[0]" LOC = V7;
NET "vme_data_b[31]" LOC = AK3;
NET "vme_data_b[30]" LOC = AH3;
NET "vme_data_b[29]" LOC = T8;
NET "vme_data_b[28]" LOC = T9;
NET "vme_data_b[27]" LOC = AK4;
NET "vme_data_b[26]" LOC = AJ4;
NET "vme_data_b[25]" LOC = W6;
NET "vme_data_b[24]" LOC = W7;
NET "vme_data_b[23]" LOC = AB6;
NET "vme_data_b[22]" LOC = AB7;
NET "vme_data_b[21]" LOC = W9;
NET "vme_data_b[20]" LOC = W10;
NET "vme_data_b[19]" LOC = AK5;
NET "vme_data_b[18]" LOC = AH5;
NET "vme_data_b[17]" LOC = AD6;
NET "vme_data_b[16]" LOC = AC6;
NET "vme_data_b[15]" LOC = AA6;
NET "vme_data_b[14]" LOC = AA7;
NET "vme_data_b[13]" LOC = T6;
NET "vme_data_b[12]" LOC = T7;
NET "vme_data_b[11]" LOC = AG5;
NET "vme_data_b[10]" LOC = AE5;
NET "vme_data_b[9]" LOC = Y11;
NET "vme_data_b[8]" LOC = W11;
NET "vme_data_b[7]" LOC = AF6;
NET "vme_data_b[6]" LOC = AE6;
NET "vme_data_b[5]" LOC = Y8;
NET "vme_data_b[4]" LOC = Y9;
NET "vme_data_b[3]" LOC = AE7;
NET "vme_data_b[2]" LOC = AD7;
NET "vme_data_b[1]" LOC = AA9;
NET "vme_data_b[0]" LOC = AA10;
NET "vme_am_i[5]" LOC = V8;
NET "vme_am_i[4]" LOC = AG3;
NET "vme_am_i[3]" LOC = AF3;
NET "vme_am_i[2]" LOC = AF4;
NET "vme_am_i[1]" LOC = AE4;
NET "vme_am_i[0]" LOC = AK2;
NET "vme_addr_b[31]" LOC = T2;
NET "vme_addr_b[30]" LOC = T3;
NET "vme_addr_b[29]" LOC = T4;
NET "vme_addr_b[28]" LOC = U1;
NET "vme_addr_b[27]" LOC = U3;
NET "vme_addr_b[26]" LOC = U4;
NET "vme_addr_b[25]" LOC = U5;
NET "vme_addr_b[24]" LOC = V1;
NET "vme_addr_b[23]" LOC = V2;
NET "vme_addr_b[22]" LOC = W1;
NET "vme_addr_b[21]" LOC = W3;
NET "vme_addr_b[20]" LOC = AA4;
NET "vme_addr_b[19]" LOC = AA5;
NET "vme_addr_b[18]" LOC = Y1;
NET "vme_addr_b[17]" LOC = Y2;
NET "vme_addr_b[16]" LOC = Y3;
NET "vme_addr_b[15]" LOC = Y4;
NET "vme_addr_b[14]" LOC = AC1;
NET "vme_addr_b[13]" LOC = AC3;
NET "vme_addr_b[12]" LOC = AD1;
NET "vme_addr_b[11]" LOC = AD2;
NET "vme_addr_b[10]" LOC = AB3;
NET "vme_addr_b[9]" LOC = AB4;
NET "vme_addr_b[8]" LOC = AD3;
NET "vme_addr_b[7]" LOC = AD4;
NET "vme_addr_b[6]" LOC = AC4;
NET "vme_addr_b[5]" LOC = AC5;
NET "vme_addr_b[4]" LOC = N7;
NET "vme_addr_b[3]" LOC = N8;
NET "vme_addr_b[2]" LOC = AE1;
NET "vme_addr_b[1]" LOC = AE3;
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "rst_n_i" LOC = AD28;
NET "clk_20m_vcxo_i" LOC = V26;
NET "clk_125m_pllref_n_i" LOC = AB30;
NET "clk_125m_pllref_p_i" LOC = AB28;
#----------------------------------------
# SFP slot
#----------------------------------------
NET "sfp_txp_o" LOC = B23;
NET "sfp_txn_o" LOC = A23;
NET "sfp_rxp_i" LOC = D22;
NET "sfp_rxn_i" LOC = C22;
NET "clk_125m_gtp_p_i" LOC = B19;
NET "clk_125m_gtp_n_i" LOC = A19;
NET "sfp_los_i" LOC = W25;
NET "sfp_mod_def0_b" LOC = Y26;
NET "sfp_mod_def1_b" LOC = Y27;
NET "sfp_mod_def2_b" LOC = AA24;
#NET "sfp_rate_select_o" LOC = W24;
NET "sfp_tx_disable_o" LOC = AA25;
NET "sfp_tx_fault_i" LOC = AA27;
#----------------------------------------
# Clock controls
#----------------------------------------\
NET "pll20dac_din_o" LOC = U28;
NET "pll20dac_sclk_o" LOC = AA28;
NET "pll20dac_sync_n_o" LOC = N28;
NET "pll25dac_din_o" LOC = P25;
NET "pll25dac_sclk_o" LOC = N27;
NET "pll25dac_sync_n_o" LOC = P26;
#----------------------------------------
# UART
#----------------------------------------
NET "uart_txd_o" LOC = U27;
NET "uart_rxd_i" LOC = U25;
#NET "fp_ledn_o[0]" LOC = AD27;
#NET "fp_ledn_o[1]" LOC = AD26;
#NET "fp_ledn_o[2]" LOC = AC28;
#NET "fp_ledn_o[3]" LOC = AC27;
#NET "fp_ledn_o[4]" LOC = AE27;
#NET "fp_ledn_o[5]" LOC = AE30;
#NET "fp_ledn_o[6]" LOC = AF28;
#NET "fp_ledn_o[7]" LOC = AE28;
#NET "fp_ledn_o[0]" IOSTANDARD = "LVCMOS33";
#NET "fp_ledn_o[1]" IOSTANDARD = "LVCMOS33";
#NET "fp_ledn_o[2]" IOSTANDARD = "LVCMOS33";
#NET "fp_ledn_o[3]" IOSTANDARD = "LVCMOS33";
#NET "fp_ledn_o[4]" IOSTANDARD = "LVCMOS33";
#NET "fp_ledn_o[5]" IOSTANDARD = "LVCMOS33";
#NET "fp_ledn_o[6]" IOSTANDARD = "LVCMOS33";
#NET "fp_ledn_o[7]" IOSTANDARD = "LVCMOS33";
#---------------------------------------- # This section has bee generated automatically by ucfgen.py. Do not hand-modify if not really necessary.
# 1-wire thermoeter + unique ID # ucfgen pin assignments for mezzanine fmc-delay-v4 slot 0
#---------------------------------------- NET "fmc0_fd_clk_ref_p_i" LOC = "E16";
NET "tempid_dq_b" LOC = AC30; NET "fmc0_fd_clk_ref_p_i" IOSTANDARD = "LVDS_25";
NET "fmc0_fd_clk_ref_n_i" LOC = "D16";
NET "fmc0_fd_clk_ref_n_i" IOSTANDARD = "LVDS_25";
NET "fmc0_fd_tdc_start_p_i" LOC = "H15";
NET "fmc0_fd_tdc_start_p_i" IOSTANDARD = "LVDS_25";
NET "fmc0_fd_tdc_start_n_i" LOC = "G15";
NET "fmc0_fd_tdc_start_n_i" IOSTANDARD = "LVDS_25";
NET "fmc0_fd_delay_len_o[3]" LOC = "G10";
NET "fmc0_fd_delay_len_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_len_o[3]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[3]" DRIVE = 4;
NET "fmc0_fd_delay_len_o[2]" LOC = "F10";
NET "fmc0_fd_delay_len_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_len_o[2]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[2]" DRIVE = 4;
NET "fmc0_fd_delay_len_o[1]" LOC = "E9";
NET "fmc0_fd_delay_len_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_len_o[1]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[1]" DRIVE = 4;
NET "fmc0_fd_delay_len_o[0]" LOC = "F9";
NET "fmc0_fd_delay_len_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_len_o[0]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[0]" DRIVE = 4;
NET "fmc0_fd_delay_pulse_o[3]" LOC = "F12";
NET "fmc0_fd_delay_pulse_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_pulse_o[1]" LOC = "E11";
NET "fmc0_fd_delay_pulse_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_pulse_o[2]" LOC = "G12";
NET "fmc0_fd_delay_pulse_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_pulse_o[0]" LOC = "F11";
NET "fmc0_fd_delay_pulse_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[3]" LOC = "J12";
NET "fmc0_fd_delay_val_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[3]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[3]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[1]" LOC = "H11";
NET "fmc0_fd_delay_val_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[1]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[1]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[7]" LOC = "L11";
NET "fmc0_fd_delay_val_o[7]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[7]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[7]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[5]" LOC = "J13";
NET "fmc0_fd_delay_val_o[5]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[5]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[5]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[9]" LOC = "L12";
NET "fmc0_fd_delay_val_o[9]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[9]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[9]" DRIVE = 4;
NET "fmc0_fd_spi_mosi_o" LOC = "M13";
NET "fmc0_fd_spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_spi_sclk_o" LOC = "L14";
NET "fmc0_fd_spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_oe_n_o" LOC = "M15";
NET "fmc0_fd_tdc_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_start_dis_o" LOC = "F13";
NET "fmc0_fd_tdc_start_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_spi_cs_gpio_n_o" LOC = "F15";
NET "fmc0_fd_spi_cs_gpio_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_cal_pulse_o" LOC = "G14";
NET "fmc0_fd_tdc_cal_pulse_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_dmtd_clk_o" LOC = "J14";
NET "fmc0_fd_dmtd_clk_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_wr_n_o" LOC = "B15";
NET "fmc0_fd_tdc_wr_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_alutrigger_o" LOC = "F19";
NET "fmc0_fd_tdc_alutrigger_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_led_trig_o" LOC = "H16";
NET "fmc0_fd_led_trig_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[26]" LOC = "F17";
NET "fmc0_fd_tdc_d_b[26]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[24]" LOC = "G18";
NET "fmc0_fd_tdc_d_b[24]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[20]" LOC = "F21";
NET "fmc0_fd_tdc_d_b[20]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[22]" LOC = "G20";
NET "fmc0_fd_tdc_d_b[22]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[18]" LOC = "L21";
NET "fmc0_fd_tdc_d_b[18]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[16]" LOC = "M20";
NET "fmc0_fd_tdc_d_b[16]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[10]" LOC = "F23";
NET "fmc0_fd_tdc_d_b[10]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[14]" LOC = "G22";
NET "fmc0_fd_tdc_d_b[14]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[8]" LOC = "B25";
NET "fmc0_fd_tdc_d_b[8]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[12]" LOC = "M19";
NET "fmc0_fd_tdc_d_b[12]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[3]" LOC = "D24";
NET "fmc0_fd_tdc_d_b[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[5]" LOC = "E25";
NET "fmc0_fd_tdc_d_b[5]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[7]" LOC = "J22";
NET "fmc0_fd_tdc_d_b[7]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[2]" LOC = "H21";
NET "fmc0_fd_tdc_d_b[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_trig_a_i" LOC = "C16";
NET "fmc0_fd_trig_a_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[2]" LOC = "H12";
NET "fmc0_fd_delay_val_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[2]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[2]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[0]" LOC = "G11";
NET "fmc0_fd_delay_val_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[0]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[0]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[6]" LOC = "K11";
NET "fmc0_fd_delay_val_o[6]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[6]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[6]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[4]" LOC = "H13";
NET "fmc0_fd_delay_val_o[4]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[4]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[4]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[8]" LOC = "K12";
NET "fmc0_fd_delay_val_o[8]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[8]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[8]" DRIVE = 4;
NET "fmc0_fd_spi_miso_i" LOC = "L13";
NET "fmc0_fd_spi_miso_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_spi_cs_pll_n_o" LOC = "K14";
NET "fmc0_fd_spi_cs_pll_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_spi_cs_dac_n_o" LOC = "K15";
NET "fmc0_fd_spi_cs_dac_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_stop_dis_o" LOC = "E13";
NET "fmc0_fd_tdc_stop_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_ext_rst_n_o" LOC = "E15";
NET "fmc0_fd_ext_rst_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_pll_status_i" LOC = "F14";
NET "fmc0_fd_pll_status_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_dmtd_fb_out_i" LOC = "H14";
NET "fmc0_fd_dmtd_fb_out_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_rd_n_o" LOC = "A15";
NET "fmc0_fd_tdc_rd_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_emptyf_i" LOC = "E19";
NET "fmc0_fd_tdc_emptyf_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_onewire_b" LOC = "G16";
NET "fmc0_fd_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[27]" LOC = "E17";
NET "fmc0_fd_tdc_d_b[27]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[25]" LOC = "F18";
NET "fmc0_fd_tdc_d_b[25]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[21]" LOC = "E21";
NET "fmc0_fd_tdc_d_b[21]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[23]" LOC = "F20";
NET "fmc0_fd_tdc_d_b[23]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[19]" LOC = "K21";
NET "fmc0_fd_tdc_d_b[19]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[17]" LOC = "L20";
NET "fmc0_fd_tdc_d_b[17]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[11]" LOC = "E23";
NET "fmc0_fd_tdc_d_b[11]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[15]" LOC = "F22";
NET "fmc0_fd_tdc_d_b[15]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[9]" LOC = "A25";
NET "fmc0_fd_tdc_d_b[9]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[13]" LOC = "L19";
NET "fmc0_fd_tdc_d_b[13]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[1]" LOC = "C24";
NET "fmc0_fd_tdc_d_b[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[4]" LOC = "D25";
NET "fmc0_fd_tdc_d_b[4]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[6]" LOC = "H22";
NET "fmc0_fd_tdc_d_b[6]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[0]" LOC = "G21";
NET "fmc0_fd_tdc_d_b[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_dmtd_fb_in_i" LOC = "A16";
NET "fmc0_fd_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";
#=============================================================================== # ucfgen pin assignments for mezzanine fmc-delay-v4 slot 1
# IO Standard Constraints NET "fmc1_fd_clk_ref_p_i" LOC = "AH16";
#=============================================================================== NET "fmc1_fd_clk_ref_p_i" IOSTANDARD = "LVDS_25";
#---------------------------------------- NET "fmc1_fd_clk_ref_n_i" LOC = "AK16";
# VME interface NET "fmc1_fd_clk_ref_n_i" IOSTANDARD = "LVDS_25";
#---------------------------------------- NET "fmc1_fd_tdc_start_p_i" LOC = "AF16";
NET "vme_write_n_i" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_start_p_i" IOSTANDARD = "LVDS_25";
NET "vme_rst_n_i" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_start_n_i" LOC = "AG16";
#NET "vme_sysclk_i" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_start_n_i" IOSTANDARD = "LVDS_25";
NET "vme_retry_oe_o" IOSTANDARD = "LVCMOS33";
NET "vme_retry_n_o" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_len_o[3]" LOC = "AB21";
NET "vme_lword_n_b" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_len_o[3]" IOSTANDARD = "LVCMOS25";
NET "vme_iackout_n_o" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_len_o[3]" SLEW = SLOW;
NET "vme_iackin_n_i" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_len_o[3]" DRIVE = 4;
NET "vme_iack_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[5]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_len_o[2]" LOC = "AC21";
NET "vme_dtack_oe_o" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_len_o[2]" IOSTANDARD = "LVCMOS25";
NET "vme_dtack_n_o" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_len_o[2]" SLEW = SLOW;
NET "vme_ds_n_i[1]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_len_o[2]" DRIVE = 4;
NET "vme_ds_n_i[0]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_len_o[1]" LOC = "AD24";
NET "vme_data_oe_n_o" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_len_o[1]" IOSTANDARD = "LVCMOS25";
NET "vme_data_dir_o" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_len_o[1]" SLEW = SLOW;
NET "vme_berr_o" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_len_o[1]" DRIVE = 4;
NET "vme_as_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_addr_oe_n_o" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_len_o[0]" LOC = "AC24";
NET "vme_addr_dir_o" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_len_o[0]" IOSTANDARD = "LVCMOS25";
NET "vme_irq_n_o[6]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_len_o[0]" SLEW = SLOW;
NET "vme_irq_n_o[5]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_len_o[0]" DRIVE = 4;
NET "vme_irq_n_o[4]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[3]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_pulse_o[3]" LOC = "AE22";
NET "vme_irq_n_o[2]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_pulse_o[3]" IOSTANDARD = "LVCMOS25";
NET "vme_irq_n_o[1]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_pulse_o[1]" LOC = "AD17";
NET "vme_irq_n_o[0]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_pulse_o[1]" IOSTANDARD = "LVCMOS25";
NET "vme_ga_i[4]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_pulse_o[2]" LOC = "AD22";
NET "vme_ga_i[3]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_pulse_o[2]" IOSTANDARD = "LVCMOS25";
NET "vme_ga_i[2]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_pulse_o[0]" LOC = "AB17";
NET "vme_ga_i[1]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_pulse_o[0]" IOSTANDARD = "LVCMOS25";
NET "vme_ga_i[0]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_val_o[3]" LOC = "AA19";
NET "vme_data_b[31]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_val_o[3]" IOSTANDARD = "LVCMOS25";
NET "vme_data_b[30]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_val_o[3]" SLEW = SLOW;
NET "vme_data_b[29]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_val_o[3]" DRIVE = 4;
NET "vme_data_b[28]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[27]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_val_o[1]" LOC = "W19";
NET "vme_data_b[26]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_val_o[1]" IOSTANDARD = "LVCMOS25";
NET "vme_data_b[25]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_val_o[1]" SLEW = SLOW;
NET "vme_data_b[24]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_val_o[1]" DRIVE = 4;
NET "vme_data_b[23]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_val_o[7]" LOC = "Y21";
NET "vme_data_b[22]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_val_o[7]" IOSTANDARD = "LVCMOS25";
NET "vme_data_b[21]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_val_o[7]" SLEW = SLOW;
NET "vme_data_b[20]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_val_o[7]" DRIVE = 4;
NET "vme_data_b[19]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_val_o[5]" LOC = "W20";
NET "vme_data_b[18]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_val_o[5]" IOSTANDARD = "LVCMOS25";
NET "vme_data_b[17]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_val_o[5]" SLEW = SLOW;
NET "vme_data_b[16]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_val_o[5]" DRIVE = 4;
NET "vme_data_b[15]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_val_o[9]" LOC = "AA22";
NET "vme_data_b[14]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_val_o[9]" IOSTANDARD = "LVCMOS25";
NET "vme_data_b[13]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_val_o[9]" SLEW = SLOW;
NET "vme_data_b[12]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_delay_val_o[9]" DRIVE = 4;
NET "vme_data_b[11]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[10]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_spi_mosi_o" LOC = "AB20";
NET "vme_data_b[9]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "vme_data_b[8]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_spi_sclk_o" LOC = "AC19";
NET "vme_data_b[7]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "vme_data_b[6]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_oe_n_o" LOC = "AF25";
NET "vme_data_b[5]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "vme_data_b[4]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_start_dis_o" LOC = "AE24";
NET "vme_data_b[3]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_start_dis_o" IOSTANDARD = "LVCMOS25";
NET "vme_data_b[2]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_spi_cs_gpio_n_o" LOC = "AE19";
NET "vme_data_b[1]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_spi_cs_gpio_n_o" IOSTANDARD = "LVCMOS25";
NET "vme_data_b[0]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_cal_pulse_o" LOC = "AE23";
NET "vme_am_i[5]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_cal_pulse_o" IOSTANDARD = "LVCMOS25";
NET "vme_am_i[4]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_dmtd_clk_o" LOC = "AE21";
NET "vme_am_i[3]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_dmtd_clk_o" IOSTANDARD = "LVCMOS25";
NET "vme_am_i[2]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_wr_n_o" LOC = "AC16";
NET "vme_am_i[1]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_wr_n_o" IOSTANDARD = "LVCMOS25";
NET "vme_am_i[0]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_alutrigger_o" LOC = "AB14";
NET "vme_addr_b[31]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_alutrigger_o" IOSTANDARD = "LVCMOS25";
NET "vme_addr_b[30]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_led_trig_o" LOC = "Y17";
NET "vme_addr_b[29]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_led_trig_o" IOSTANDARD = "LVCMOS25";
NET "vme_addr_b[28]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[26]" LOC = "Y15";
NET "vme_addr_b[27]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[26]" IOSTANDARD = "LVCMOS25";
NET "vme_addr_b[26]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[24]" LOC = "AC15";
NET "vme_addr_b[25]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[24]" IOSTANDARD = "LVCMOS25";
NET "vme_addr_b[24]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[20]" LOC = "AE15";
NET "vme_addr_b[23]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[20]" IOSTANDARD = "LVCMOS25";
NET "vme_addr_b[22]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[22]" LOC = "Y16";
NET "vme_addr_b[21]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[22]" IOSTANDARD = "LVCMOS25";
NET "vme_addr_b[20]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[18]" LOC = "Y14";
NET "vme_addr_b[19]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[18]" IOSTANDARD = "LVCMOS25";
NET "vme_addr_b[18]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[16]" LOC = "W14";
NET "vme_addr_b[17]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[16]" IOSTANDARD = "LVCMOS25";
NET "vme_addr_b[16]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[10]" LOC = "AB12";
NET "vme_addr_b[15]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[10]" IOSTANDARD = "LVCMOS25";
NET "vme_addr_b[14]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[14]" LOC = "AD12";
NET "vme_addr_b[13]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[14]" IOSTANDARD = "LVCMOS25";
NET "vme_addr_b[12]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[8]" LOC = "AD10";
NET "vme_addr_b[11]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[8]" IOSTANDARD = "LVCMOS25";
NET "vme_addr_b[10]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[12]" LOC = "AE11";
NET "vme_addr_b[9]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[12]" IOSTANDARD = "LVCMOS25";
NET "vme_addr_b[8]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[3]" LOC = "AJ15";
NET "vme_addr_b[7]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[3]" IOSTANDARD = "LVCMOS25";
NET "vme_addr_b[6]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[5]" LOC = "AE13";
NET "vme_addr_b[5]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[5]" IOSTANDARD = "LVCMOS25";
NET "vme_addr_b[4]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[7]" LOC = "AC11";
NET "vme_addr_b[3]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[7]" IOSTANDARD = "LVCMOS25";
NET "vme_addr_b[2]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[2]" LOC = "AG8";
NET "vme_addr_b[1]" IOSTANDARD = "LVCMOS33"; NET "fmc1_fd_tdc_d_b[2]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_trig_a_i" LOC = "AJ17";
NET "fmc1_fd_trig_a_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[2]" LOC = "AB19";
NET "fmc1_fd_delay_val_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[2]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[2]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[0]" LOC = "Y19";
NET "fmc1_fd_delay_val_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[0]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[0]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[6]" LOC = "AA21";
NET "fmc1_fd_delay_val_o[6]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[6]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[6]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[4]" LOC = "Y20";
NET "fmc1_fd_delay_val_o[4]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[4]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[4]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[8]" LOC = "AC22";
NET "fmc1_fd_delay_val_o[8]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[8]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[8]" DRIVE = 4;
NET "fmc1_fd_spi_miso_i" LOC = "AC20";
NET "fmc1_fd_spi_miso_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_spi_cs_pll_n_o" LOC = "AD19";
NET "fmc1_fd_spi_cs_pll_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_spi_cs_dac_n_o" LOC = "AG25";
NET "fmc1_fd_spi_cs_dac_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_stop_dis_o" LOC = "AF24";
NET "fmc1_fd_tdc_stop_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_ext_rst_n_o" LOC = "AF19";
NET "fmc1_fd_ext_rst_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_pll_status_i" LOC = "AF23";
NET "fmc1_fd_pll_status_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_dmtd_fb_out_i" LOC = "AF21";
NET "fmc1_fd_dmtd_fb_out_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_rd_n_o" LOC = "AD16";
NET "fmc1_fd_tdc_rd_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_emptyf_i" LOC = "AC14";
NET "fmc1_fd_tdc_emptyf_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_onewire_b" LOC = "AA17";
NET "fmc1_fd_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[27]" LOC = "AA15";
NET "fmc1_fd_tdc_d_b[27]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[25]" LOC = "AD15";
NET "fmc1_fd_tdc_d_b[25]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[21]" LOC = "AF15";
NET "fmc1_fd_tdc_d_b[21]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[23]" LOC = "AB16";
NET "fmc1_fd_tdc_d_b[23]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[19]" LOC = "AA14";
NET "fmc1_fd_tdc_d_b[19]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[17]" LOC = "Y13";
NET "fmc1_fd_tdc_d_b[17]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[11]" LOC = "AC12";
NET "fmc1_fd_tdc_d_b[11]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[15]" LOC = "AE12";
NET "fmc1_fd_tdc_d_b[15]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[9]" LOC = "AE10";
NET "fmc1_fd_tdc_d_b[9]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[13]" LOC = "AF11";
NET "fmc1_fd_tdc_d_b[13]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[1]" LOC = "AK15";
NET "fmc1_fd_tdc_d_b[1]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[4]" LOC = "AF13";
NET "fmc1_fd_tdc_d_b[4]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[6]" LOC = "AD11";
NET "fmc1_fd_tdc_d_b[6]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[0]" LOC = "AH8";
NET "fmc1_fd_tdc_d_b[0]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_dmtd_fb_in_i" LOC = "AK17";
NET "fmc1_fd_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";
# <ucfgen_end>
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "rst_n_i" IOSTANDARD = "LVCMOS33";
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS33";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
#---------------------------------------- NET "fp_gpio3_b" TNM_NET = fp_gpio3;
# SFP slot TIMESPEC TS_fp_gpio3 = PERIOD "fp_gpio3" 100 ns HIGH 50%;
#----------------------------------------
NET "sfp_los_i" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def0_b" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS33";
#NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
NET "pll20dac_din_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_sclk_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_din_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_sclk_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS33";
NET "fp_led_line_oen_o[0]" LOC = AD26;
NET "fp_led_line_oen_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_oen_o[1]" LOC = AD27;
NET "fp_led_line_oen_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_o[0]" LOC = AC27;
NET "fp_led_line_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_o[1]" LOC = AC28;
NET "fp_led_line_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[0]" LOC = AE30;
NET "fp_led_column_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[1]" LOC = AE27;
NET "fp_led_column_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[2]" LOC = AE28;
NET "fp_led_column_o[2]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[3]" LOC = AF28;
NET "fp_led_column_o[3]" IOSTANDARD="LVCMOS33";
NET "fp_gpio1_a2b_o" LOC=R29;
NET "fp_gpio1_a2b_o" IOSTANDARD="LVCMOS33";
NET "fp_gpio2_a2b_o" LOC=T30;
NET "fp_gpio2_a2b_o" IOSTANDARD="LVCMOS33";
NET "fp_gpio34_a2b_o" LOC=V28;
NET "fp_gpio34_a2b_o" IOSTANDARD="LVCMOS33";
NET "fp_gpio1_b" LOC=R30;
NET "fp_gpio1_b" IOSTANDARD="LVCMOS33";
NET "fp_gpio2_b" LOC=T28;
NET "fp_gpio2_b" IOSTANDARD="LVCMOS33";
NET "fp_gpio3_b" LOC=U29;
NET "fp_gpio3_b" IOSTANDARD="LVCMOS33";
NET "fp_gpio4_b" LOC=V27;
NET "fp_gpio4_b" IOSTANDARD="LVCMOS33";
#---------------------------------------- NET "fmc0_fd_clk_ref_n_i" TNM_NET = fmc0_fd_clk_ref_n_i;
# UART TIMESPEC TS_fmc0_fd_clk_ref_n_i = PERIOD "fmc0_fd_clk_ref_n_i" 8 ns HIGH 50%;
#----------------------------------------
NET "uart_txd_o" IOSTANDARD = "LVCMOS33";
NET "uart_rxd_i" IOSTANDARD = "LVCMOS33";
NET "fmc1_fd_clk_ref_n_i" TNM_NET = fmc1_fd_clk_ref_n_i;
TIMESPEC TS_fmc1_fd_clk_ref_n_i = PERIOD "fmc1_fd_clk_ref_n_i" 8 ns HIGH 50%;
#---------------------------------------- #----------------------------------------
# 1-wire thermoeter + unique ID # Cross-clock domain sync
#---------------------------------------- #----------------------------------------
NET "tempid_dq_b" IOSTANDARD = "LVCMOS33";
NET "fmc0_prsntm2c_n_i" LOC = N30;
NET "fmc0_scl_b" LOC = P28;
NET "fmc0_sda_b" LOC = P30;
NET "fmc1_prsntm2c_n_i" LOC = AE29;
NET "fmc1_scl_b" LOC = W29;
NET "fmc1_sda_b" LOC = V30;
NET "fmc1_prsntm2c_n_i" IOSTANDARD = "LVCMOS33"; # IMPORTANT: timing constraints are also coming from SVEC template UCF files
NET "fmc1_scl_b" IOSTANDARD = "LVCMOS33";
NET "fmc1_sda_b" IOSTANDARD = "LVCMOS33";
NET "fmc0_prsntm2c_n_i" IOSTANDARD = "LVCMOS33"; # Declaration of domains
NET "fmc0_scl_b" IOSTANDARD = "LVCMOS33"; NET "dcm0_clk_ref_0" TNM_NET = fd0_clk;
NET "fmc0_sda_b" IOSTANDARD = "LVCMOS33"; NET "dcm1_clk_ref_0" TNM_NET = fd1_clk;
# Exceptions for crossings via gc_sync_ffs
TIMEGRP "fd0_sync_ffs" = "sync_ffs" EXCEPT "fd0_clk";
TIMEGRP "fd1_sync_ffs" = "sync_ffs" EXCEPT "fd1_clk";
#Created by Constraints Editor (xc6slx150t-fgg900-3) - 2012/06/15 TIMESPEC TS_fd0_sync_ffs = FROM fd0_clk TO "fd0_sync_ffs" TIG;
NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i; TIMESPEC TS_fd1_sync_ffs = FROM fd1_clk TO "fd1_sync_ffs" TIG;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp_p_i;
TIMESPEC TS_clk_125m_gtp_p_i = PERIOD "clk_125m_gtp_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "fd0_clk_ref_n_i" TNM_NET = fd0_clk_ref_n_i;
TIMESPEC TS_fd0_clk_ref_n_i = PERIOD "fd0_clk_ref_n_i" 8 ns HIGH 50%;
NET "fd0_clk_ref_p_i" TNM_NET = fd0_clk_ref_p_i;
TIMESPEC TS_fd0_clk_ref_p_i = PERIOD "fd0_clk_ref_p_i" 8 ns HIGH 50%;
NET "fd1_clk_ref_p_i" TNM_NET = fd1_clk_ref_p_i;
TIMESPEC TS_fd1_clk_ref_p_i = PERIOD "fd1_clk_ref_p_i" 8 ns HIGH 50%;
NET "fd1_clk_ref_n_i" TNM_NET = fd1_clk_ref_n_i;
TIMESPEC TS_fd1_clk_ref_n_i = PERIOD "fd1_clk_ref_n_i" 8 ns HIGH 50%;
#NET "gen_with_phy.U_GTP/ch0_gtp_clkout_int<1>" TNM_NET = gen_with_phy.U_GTP/ch0_gtp_clkout_int<1>;
#TIMESPEC TS_gen_with_phy_U_GTP_ch0_gtp_clkout_int_1_ = PERIOD "gen_with_phy.U_GTP/ch0_gtp_clkout_int<1>" 8 ns HIGH 50%;
NET "gen_with_phy.U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = gen_with_phy.U_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_gen_with_phy_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "gen_with_phy.U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
# Exceptions for crossings via gc_sync_register
TIMESPEC ts_ignore_xclock1 = FROM "pllout_clk_sys" TO "clk_125m_pllref_p_i" 16 ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock2 = FROM "clk_125m_pllref_p_i" TO "pllout_clk_sys" 16 ns DATAPATHONLY;
TIMESPEC ts_x3 = FROM "pllout_clk_sys" TO "gen_with_phy_U_GTP_ch1_rx_divclk" 16 ns DATAPATHONLY;
TIMESPEC TS_x4 = FROM "gen_with_phy_U_GTP_ch1_rx_divclk" TO "pllout_clk_sys" 16 ns DATAPATHONLY;
TIMESPEC ts_x5 = FROM "clk_125m_pllref_p_i" TO "gen_with_phy_U_GTP_ch1_rx_divclk" 10 ns DATAPATHONLY;
TIMESPEC TS_x6 = FROM "gen_with_phy_U_GTP_ch1_rx_divclk" TO "clk_125m_pllref_p_i" 10 ns DATAPATHONLY;
# <ucfgen_start>
# This section has bee generated automatically by ucfgen.py. Do not hand-modify if not really necessary.
# ucfgen pin assignments for mezzanine fmc-delay-v4 slot 0
NET "fd0_clk_ref_p_i" LOC = "E16";
NET "fd0_clk_ref_p_i" IOSTANDARD = "LVDS_25";
NET "fd0_clk_ref_n_i" LOC = "D16";
NET "fd0_clk_ref_n_i" IOSTANDARD = "LVDS_25";
NET "fd0_tdc_start_p_i" LOC = "H15";
NET "fd0_tdc_start_p_i" IOSTANDARD = "LVDS_25";
NET "fd0_tdc_start_n_i" LOC = "G15";
NET "fd0_tdc_start_n_i" IOSTANDARD = "LVDS_25";
NET "fd0_delay_len_o[3]" LOC = "G10";
NET "fd0_delay_len_o[3]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_len_o[3]" SLEW = SLOW;
NET "fd0_delay_len_o[3]" DRIVE = 4;
NET "fd0_delay_len_o[2]" LOC = "F10";
NET "fd0_delay_len_o[2]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_len_o[2]" SLEW = SLOW;
NET "fd0_delay_len_o[2]" DRIVE = 4;
NET "fd0_delay_len_o[1]" LOC = "E9";
NET "fd0_delay_len_o[1]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_len_o[1]" SLEW = SLOW;
NET "fd0_delay_len_o[1]" DRIVE = 4;
NET "fd0_delay_len_o[0]" LOC = "F9";
NET "fd0_delay_len_o[0]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_len_o[0]" SLEW = SLOW;
NET "fd0_delay_len_o[0]" DRIVE = 4;
NET "fd0_delay_pulse_o[3]" LOC = "F12";
NET "fd0_delay_pulse_o[3]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_pulse_o[1]" LOC = "E11";
NET "fd0_delay_pulse_o[1]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_pulse_o[2]" LOC = "G12";
NET "fd0_delay_pulse_o[2]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_pulse_o[0]" LOC = "F11";
NET "fd0_delay_pulse_o[0]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_val_o[3]" LOC = "J12";
NET "fd0_delay_val_o[3]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_val_o[3]" SLEW = SLOW;
NET "fd0_delay_val_o[3]" DRIVE = 4;
NET "fd0_delay_val_o[1]" LOC = "H11";
NET "fd0_delay_val_o[1]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_val_o[1]" SLEW = SLOW;
NET "fd0_delay_val_o[1]" DRIVE = 4;
NET "fd0_delay_val_o[7]" LOC = "L11";
NET "fd0_delay_val_o[7]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_val_o[7]" SLEW = SLOW;
NET "fd0_delay_val_o[7]" DRIVE = 4;
NET "fd0_delay_val_o[5]" LOC = "J13";
NET "fd0_delay_val_o[5]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_val_o[5]" SLEW = SLOW;
NET "fd0_delay_val_o[5]" DRIVE = 4;
NET "fd0_delay_val_o[9]" LOC = "L12";
NET "fd0_delay_val_o[9]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_val_o[9]" SLEW = SLOW;
NET "fd0_delay_val_o[9]" DRIVE = 4;
NET "fd0_spi_mosi_o" LOC = "M13";
NET "fd0_spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "fd0_spi_sclk_o" LOC = "L14";
NET "fd0_spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_oe_n_o" LOC = "M15";
NET "fd0_tdc_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_start_dis_o" LOC = "F13";
NET "fd0_tdc_start_dis_o" IOSTANDARD = "LVCMOS25";
NET "fd0_spi_cs_gpio_n_o" LOC = "F15";
NET "fd0_spi_cs_gpio_n_o" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_cal_pulse_o" LOC = "G14";
NET "fd0_tdc_cal_pulse_o" IOSTANDARD = "LVCMOS25";
NET "fd0_dmtd_clk_o" LOC = "J14";
NET "fd0_dmtd_clk_o" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_wr_n_o" LOC = "B15";
NET "fd0_tdc_wr_n_o" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_alutrigger_o" LOC = "F19";
NET "fd0_tdc_alutrigger_o" IOSTANDARD = "LVCMOS25";
NET "fd0_led_trig_o" LOC = "H16";
NET "fd0_led_trig_o" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[26]" LOC = "F17";
NET "fd0_tdc_d_b[26]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[24]" LOC = "G18";
NET "fd0_tdc_d_b[24]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[20]" LOC = "F21";
NET "fd0_tdc_d_b[20]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[22]" LOC = "G20";
NET "fd0_tdc_d_b[22]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[18]" LOC = "L21";
NET "fd0_tdc_d_b[18]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[16]" LOC = "M20";
NET "fd0_tdc_d_b[16]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[10]" LOC = "F23";
NET "fd0_tdc_d_b[10]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[14]" LOC = "G22";
NET "fd0_tdc_d_b[14]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[8]" LOC = "B25";
NET "fd0_tdc_d_b[8]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[12]" LOC = "M19";
NET "fd0_tdc_d_b[12]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[3]" LOC = "D24";
NET "fd0_tdc_d_b[3]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[5]" LOC = "E25";
NET "fd0_tdc_d_b[5]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[7]" LOC = "J22";
NET "fd0_tdc_d_b[7]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[2]" LOC = "H21";
NET "fd0_tdc_d_b[2]" IOSTANDARD = "LVCMOS25";
NET "fd0_trig_a_i" LOC = "C16";
NET "fd0_trig_a_i" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_val_o[2]" LOC = "H12";
NET "fd0_delay_val_o[2]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_val_o[2]" SLEW = SLOW;
NET "fd0_delay_val_o[2]" DRIVE = 4;
NET "fd0_delay_val_o[0]" LOC = "G11";
NET "fd0_delay_val_o[0]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_val_o[0]" SLEW = SLOW;
NET "fd0_delay_val_o[0]" DRIVE = 4;
NET "fd0_delay_val_o[6]" LOC = "K11";
NET "fd0_delay_val_o[6]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_val_o[6]" SLEW = SLOW;
NET "fd0_delay_val_o[6]" DRIVE = 4;
NET "fd0_delay_val_o[4]" LOC = "H13";
NET "fd0_delay_val_o[4]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_val_o[4]" SLEW = SLOW;
NET "fd0_delay_val_o[4]" DRIVE = 4;
NET "fd0_delay_val_o[8]" LOC = "K12";
NET "fd0_delay_val_o[8]" IOSTANDARD = "LVCMOS25";
NET "fd0_delay_val_o[8]" SLEW = SLOW;
NET "fd0_delay_val_o[8]" DRIVE = 4;
NET "fd0_spi_miso_i" LOC = "L13";
NET "fd0_spi_miso_i" IOSTANDARD = "LVCMOS25";
NET "fd0_spi_cs_pll_n_o" LOC = "K14";
NET "fd0_spi_cs_pll_n_o" IOSTANDARD = "LVCMOS25";
NET "fd0_spi_cs_dac_n_o" LOC = "K15";
NET "fd0_spi_cs_dac_n_o" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_stop_dis_o" LOC = "E13";
NET "fd0_tdc_stop_dis_o" IOSTANDARD = "LVCMOS25";
NET "fd0_ext_rst_n_o" LOC = "E15";
NET "fd0_ext_rst_n_o" IOSTANDARD = "LVCMOS25";
NET "fd0_pll_status_i" LOC = "F14";
NET "fd0_pll_status_i" IOSTANDARD = "LVCMOS25";
NET "fd0_dmtd_fb_out_i" LOC = "H14";
NET "fd0_dmtd_fb_out_i" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_rd_n_o" LOC = "A15";
NET "fd0_tdc_rd_n_o" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_emptyf_i" LOC = "E19";
NET "fd0_tdc_emptyf_i" IOSTANDARD = "LVCMOS25";
NET "fd0_onewire_b" LOC = "G16";
NET "fd0_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[27]" LOC = "E17";
NET "fd0_tdc_d_b[27]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[25]" LOC = "F18";
NET "fd0_tdc_d_b[25]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[21]" LOC = "E21";
NET "fd0_tdc_d_b[21]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[23]" LOC = "F20";
NET "fd0_tdc_d_b[23]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[19]" LOC = "K21";
NET "fd0_tdc_d_b[19]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[17]" LOC = "L20";
NET "fd0_tdc_d_b[17]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[11]" LOC = "E23";
NET "fd0_tdc_d_b[11]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[15]" LOC = "F22";
NET "fd0_tdc_d_b[15]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[9]" LOC = "A25";
NET "fd0_tdc_d_b[9]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[13]" LOC = "L19";
NET "fd0_tdc_d_b[13]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[1]" LOC = "C24";
NET "fd0_tdc_d_b[1]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[4]" LOC = "D25";
NET "fd0_tdc_d_b[4]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[6]" LOC = "H22";
NET "fd0_tdc_d_b[6]" IOSTANDARD = "LVCMOS25";
NET "fd0_tdc_d_b[0]" LOC = "G21";
NET "fd0_tdc_d_b[0]" IOSTANDARD = "LVCMOS25";
NET "fd0_dmtd_fb_in_i" LOC = "A16";
NET "fd0_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";
# ucfgen pin assignments for mezzanine fmc-delay-v4 slot 1
NET "fd1_clk_ref_p_i" LOC = "AH16";
NET "fd1_clk_ref_p_i" IOSTANDARD = "LVDS_25";
NET "fd1_clk_ref_n_i" LOC = "AK16";
NET "fd1_clk_ref_n_i" IOSTANDARD = "LVDS_25";
NET "fd1_tdc_start_p_i" LOC = "AF16";
NET "fd1_tdc_start_p_i" IOSTANDARD = "LVDS_25";
NET "fd1_tdc_start_n_i" LOC = "AG16";
NET "fd1_tdc_start_n_i" IOSTANDARD = "LVDS_25";
NET "fd1_delay_len_o[3]" LOC = "AB21";
NET "fd1_delay_len_o[3]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_len_o[3]" SLEW = SLOW;
NET "fd1_delay_len_o[3]" DRIVE = 4;
NET "fd1_delay_len_o[2]" LOC = "AC21";
NET "fd1_delay_len_o[2]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_len_o[2]" SLEW = SLOW;
NET "fd1_delay_len_o[2]" DRIVE = 4;
NET "fd1_delay_len_o[1]" LOC = "AD24";
NET "fd1_delay_len_o[1]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_len_o[1]" SLEW = SLOW;
NET "fd1_delay_len_o[1]" DRIVE = 4;
NET "fd1_delay_len_o[0]" LOC = "AC24";
NET "fd1_delay_len_o[0]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_len_o[0]" SLEW = SLOW;
NET "fd1_delay_len_o[0]" DRIVE = 4;
NET "fd1_delay_pulse_o[3]" LOC = "AE22";
NET "fd1_delay_pulse_o[3]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_pulse_o[1]" LOC = "AD17";
NET "fd1_delay_pulse_o[1]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_pulse_o[2]" LOC = "AD22";
NET "fd1_delay_pulse_o[2]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_pulse_o[0]" LOC = "AB17";
NET "fd1_delay_pulse_o[0]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[3]" LOC = "AA19";
NET "fd1_delay_val_o[3]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[3]" SLEW = SLOW;
NET "fd1_delay_val_o[3]" DRIVE = 4;
NET "fd1_delay_val_o[1]" LOC = "W19";
NET "fd1_delay_val_o[1]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[1]" SLEW = SLOW;
NET "fd1_delay_val_o[1]" DRIVE = 4;
NET "fd1_delay_val_o[7]" LOC = "Y21";
NET "fd1_delay_val_o[7]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[7]" SLEW = SLOW;
NET "fd1_delay_val_o[7]" DRIVE = 4;
NET "fd1_delay_val_o[5]" LOC = "W20";
NET "fd1_delay_val_o[5]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[5]" SLEW = SLOW;
NET "fd1_delay_val_o[5]" DRIVE = 4;
NET "fd1_delay_val_o[9]" LOC = "AA22";
NET "fd1_delay_val_o[9]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[9]" SLEW = SLOW;
NET "fd1_delay_val_o[9]" DRIVE = 4;
NET "fd1_spi_mosi_o" LOC = "AB20";
NET "fd1_spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "fd1_spi_sclk_o" LOC = "AC19";
NET "fd1_spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_oe_n_o" LOC = "AF25";
NET "fd1_tdc_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_start_dis_o" LOC = "AE24";
NET "fd1_tdc_start_dis_o" IOSTANDARD = "LVCMOS25";
NET "fd1_spi_cs_gpio_n_o" LOC = "AE19";
NET "fd1_spi_cs_gpio_n_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_cal_pulse_o" LOC = "AE23";
NET "fd1_tdc_cal_pulse_o" IOSTANDARD = "LVCMOS25";
NET "fd1_dmtd_clk_o" LOC = "AE21";
NET "fd1_dmtd_clk_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_wr_n_o" LOC = "AC16";
NET "fd1_tdc_wr_n_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_alutrigger_o" LOC = "AB14";
NET "fd1_tdc_alutrigger_o" IOSTANDARD = "LVCMOS25";
NET "fd1_led_trig_o" LOC = "Y17";
NET "fd1_led_trig_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[26]" LOC = "Y15";
NET "fd1_tdc_d_b[26]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[24]" LOC = "AC15";
NET "fd1_tdc_d_b[24]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[20]" LOC = "AE15";
NET "fd1_tdc_d_b[20]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[22]" LOC = "Y16";
NET "fd1_tdc_d_b[22]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[18]" LOC = "Y14";
NET "fd1_tdc_d_b[18]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[16]" LOC = "W14";
NET "fd1_tdc_d_b[16]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[10]" LOC = "AB12";
NET "fd1_tdc_d_b[10]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[14]" LOC = "AD12";
NET "fd1_tdc_d_b[14]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[8]" LOC = "AD10";
NET "fd1_tdc_d_b[8]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[12]" LOC = "AE11";
NET "fd1_tdc_d_b[12]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[3]" LOC = "AJ15";
NET "fd1_tdc_d_b[3]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[5]" LOC = "AE13";
NET "fd1_tdc_d_b[5]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[7]" LOC = "AC11";
NET "fd1_tdc_d_b[7]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[2]" LOC = "AG8";
NET "fd1_tdc_d_b[2]" IOSTANDARD = "LVCMOS25";
NET "fd1_trig_a_i" LOC = "AJ17";
NET "fd1_trig_a_i" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[2]" LOC = "AB19";
NET "fd1_delay_val_o[2]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[2]" SLEW = SLOW;
NET "fd1_delay_val_o[2]" DRIVE = 4;
NET "fd1_delay_val_o[0]" LOC = "Y19";
NET "fd1_delay_val_o[0]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[0]" SLEW = SLOW;
NET "fd1_delay_val_o[0]" DRIVE = 4;
NET "fd1_delay_val_o[6]" LOC = "AA21";
NET "fd1_delay_val_o[6]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[6]" SLEW = SLOW;
NET "fd1_delay_val_o[6]" DRIVE = 4;
NET "fd1_delay_val_o[4]" LOC = "Y20";
NET "fd1_delay_val_o[4]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[4]" SLEW = SLOW;
NET "fd1_delay_val_o[4]" DRIVE = 4;
NET "fd1_delay_val_o[8]" LOC = "AC22";
NET "fd1_delay_val_o[8]" IOSTANDARD = "LVCMOS25";
NET "fd1_delay_val_o[8]" SLEW = SLOW;
NET "fd1_delay_val_o[8]" DRIVE = 4;
NET "fd1_spi_miso_i" LOC = "AC20";
NET "fd1_spi_miso_i" IOSTANDARD = "LVCMOS25";
NET "fd1_spi_cs_pll_n_o" LOC = "AD19";
NET "fd1_spi_cs_pll_n_o" IOSTANDARD = "LVCMOS25";
NET "fd1_spi_cs_dac_n_o" LOC = "AG25";
NET "fd1_spi_cs_dac_n_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_stop_dis_o" LOC = "AF24";
NET "fd1_tdc_stop_dis_o" IOSTANDARD = "LVCMOS25";
NET "fd1_ext_rst_n_o" LOC = "AF19";
NET "fd1_ext_rst_n_o" IOSTANDARD = "LVCMOS25";
NET "fd1_pll_status_i" LOC = "AF23";
NET "fd1_pll_status_i" IOSTANDARD = "LVCMOS25";
NET "fd1_dmtd_fb_out_i" LOC = "AF21";
NET "fd1_dmtd_fb_out_i" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_rd_n_o" LOC = "AD16";
NET "fd1_tdc_rd_n_o" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_emptyf_i" LOC = "AC14";
NET "fd1_tdc_emptyf_i" IOSTANDARD = "LVCMOS25";
NET "fd1_onewire_b" LOC = "AA17";
NET "fd1_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[27]" LOC = "AA15";
NET "fd1_tdc_d_b[27]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[25]" LOC = "AD15";
NET "fd1_tdc_d_b[25]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[21]" LOC = "AF15";
NET "fd1_tdc_d_b[21]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[23]" LOC = "AB16";
NET "fd1_tdc_d_b[23]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[19]" LOC = "AA14";
NET "fd1_tdc_d_b[19]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[17]" LOC = "Y13";
NET "fd1_tdc_d_b[17]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[11]" LOC = "AC12";
NET "fd1_tdc_d_b[11]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[15]" LOC = "AE12";
NET "fd1_tdc_d_b[15]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[9]" LOC = "AE10";
NET "fd1_tdc_d_b[9]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[13]" LOC = "AF11";
NET "fd1_tdc_d_b[13]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[1]" LOC = "AK15";
NET "fd1_tdc_d_b[1]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[4]" LOC = "AF13";
NET "fd1_tdc_d_b[4]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[6]" LOC = "AD11";
NET "fd1_tdc_d_b[6]" IOSTANDARD = "LVCMOS25";
NET "fd1_tdc_d_b[0]" LOC = "AH8";
NET "fd1_tdc_d_b[0]" IOSTANDARD = "LVCMOS25";
NET "fd1_dmtd_fb_in_i" LOC = "AK17";
NET "fd1_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";
# <ucfgen_end>
hdl/top/svec/svec_top.vhd
View file @ be2a5d7b
------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Title : Fine Delay FMC SVEC (Simple VME FMC Carrier) top level -- CERN BE-CO-HT
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha) -- Fine Delay Mezzanine (fmc-fine-delay)
------------------------------------------------------------------------------- -- https://ohwr.org/projects/fmc-delay-1ns-8cha
-- File : svec_top.vhd --------------------------------------------------------------------------------
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2019-03-25
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top level for the SVEC 1.0 card with two Fine Delay FMCs.
-- Supports:
-- - A24/A32/D32 VME addressing
-- - SDB enumeration (SDB descriptor at 0x0)
-- - White Rabbit and Etherbone
-- - Interrupts (via vme64x-core interrupter, to be verified)
-------------------------------------------------------------------------------
-- --
-- Copyright (c) 2011 CERN / BE-CO-HT -- unit name: spec_top
-- --
-- This source file is free software; you can redistribute it -- description: Top entity for Fine Delay reference design.
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
-- --
-- This source is distributed in the hope that it will be -- Top level design of the SVEC-based FMC Fine Delay (2 mezzanines).
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
-- --
-- You should have received a copy of the GNU Lesser General -- This is the standard pulse-in/pulse-out WRTD node, with the FMC TDC
-- Public License along with this source; if not, download it -- injecting pulses into the WR network in the form of WRTD messages and
-- from http://www.gnu.org/licenses/lgpl-2.1.html -- the FMC Fine Delay converting those messages back to pulses at the
-- destination.
-- --
------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Copyright CERN 2011-2019
--------------------------------------------------------------------------------
library IEEE; -- Copyright and related rights are licensed under the Solderpad Hardware
use IEEE.STD_LOGIC_1164.all; -- License, Version 2.0 (the "License"); you may not use this file except
use IEEE.NUMERIC_STD.all; -- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all; use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_fabric_pkg.all;
use work.fine_delay_pkg.all; use work.fine_delay_pkg.all;
--use work.etherbone_pkg.all;
use work.wr_xilinx_pkg.all;
use work.vme64x_pkg.all;
use work.synthesis_descriptor.all;
library UNISIM; library unisim;
use UNISIM.vcomponents.all; use unisim.vcomponents.all;
entity svec_top is entity svec_top is
generic generic (
( g_WRPC_INITF : string := "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram";
g_with_wr_phy : integer := 1; -- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
g_simulation : integer := 0; -- changed to non-zero in the instantiation of the top level DUT in the
g_SIM_BYPASS_VME : integer := 0 -- testbench. Its purpose is to reduce some internal counters/timeouts
); -- to speed up simulations.
port g_SIMULATION : integer := 0);
( port (
---------------------------------------------------------------------------
------------------------------------------------------------------------- -- Clocks/resets
-- Standard SVEC ports (Gennum bridge, LEDS, Etc. Do not modify ---------------------------------------------------------------------------
-------------------------------------------------------------------------
-- Reset from system fpga
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock rst_n_i : in std_logic;
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference -- Local oscillators
clk_125m_pllref_n_i : in std_logic; clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_gtp_p_i : in std_logic; -- 125 MHz PLL reference clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_gtp_n_i : in std_logic; clk_125m_pllref_n_i : in std_logic;
rst_n_i : in std_logic; clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic;
-- SVEC Front panel LEDs
---------------------------------------------------------------------------
fp_led_line_oen_o : out std_logic_vector(1 downto 0); -- VME interface
fp_led_line_o : out std_logic_vector(1 downto 0); ---------------------------------------------------------------------------
fp_led_column_o : out std_logic_vector(3 downto 0);
vme_write_n_i : in std_logic;
fp_gpio1_a2b_o : out std_logic; vme_sysreset_n_i : in std_logic;
fp_gpio2_a2b_o : out std_logic; vme_retry_oe_o : out std_logic;
fp_gpio34_a2b_o : out std_logic; vme_retry_n_o : out std_logic;
vme_lword_n_b : inout std_logic;
fp_gpio1_b : out std_logic; vme_iackout_n_o : out std_logic;
fp_gpio2_b : out std_logic; vme_iackin_n_i : in std_logic;
fp_gpio3_b : out std_logic; vme_iack_n_i : in std_logic;
fp_gpio4_b : out std_logic; vme_gap_i : in std_logic;
vme_dtack_oe_o : out std_logic;
------------------------------------------------------------------------- vme_dtack_n_o : out std_logic;
-- VME Interface pins vme_ds_n_i : in std_logic_vector(1 downto 0);
------------------------------------------------------------------------- vme_data_oe_n_o : out std_logic;
vme_data_dir_o : out std_logic;
VME_AS_n_i : in std_logic; vme_berr_o : out std_logic;
VME_RST_n_i : in std_logic; vme_as_n_i : in std_logic;
VME_WRITE_n_i : in std_logic; vme_addr_oe_n_o : out std_logic;
VME_AM_i : in std_logic_vector(5 downto 0); vme_addr_dir_o : out std_logic;
VME_DS_n_i : in std_logic_vector(1 downto 0); vme_irq_o : out std_logic_vector(7 downto 1);
VME_GA_i : in std_logic_vector(5 downto 0); vme_ga_i : in std_logic_vector(4 downto 0);
VME_BERR_o : inout std_logic; vme_data_b : inout std_logic_vector(31 downto 0);
VME_DTACK_n_o : inout std_logic; vme_am_i : in std_logic_vector(5 downto 0);
VME_RETRY_n_o : out std_logic; vme_addr_b : inout std_logic_vector(31 downto 1);
VME_RETRY_OE_o : out std_logic;
---------------------------------------------------------------------------
VME_LWORD_n_b : inout std_logic; -- SPI interfaces to DACs
VME_ADDR_b : inout std_logic_vector(31 downto 1); ---------------------------------------------------------------------------
VME_DATA_b : inout std_logic_vector(31 downto 0);
VME_BBSY_n_i : in std_logic; pll20dac_din_o : out std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0); pll20dac_sclk_o : out std_logic;
VME_IACK_n_i : in std_logic; pll20dac_sync_n_o : out std_logic;
VME_IACKIN_n_i : in std_logic; pll25dac_din_o : out std_logic;
VME_IACKOUT_n_o : out std_logic; pll25dac_sclk_o : out std_logic;
VME_DTACK_OE_o : inout std_logic; pll25dac_sync_n_o : out std_logic;
VME_DATA_DIR_o : inout std_logic;
VME_DATA_OE_N_o : inout std_logic; ---------------------------------------------------------------------------
VME_ADDR_DIR_o : inout std_logic; -- SFP I/O for transceiver
VME_ADDR_OE_N_o : inout std_logic; ---------------------------------------------------------------------------
------------------------------------------------------------------------- sfp_txp_o : out std_logic;
-- SFP pins sfp_txn_o : out std_logic;
------------------------------------------------------------------------- sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_txp_o : out std_logic; sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_txn_o : out std_logic; sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rxp_i : in std_logic := '0'; sfp_rate_select_o : out std_logic;
sfp_rxn_i : in std_logic := '1'; sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_mod_def0_b : in std_logic; -- detect pin sfp_los_i : in std_logic;
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda ---------------------------------------------------------------------------
sfp_rate_select_b : inout std_logic := '0'; -- Carrier I2C EEPROM
sfp_tx_fault_i : in std_logic := '0'; ---------------------------------------------------------------------------
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0'; carrier_scl_b : inout std_logic;
carrier_sda_b : inout std_logic;
fmc0_prsntm2c_n_i : in std_logic;
fmc1_prsntm2c_n_i : in std_logic; ---------------------------------------------------------------------------
-- PCB version
fmc0_scl_b : inout std_logic; ---------------------------------------------------------------------------
fmc0_sda_b : inout std_logic; pcbrev_i : in std_logic_vector(4 downto 0);
fmc1_scl_b : inout std_logic; ---------------------------------------------------------------------------
fmc1_sda_b : inout std_logic; -- Onewire interface
---------------------------------------------------------------------------
pll20dac_din_o : out std_logic;
pll20dac_sclk_o : out std_logic; onewire_b : inout std_logic;
pll20dac_sync_n_o : out std_logic;
pll25dac_din_o : out std_logic; ---------------------------------------------------------------------------
pll25dac_sclk_o : out std_logic; -- UART
pll25dac_sync_n_o : out std_logic; ---------------------------------------------------------------------------
tempid_dq_b : inout std_logic; uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
-------------------------------------------------------------------------
-- Fine Delay Pins ---------------------------------------------------------------------------
------------------------------------------------------------------------- -- SPI (flash is connected to SFPGA and routed to AFPGA
-- once the boot process is complete)
fd0_tdc_start_p_i : in std_logic; ---------------------------------------------------------------------------
fd0_tdc_start_n_i : in std_logic;
spi_sclk_o : out std_logic;
fd0_clk_ref_p_i : in std_logic; spi_ncs_o : out std_logic;
fd0_clk_ref_n_i : in std_logic; spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
fd0_trig_a_i : in std_logic;
fd0_tdc_cal_pulse_o : out std_logic; ---------------------------------------------------------------------------
fd0_tdc_d_b : inout std_logic_vector(27 downto 0); -- Carrier front panel LEDs and IOs
fd0_tdc_emptyf_i : in std_logic; ---------------------------------------------------------------------------
fd0_tdc_alutrigger_o : out std_logic;
fd0_tdc_wr_n_o : out std_logic; fp_led_line_oen_o : out std_logic_vector(1 downto 0);
fd0_tdc_rd_n_o : out std_logic; fp_led_line_o : out std_logic_vector(1 downto 0);
fd0_tdc_oe_n_o : out std_logic; fp_led_column_o : out std_logic_vector(3 downto 0);
fd0_led_trig_o : out std_logic;
fd0_tdc_start_dis_o : out std_logic; fp_gpio1_b : out std_logic; -- PPS output
fd0_tdc_stop_dis_o : out std_logic; fp_gpio2_b : out std_logic; -- Ref clock div2 output
fd0_spi_cs_dac_n_o : out std_logic; fp_gpio3_b : in std_logic; -- ext 10MHz clock input
fd0_spi_cs_pll_n_o : out std_logic; fp_gpio4_b : in std_logic; -- ext PPS input
fd0_spi_cs_gpio_n_o : out std_logic; fp_term_en_o : out std_logic_vector(4 downto 1);
fd0_spi_sclk_o : out std_logic; fp_gpio1_a2b_o : out std_logic;
fd0_spi_mosi_o : out std_logic; fp_gpio2_a2b_o : out std_logic;
fd0_spi_miso_i : in std_logic; fp_gpio34_a2b_o : out std_logic;
fd0_delay_len_o : out std_logic_vector(3 downto 0);
fd0_delay_val_o : out std_logic_vector(9 downto 0); ------------------------------------------
fd0_delay_pulse_o : out std_logic_vector(3 downto 0); -- FMC slot 1
------------------------------------------
fd0_dmtd_clk_o : out std_logic;
fd0_dmtd_fb_in_i : in std_logic; fmc0_fd_tdc_start_p_i : in std_logic;
fd0_dmtd_fb_out_i : in std_logic; fmc0_fd_tdc_start_n_i : in std_logic;
fd0_pll_status_i : in std_logic; fmc0_fd_clk_ref_p_i : in std_logic;
fd0_ext_rst_n_o : out std_logic; fmc0_fd_clk_ref_n_i : in std_logic;
fd0_onewire_b : inout std_logic; fmc0_fd_trig_a_i : in std_logic;
fmc0_fd_tdc_cal_pulse_o : out std_logic;
fmc0_fd_tdc_d_b : inout std_logic_vector(27 downto 0);
fd1_tdc_start_p_i : in std_logic; fmc0_fd_tdc_emptyf_i : in std_logic;
fd1_tdc_start_n_i : in std_logic; fmc0_fd_tdc_alutrigger_o : out std_logic;
fmc0_fd_tdc_wr_n_o : out std_logic;
fd1_clk_ref_p_i : in std_logic; fmc0_fd_tdc_rd_n_o : out std_logic;
fd1_clk_ref_n_i : in std_logic; fmc0_fd_tdc_oe_n_o : out std_logic;
fmc0_fd_led_trig_o : out std_logic;
fd1_trig_a_i : in std_logic; fmc0_fd_tdc_start_dis_o : out std_logic;
fd1_tdc_cal_pulse_o : out std_logic; fmc0_fd_tdc_stop_dis_o : out std_logic;
fd1_tdc_d_b : inout std_logic_vector(27 downto 0); fmc0_fd_spi_cs_dac_n_o : out std_logic;
fd1_tdc_emptyf_i : in std_logic; fmc0_fd_spi_cs_pll_n_o : out std_logic;
fd1_tdc_alutrigger_o : out std_logic; fmc0_fd_spi_cs_gpio_n_o : out std_logic;
fd1_tdc_wr_n_o : out std_logic; fmc0_fd_spi_sclk_o : out std_logic;
fd1_tdc_rd_n_o : out std_logic; fmc0_fd_spi_mosi_o : out std_logic;
fd1_tdc_oe_n_o : out std_logic; fmc0_fd_spi_miso_i : in std_logic;
fd1_led_trig_o : out std_logic; fmc0_fd_delay_len_o : out std_logic_vector(3 downto 0);
fd1_tdc_start_dis_o : out std_logic; fmc0_fd_delay_val_o : out std_logic_vector(9 downto 0);
fd1_tdc_stop_dis_o : out std_logic; fmc0_fd_delay_pulse_o : out std_logic_vector(3 downto 0);
fd1_spi_cs_dac_n_o : out std_logic;
fd1_spi_cs_pll_n_o : out std_logic; fmc0_fd_dmtd_clk_o : out std_logic;
fd1_spi_cs_gpio_n_o : out std_logic; fmc0_fd_dmtd_fb_in_i : in std_logic;
fd1_spi_sclk_o : out std_logic; fmc0_fd_dmtd_fb_out_i : in std_logic;
fd1_spi_mosi_o : out std_logic;
fd1_spi_miso_i : in std_logic; fmc0_fd_pll_status_i : in std_logic;
fd1_delay_len_o : out std_logic_vector(3 downto 0); fmc0_fd_ext_rst_n_o : out std_logic;
fd1_delay_val_o : out std_logic_vector(9 downto 0);
fd1_delay_pulse_o : out std_logic_vector(3 downto 0); fmc0_fd_onewire_b : inout std_logic;
fd1_dmtd_clk_o : out std_logic; -- FMC slot management
fd1_dmtd_fb_in_i : in std_logic;
fd1_dmtd_fb_out_i : in std_logic; fmc0_prsnt_m2c_n_i : in std_logic;
fd1_pll_status_i : in std_logic; fmc0_scl_b : inout std_logic;
fd1_ext_rst_n_o : out std_logic; fmc0_sda_b : inout std_logic;
fd1_onewire_b : inout std_logic; ------------------------------------------
-- FMC slot 1
----------------------------------------- ------------------------------------------
-- UART
----------------------------------------- fmc1_fd_tdc_start_p_i : in std_logic;
fmc1_fd_tdc_start_n_i : in std_logic;
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic fmc1_fd_clk_ref_p_i : in std_logic;
-- Bypass VME core, useful only in simulation fmc1_fd_clk_ref_n_i : in std_logic;
-- synthesis translate_off
; fmc1_fd_trig_a_i : in std_logic;
sim_wb_i : in t_wishbone_slave_in := cc_dummy_slave_in; fmc1_fd_tdc_cal_pulse_o : out std_logic;
sim_wb_o : out t_wishbone_slave_out fmc1_fd_tdc_d_b : inout std_logic_vector(27 downto 0);
-- synthesis translate_on fmc1_fd_tdc_emptyf_i : in std_logic;
); fmc1_fd_tdc_alutrigger_o : out std_logic;
fmc1_fd_tdc_wr_n_o : out std_logic;
end svec_top; fmc1_fd_tdc_rd_n_o : out std_logic;
fmc1_fd_tdc_oe_n_o : out std_logic;
architecture rtl of svec_top is fmc1_fd_led_trig_o : out std_logic;
fmc1_fd_tdc_start_dis_o : out std_logic;
signal VME_BERR_n : std_logic; fmc1_fd_tdc_stop_dis_o : out std_logic;
signal VME_IRQ_n : std_logic_vector(6 downto 0); fmc1_fd_spi_cs_dac_n_o : out std_logic;
fmc1_fd_spi_cs_pll_n_o : out std_logic;
fmc1_fd_spi_cs_gpio_n_o : out std_logic;
component fd_ddr_pll fmc1_fd_spi_sclk_o : out std_logic;
fmc1_fd_spi_mosi_o : out std_logic;
fmc1_fd_spi_miso_i : in std_logic;
fmc1_fd_delay_len_o : out std_logic_vector(3 downto 0);
fmc1_fd_delay_val_o : out std_logic_vector(9 downto 0);
fmc1_fd_delay_pulse_o : out std_logic_vector(3 downto 0);
fmc1_fd_dmtd_clk_o : out std_logic;
fmc1_fd_dmtd_fb_in_i : in std_logic;
fmc1_fd_dmtd_fb_out_i : in std_logic;
fmc1_fd_pll_status_i : in std_logic;
fmc1_fd_ext_rst_n_o : out std_logic;
fmc1_fd_onewire_b : inout std_logic;
-- FMC slot management
fmc1_prsnt_m2c_n_i : in std_logic;
fmc1_scl_b : inout std_logic;
fmc1_sda_b : inout std_logic
);
end entity svec_top;
architecture arch of svec_top is
component fd_ddr_pll
port ( port (
RST : in std_logic; RST : in std_logic;
LOCKED : out std_logic; LOCKED : out std_logic;
...@@ -270,100 +283,86 @@ architecture rtl of svec_top is ...@@ -270,100 +283,86 @@ architecture rtl of svec_top is
CLK_OUT2 : out std_logic); CLK_OUT2 : out std_logic);
end component; end component;
component spec_serial_dac -----------------------------------------------------------------------------
generic ( -- Constants
g_num_data_bits : integer; -----------------------------------------------------------------------------
g_num_extra_bits : integer;
g_num_cs_select : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
value_i : in std_logic_vector(g_num_data_bits-1 downto 0);
cs_sel_i : in std_logic_vector(g_num_cs_select-1 downto 0);
load_i : in std_logic;
sclk_divsel_i : in std_logic_vector(2 downto 0);
dac_cs_n_o : out std_logic_vector(g_num_cs_select-1 downto 0);
dac_sclk_o : out std_logic;
dac_sdata_o : out std_logic;
xdone_o : out std_logic);
end component;
component bicolor_led_ctrl -- Number of masters attached to the primary wishbone crossbar
generic ( constant c_NUM_WB_MASTERS : integer := 1;
g_NB_COLUMN : natural;
g_NB_LINE : natural;
g_CLK_FREQ : natural;
g_REFRESH_RATE : natural);
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
led_intensity_i : in std_logic_vector(6 downto 0);
led_state_i : in std_logic_vector((g_NB_LINE * g_NB_COLUMN * 2) - 1 downto 0);
column_o : out std_logic_vector(g_NB_COLUMN - 1 downto 0);
line_o : out std_logic_vector(g_NB_LINE - 1 downto 0);
line_oen_o : out std_logic_vector(g_NB_LINE - 1 downto 0));
end component;
signal VME_DATA_b_out : std_logic_vector(31 downto 0); -- Number of slaves attached to the primary wishbone crossbar
signal VME_ADDR_b_out : std_logic_vector(31 downto 1); constant c_NUM_WB_SLAVES : integer := 3;
signal VME_LWORD_n_b_out, VME_DATA_DIR_int, VME_ADDR_DIR_int : std_logic;
-- Primary Wishbone master(s) offsets
signal dac_hpll_load_p1 : std_logic; constant c_WB_MASTER_VME : integer := 0;
signal dac_dpll_load_p1 : std_logic;
signal dac_hpll_data : std_logic_vector(15 downto 0);
signal dac_dpll_data : std_logic_vector(15 downto 0);
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_k : std_logic_vector(0 downto 0);
signal phy_tx_disparity : std_logic;
signal phy_tx_enc_err : std_logic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_rx_rbclk : std_logic;
signal phy_rx_k : std_logic_vector(0 downto 0);
signal phy_rx_enc_err : std_logic;
signal phy_rx_bitslide : std_logic_vector(3 downto 0);
signal phy_rst : std_logic;
signal phy_loopen : std_logic;
constant c_NUM_WB_MASTERS : integer := 4;
constant c_NUM_WB_SLAVES : integer := 2;
constant c_MASTER_VME : integer := 0;
constant c_MASTER_ETHERBONE : integer := 1;
constant c_SLAVE_FD1 : integer := 1;
constant c_SLAVE_FD0 : integer := 0;
constant c_SLAVE_WRCORE : integer := 3;
constant c_SLAVE_VIC : integer := 2;
constant c_DESC_SYNTHESIS : integer := 4;
constant c_DESC_REPO_URL : integer := 5;
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS + 1 downto 0) :=
(
c_SLAVE_FD0 => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00010000"),
c_SLAVE_FD1 => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00020000"),
c_SLAVE_VIC => f_sdb_embed_device(c_xwb_vic_sdb, x"00030000"),
c_SLAVE_WRCORE => f_sdb_embed_bridge(c_WRCORE_BRIDGE_SDB, x"00040000"),
c_DESC_SYNTHESIS => f_sdb_embed_synthesis(c_sdb_synthesis_info),
c_DESC_REPO_URL => f_sdb_embed_repo_url(c_sdb_repo_url)
);
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000"; -- Primary Wishbone slave(s) offsets
constant c_WB_SLAVE_METADATA : integer := 0;
constant c_WB_SLAVE_FD0 : integer := 1;
constant c_WB_SLAVE_FD1 : integer := 2;
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 1) := -- Convention metadata base address
(0 => x"00010000", constant c_METADATA_ADDR : t_wishbone_address := x"0000_2000";
1 => x"00020000");
-- Primary wishbone crossbar layout
constant c_WB_LAYOUT_ADDR :
t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_METADATA => c_METADATA_ADDR,
c_WB_SLAVE_FD0 => x"0001_0000",
c_WB_SLAVE_FD1 => x"0002_0000");
constant c_WB_LAYOUT_MASK :
t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_METADATA => x"0003_ffc0", -- 0x40 bytes
c_WB_SLAVE_FD0 => x"0003_0000", -- 0x200 bytes
c_WB_SLAVE_FD1 => x"0003_0000"); -- 0x20000 bytes
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- Wishbone buse(s) from masters attached to crossbar
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0); signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0); signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
-- Wishbone buse(s) to slaves attached to crossbar
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0); signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0); signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
signal dcm0_clk_ref_0, dcm0_clk_ref_180 : std_logic; -- clock and reset
signal areset_n : std_logic;
signal clk_dmtd_125m : std_logic;
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal clk_ref_125m : std_logic;
signal clk_ref_div2 : std_logic;
signal clk_ext_ref : std_logic;
-- VME
signal vme_access_led : std_logic;
-- LEDs and GPIO
signal pps : std_logic;
signal pps_led : std_logic;
signal svec_led : std_logic_vector(15 downto 0);
signal wr_led_link : std_logic;
signal wr_led_act : std_logic;
-- Interrupts
signal irq_vector : std_logic_vector(1 downto 0);
-- WRPC TM interface and aux clocks
signal tm_link_up : std_logic;
signal tm_tai : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_time_valid : std_logic;
signal tm_clk_aux_lock_en : std_logic_vector(1 downto 0);
signal tm_clk_aux_locked : std_logic_vector(1 downto 0);
signal tm_dac_value : std_logic_vector(23 downto 0);
signal tm_dac_wr : std_logic_vector(1 downto 0);
signal dcm0_clk_ref_0, dcm0_clk_ref_180 : std_logic;
signal fd0_tdc_start : std_logic; signal fd0_tdc_start : std_logic;
signal fd0_tdc_start_predelay : std_logic; signal fd0_tdc_start_predelay : std_logic;
signal fd0_tdc_start_iodelay_inc : std_logic; signal fd0_tdc_start_iodelay_inc : std_logic;
...@@ -385,528 +384,174 @@ architecture rtl of svec_top is ...@@ -385,528 +384,174 @@ architecture rtl of svec_top is
signal tdc1_data_out, tdc1_data_in : std_logic_vector(27 downto 0); signal tdc1_data_out, tdc1_data_in : std_logic_vector(27 downto 0);
signal tdc1_data_oe : std_logic; signal tdc1_data_oe : std_logic;
signal tm_link_up : std_logic;
signal tm_utc : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_time_valid : std_logic;
signal tm_clk_aux_lock_en : std_logic_vector(1 downto 0);
signal tm_clk_aux_locked : std_logic_vector(1 downto 0);
signal tm_dac_value : std_logic_vector(23 downto 0);
signal tm_dac_wr : std_logic_vector(1 downto 0);
signal ddr0_pll_reset : std_logic; signal ddr0_pll_reset : std_logic;
signal ddr0_pll_locked, fd0_pll_status : std_logic; signal ddr0_pll_locked, fd0_pll_status : std_logic;
signal ddr1_pll_reset : std_logic; signal ddr1_pll_reset : std_logic;
signal ddr1_pll_locked, fd1_pll_status : std_logic; signal ddr1_pll_locked, fd1_pll_status : std_logic;
signal wrc_scl_out, wrc_scl_in, wrc_sda_out, wrc_sda_in : std_logic;
signal fd0_scl_out, fd0_scl_in, fd0_sda_out, fd0_sda_in : std_logic; signal fd0_scl_out, fd0_scl_in, fd0_sda_out, fd0_sda_in : std_logic;
signal fd1_scl_out, fd1_scl_in, fd1_sda_out, fd1_sda_in : std_logic; signal fd1_scl_out, fd1_scl_in, fd1_sda_out, fd1_sda_in : std_logic;
signal sfp_scl_out, sfp_scl_in, sfp_sda_out, sfp_sda_in : std_logic;
signal wrc_owr_en, wrc_owr_in : std_logic_vector(1 downto 0);
signal fd0_owr_en, fd0_owr_in : std_logic; signal fd0_owr_en, fd0_owr_in : std_logic;
signal fd1_owr_en, fd1_owr_in : std_logic; signal fd1_owr_en, fd1_owr_in : std_logic;
signal fd0_irq, fd1_irq : std_logic; signal fd0_irq, fd1_irq : std_logic;
signal pllout_clk_sys : std_logic;
signal pllout_clk_dmtd : std_logic;
signal pllout_clk_fb_pllref : std_logic;
signal pllout_clk_fb_dmtd : std_logic;
signal clk_20m_vcxo_buf : std_logic;
signal clk_125m_pllref : std_logic;
signal clk_125m_gtp : std_logic;
signal clk_sys : std_logic;
signal clk_dmtd : std_logic;
signal local_reset_n : std_logic;
signal vme_master_out : t_wishbone_master_out;
signal vme_master_in : t_wishbone_master_in;
signal pins : std_logic_vector(31 downto 0);
signal pps : std_logic;
signal vic_master_irq : std_logic;
function f_int2bool (x : integer) return boolean is
begin
if(x = 0) then
return false;
else
return true;
end if;
end f_int2bool;
function f_resize_slv (x : std_logic_vector; len : integer) return std_logic_vector is
variable tmp : std_logic_vector(len-1 downto 0);
begin
if(len > x'length) then
tmp(x'length-1 downto 0) := x;
tmp(len-1 downto x'length) := (others => '0');
elsif(len < x'length) then
tmp := x(len-1 downto 0);
else
tmp := x;
end if;
return tmp;
end f_resize_slv;
signal etherbone_rst_n : std_logic;
signal etherbone_src_out : t_wrf_source_out;
signal etherbone_src_in : t_wrf_source_in;
signal etherbone_snk_out : t_wrf_sink_out;
signal etherbone_snk_in : t_wrf_sink_in;
signal etherbone_cfg_in : t_wishbone_slave_in;
signal etherbone_cfg_out : t_wishbone_slave_out;
attribute buffer_type : string; --" {bufgdll | ibufg | bufgp | ibuf | bufr | none}";
attribute buffer_type of clk_125m_pllref : signal is "BUFG";
signal powerup_reset_cnt : unsigned(7 downto 0) := "00000000";
signal powerup_rst_n : std_logic := '0';
signal sys_locked : std_logic;
signal led_state : std_logic_vector(15 downto 0);
signal pps_led, pps_ext : std_logic;
signal led_link : std_logic;
signal led_act : std_logic;
signal vme_access : std_logic;
signal fd0_dbg : std_logic_vector(7 downto 0);
begin attribute keep : string;
attribute keep of dcm0_clk_ref_0 : signal is "TRUE";
attribute keep of dcm1_clk_ref_0 : signal is "TRUE";
p_powerup_reset : process(clk_sys) -- Misc FMC signals
begin
if rising_edge(clk_sys) then
if(VME_RST_n_i = '0' or rst_n_i = '0') then
powerup_rst_n <= '0';
elsif sys_locked = '1' then
if(powerup_reset_cnt = "11111111") then
powerup_rst_n <= '1';
else
powerup_rst_n <= '0';
powerup_reset_cnt <= powerup_reset_cnt + 1;
end if;
else
powerup_rst_n <= '0';
powerup_reset_cnt <= "00000000";
end if;
end if;
end process;
U_Buf_CLK_GTP : IBUFDS attribute iob : string;
generic map ( attribute iob of pps : signal is "FORCE";
DIFF_TERM => true,
IBUF_LOW_PWR => false -- Low power (TRUE) vs. performance (FALSE) setting for referenced
)
port map (
O => clk_125m_gtp,
I => clk_125m_gtp_p_i,
IB => clk_125m_gtp_n_i
);
begin -- architecture arch
cmp_sys_clk_pll : PLL_BASE areset_n <= vme_sysreset_n_i and rst_n_i;
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16, -- 125 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_pllref,
CLKOUT0 => pllout_clk_sys,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => sys_locked,
RST => '0',
CLKFBIN => pllout_clk_fb_pllref,
CLKIN => clk_125m_pllref);
cmp_dmtd_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16, -- 62.5 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_dmtd,
CLKOUT0 => pllout_clk_dmtd,
CLKOUT1 => open, --pllout_clk_sys,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
CLKFBIN => pllout_clk_fb_dmtd,
CLKIN => clk_20m_vcxo_buf);
-- rst_n_a <= VME_RST_n_i and rst_n_i;
U_Sync_Reset : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => powerup_rst_n,
synced_o => local_reset_n);
U_Buf_CLK_PLL : IBUFGDS cmp_xwb_metadata : entity work.xwb_metadata
generic map ( generic map (
DIFF_TERM => true, g_VENDOR_ID => x"0000_10DC",
IBUF_LOW_PWR => true -- Low power (TRUE) vs. performance (FALSE) setting for referenced g_DEVICE_ID => x"574E_caff", -- WRTD Node (WN) 1
) g_VERSION => x"0100_0000",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => (others => '0'))
port map ( port map (
O => clk_125m_pllref, -- Buffer output clk_i => clk_sys_62m5,
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port) rst_n_i => rst_sys_62m5_n,
IB => clk_125m_pllref_n_i -- Diff_n buffer input (connect directly to top-level port) wb_i => cnx_slave_in(c_WB_SLAVE_METADATA),
); wb_o => cnx_slave_out(c_WB_SLAVE_METADATA));
cmp_clk_sys_buf : BUFG inst_svec_base : entity work.svec_base_wr
port map (
O => clk_sys,
I => pllout_clk_sys);
cmp_clk_dmtd_buf : BUFG
port map (
O => clk_dmtd,
I => pllout_clk_dmtd);
cmp_clk_vcxo : BUFG
port map (
O => clk_20m_vcxo_buf,
I => clk_20m_vcxo_i);
gen_with_vme64_core : if g_SIM_BYPASS_VME = 0 generate
U_VME_Core : xvme64x_core
generic map (
g_CLOCK_PERIOD => 16,
g_DECODE_AM => TRUE,
g_USER_CSR_EXT => FALSE,
g_WB_GRANULARITY => BYTE,
g_MANUFACTURER_ID => c_CERN_ID,
g_BOARD_ID => c_SVEC_ID,
g_REVISION_ID => c_SVEC_REVISION_ID,
g_PROGRAM_ID => c_SVEC_PROGRAM_ID)
port map (
clk_i => clk_sys,
rst_n_i => local_reset_n,
vme_i.as_n => VME_AS_n_i,
vme_i.rst_n => VME_RST_n_i,
vme_i.write_n => VME_WRITE_n_i,
vme_i.am => VME_AM_i,
vme_i.ds_n => VME_DS_n_i,
vme_i.ga => VME_GA_i,
vme_i.lword_n => VME_LWORD_n_b,
vme_i.addr => VME_ADDR_b,
vme_i.data => VME_DATA_b,
vme_i.iack_n => VME_IACK_n_i,
vme_i.iackin_n => VME_IACKIN_n_i,
vme_o.berr_n => VME_BERR_n,
vme_o.dtack_n => VME_DTACK_n_o,
vme_o.retry_n => VME_RETRY_n_o,
vme_o.retry_oe => VME_RETRY_OE_o,
vme_o.lword_n => VME_LWORD_n_b_out,
vme_o.data => VME_DATA_b_out,
vme_o.addr => VME_ADDR_b_out,
vme_o.irq_n => VME_IRQ_n,
vme_o.iackout_n => VME_IACKOUT_n_o,
vme_o.dtack_oe => VME_DTACK_OE_o,
vme_o.data_dir => VME_DATA_DIR_int,
vme_o.data_oe_n => VME_DATA_OE_N_o,
vme_o.addr_dir => VME_ADDR_DIR_int,
vme_o.addr_oe_n => VME_ADDR_OE_N_o,
wb_o => cnx_slave_in(c_MASTER_VME),
wb_i => cnx_slave_out(c_MASTER_VME),
int_i => vic_master_irq);
VME_DATA_b <= VME_DATA_b_out when VME_DATA_DIR_int = '1' else (others => 'Z');
VME_ADDR_b <= VME_ADDR_b_out when VME_ADDR_DIR_int = '1' else (others => 'Z');
VME_LWORD_n_b <= VME_LWORD_n_b_out when VME_ADDR_DIR_int = '1' else 'Z';
VME_ADDR_DIR_o <= VME_ADDR_DIR_int;
VME_DATA_DIR_o <= VME_DATA_DIR_int;
-- BERR and IRQ vme signals are inverted by the drivers. See SVEC schematics.
VME_BERR_o <= not VME_BERR_n;
VME_IRQ_n_o <= not VME_IRQ_n;
end generate gen_with_vme64_core;
gen_without_vme64_core : if g_SIM_BYPASS_VME /= 0 generate
-- synthesis translate_off
cnx_slave_in(c_MASTER_VME) <= sim_wb_i;
sim_wb_o <= cnx_slave_out(c_MASTER_VME);
-- synthesis translate_on
end generate gen_without_vme64_core;
-- Tristates for FMC0 EEPROM: fixme: wire to WRCore
fmc0_scl_b <= '0' when (fd0_scl_out = '0') else 'Z';
fmc0_sda_b <= '0' when (fd0_sda_out = '0') else 'Z';
-- wrc_scl_in <= fmc_scl_b;
-- wrc_sda_in <= fmc_sda_b;
fd0_scl_in <= fmc0_scl_b;
fd0_sda_in <= fmc0_sda_b;
-- Tristates for FMC0 EEPROM: fixme: wire to WRCore
fmc1_scl_b <= '0' when (fd1_scl_out = '0') else 'Z';
fmc1_sda_b <= '0' when (fd1_sda_out = '0') else 'Z';
-- wrc_scl_in <= fmc_scl_b;
-- wrc_sda_in <= fmc_sda_b;
fd1_scl_in <= fmc1_scl_b;
fd1_sda_in <= fmc1_sda_b;
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
tempid_dq_b <= '0' when wrc_owr_en(0) = '1' else 'Z';
wrc_owr_in(0) <= tempid_dq_b;
U_WR_CORE : xwr_core
generic map ( generic map (
g_simulation => g_simulation, g_WITH_VIC => TRUE,
g_phys_uart => true, g_WITH_ONEWIRE => FALSE,
g_virtual_uart => true, g_WITH_SPI => FALSE,
g_with_external_clock_input => false, g_WITH_WR => TRUE,
g_aux_clks => 2, g_WITH_DDR4 => FALSE,
g_interface_mode => PIPELINED, g_WITH_DDR5 => FALSE,
g_address_granularity => BYTE, g_APP_OFFSET => c_METADATA_ADDR,
g_softpll_enable_debugger => false, g_NUM_USER_IRQ => 2,
g_dpram_initf => "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram") g_DPRAM_INITF => g_WRPC_INITF,
g_AUX_CLKS => 2,
g_FABRIC_IFACE => plain,
g_SIMULATION => g_SIMULATION,
g_VERBOSE => FALSE)
port map ( port map (
clk_sys_i => clk_sys, rst_n_i => areset_n,
clk_dmtd_i => clk_dmtd, clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_ref_i => clk_125m_pllref, clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_aux_i(0) => dcm0_clk_ref_0, clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_aux_i(1) => dcm1_clk_ref_0, clk_125m_gtp_n_i => clk_125m_gtp_n_i,
rst_n_i => local_reset_n, clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_aux_i(0) => dcm0_clk_ref_0,
dac_hpll_load_p1_o => dac_hpll_load_p1, clk_aux_i(1) => dcm1_clk_ref_0,
dac_hpll_data_o => dac_hpll_data, clk_10m_ext_i => '0',
dac_dpll_load_p1_o => dac_dpll_load_p1, pps_ext_i => '0',
dac_dpll_data_o => dac_dpll_data, vme_write_n_i => vme_write_n_i,
vme_sysreset_n_i => vme_sysreset_n_i,
phy_ref_clk_i => clk_125m_pllref, vme_retry_oe_o => vme_retry_oe_o,
phy_tx_data_o => phy_tx_data, vme_retry_n_o => vme_retry_n_o,
phy_tx_k_o => phy_tx_k, vme_lword_n_b => vme_lword_n_b,
phy_tx_disparity_i => phy_tx_disparity, vme_iackout_n_o => vme_iackout_n_o,
phy_tx_enc_err_i => phy_tx_enc_err, vme_iackin_n_i => vme_iackin_n_i,
phy_rx_data_i => phy_rx_data, vme_iack_n_i => vme_iack_n_i,
phy_rx_rbclk_i => phy_rx_rbclk, vme_gap_i => vme_gap_i,
phy_rx_k_i => phy_rx_k, vme_dtack_oe_o => vme_dtack_oe_o,
phy_rx_enc_err_i => phy_rx_enc_err, vme_dtack_n_o => vme_dtack_n_o,
phy_rx_bitslide_i => phy_rx_bitslide, vme_ds_n_i => vme_ds_n_i,
phy_rst_o => phy_rst, vme_data_oe_n_o => vme_data_oe_n_o,
phy_loopen_o => phy_loopen, vme_data_dir_o => vme_data_dir_o,
vme_berr_o => vme_berr_o,
led_link_o => led_link, vme_as_n_i => vme_as_n_i,
led_act_o => led_act, vme_addr_oe_n_o => vme_addr_oe_n_o,
vme_addr_dir_o => vme_addr_dir_o,
scl_o => wrc_scl_out, vme_irq_o => vme_irq_o,
scl_i => wrc_scl_in, vme_ga_i => vme_ga_i,
sda_o => wrc_sda_out, vme_data_b => vme_data_b,
sda_i => wrc_sda_in, vme_am_i => vme_am_i,
sfp_scl_o => sfp_scl_out, vme_addr_b => vme_addr_b,
sfp_scl_i => sfp_scl_in, fmc0_scl_b => fmc0_scl_b,
sfp_sda_o => sfp_sda_out, fmc0_sda_b => fmc0_sda_b,
sfp_sda_i => sfp_sda_in, fmc1_scl_b => fmc1_scl_b,
sfp_det_i => sfp_mod_def0_b, fmc1_sda_b => fmc1_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
uart_rxd_i => uart_rxd_i, fmc1_prsnt_m2c_n_i => fmc1_prsnt_m2c_n_i,
uart_txd_o => uart_txd_o, onewire_b => onewire_b,
carrier_scl_b => carrier_scl_b,
owr_en_o => wrc_owr_en, carrier_sda_b => carrier_sda_b,
owr_i => wrc_owr_in, spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
slave_i => cnx_master_out(c_SLAVE_WRCORE), spi_mosi_o => spi_mosi_o,
slave_o => cnx_master_in(c_SLAVE_WRCORE), spi_miso_i => spi_miso_i,
uart_rxd_i => uart_rxd_i,
--aux_master_o => etherbone_cfg_in, uart_txd_o => uart_txd_o,
--aux_master_i => etherbone_cfg_out, plldac_sclk_o => pll20dac_sclk_o,
plldac_din_o => pll20dac_din_o,
--wrf_src_o => etherbone_snk_in, pll20dac_din_o => pll20dac_din_o,
--wrf_src_i => etherbone_snk_out, pll20dac_sclk_o => pll20dac_sclk_o,
--wrf_snk_o => etherbone_src_in, pll20dac_sync_n_o => pll20dac_sync_n_o,
--wrf_snk_i => etherbone_src_out, pll25dac_din_o => pll25dac_din_o,
pll25dac_sclk_o => pll25dac_sclk_o,
btn1_i => '0', pll25dac_sync_n_o => pll25dac_sync_n_o,
btn2_i => '0', sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_mod_def0_i => sfp_mod_def0_i,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
pcbrev_i => pcbrev_i,
clk_dmtd_125m_o => clk_dmtd_125m,
clk_sys_62m5_o => clk_sys_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
clk_ref_125m_o => clk_ref_125m,
rst_ref_125m_n_o => open,
irq_user_i => irq_vector,
tm_link_up_o => tm_link_up, tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
tm_dac_value_o => tm_dac_value, tm_dac_value_o => tm_dac_value,
tm_dac_wr_o => tm_dac_wr, tm_dac_wr_o => tm_dac_wr,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en, tm_clk_aux_lock_en_i => tm_clk_aux_lock_en,
tm_clk_aux_locked_o => tm_clk_aux_locked, tm_clk_aux_locked_o => tm_clk_aux_locked,
tm_time_valid_o => tm_time_valid, pps_p_o => pps,
tm_tai_o => tm_utc, pps_led_o => pps_led,
tm_cycles_o => tm_cycles, link_ok_o => open,
led_link_o => wr_led_link,
rst_aux_n_o => etherbone_rst_n, led_act_o => wr_led_act,
pps_p_o => pps, app_wb_o => cnx_master_out(c_WB_MASTER_VME),
pps_led_o => pps_led app_wb_i => cnx_master_in(c_WB_MASTER_VME));
);
irq_vector(0) <= fd0_irq;
irq_vector(1) <= fd1_irq;
-----------------------------------------------------------------------------
-- Primary wishbone Crossbar
-----------------------------------------------------------------------------
U_DAC_Helper : spec_serial_dac cmp_sdb_crossbar : xwb_crossbar
generic map (
g_num_data_bits => 16,
g_num_extra_bits => 8,
g_num_cs_select => 1)
port map (
clk_i => clk_sys,
rst_n_i => local_reset_n,
value_i => dac_hpll_data,
cs_sel_i => "1",
load_i => dac_hpll_load_p1,
sclk_divsel_i => "010",
dac_cs_n_o(0) => pll20dac_sync_n_o,
dac_sclk_o => pll20dac_sclk_o,
dac_sdata_o => pll20dac_din_o,
xdone_o => open);
U_DAC_Main : spec_serial_dac
generic map (
g_num_data_bits => 16,
g_num_extra_bits => 8,
g_num_cs_select => 1)
port map (
clk_i => clk_sys,
rst_n_i => local_reset_n,
value_i => dac_dpll_data,
cs_sel_i => "1",
load_i => dac_dpll_load_p1,
sclk_divsel_i => "010",
dac_cs_n_o(0) => pll25dac_sync_n_o,
dac_sclk_o => pll25dac_sclk_o,
dac_sdata_o => pll25dac_din_o,
xdone_o => open);
--U_Etherbone : eb_slave_core
-- generic map (
-- g_sdb_address => f_resize_slv(c_sdb_address, 64))
-- port map (
-- clk_i => clk_sys,
-- nRst_i => etherbone_rst_n,
-- src_o => etherbone_src_out,
-- src_i => etherbone_src_in,
-- snk_o => etherbone_snk_out,
-- snk_i => etherbone_snk_in,
-- cfg_slave_o => etherbone_cfg_out,
-- cfg_slave_i => etherbone_cfg_in,
-- master_o => cnx_slave_in(c_MASTER_ETHERBONE),
-- master_i => cnx_slave_out(c_MASTER_ETHERBONE));
cnx_slave_in(c_MASTER_ETHERBONE).cyc <= '0';
U_Intercon : xwb_sdb_crossbar
generic map (
g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map (
clk_sys_i => clk_sys,
rst_n_i => local_reset_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
U_VIC : xwb_vic
generic map ( generic map (
g_interface_mode => PIPELINED, g_VERBOSE => FALSE,
g_address_granularity => BYTE, g_NUM_MASTERS => c_NUM_WB_MASTERS,
g_num_interrupts => 2, g_NUM_SLAVES => c_NUM_WB_SLAVES,
g_init_vectors => c_VIC_VECTOR_TABLE) g_REGISTERED => TRUE,
g_ADDRESS => c_WB_LAYOUT_ADDR,
g_MASK => c_WB_LAYOUT_MASK)
port map ( port map (
clk_sys_i => clk_sys, clk_sys_i => clk_sys_62m5,
rst_n_i => local_reset_n, rst_n_i => rst_sys_62m5_n,
slave_i => cnx_master_out(c_SLAVE_VIC), slave_i => cnx_master_out,
slave_o => cnx_master_in(c_SLAVE_VIC), slave_o => cnx_master_in,
irqs_i(0) => fd0_irq, master_i => cnx_slave_out,
irqs_i(1) => fd1_irq, master_o => cnx_slave_in);
irq_master_o => vic_master_irq);
gen_with_phy : if(g_with_wr_phy /= 0) generate
U_GTP : wr_gtp_phy_spartan6
generic map (
g_enable_ch0 => 0,
g_enable_ch1 => 1,
g_simulation => g_simulation)
port map (
gtp_clk_i => clk_125m_gtp,
ch0_ref_clk_i => clk_125m_pllref,
ch0_tx_data_i => x"00",
ch0_tx_k_i => '0',
ch0_tx_disparity_o => open,
ch0_tx_enc_err_o => open,
ch0_rx_rbclk_o => open,
ch0_rx_data_o => open,
ch0_rx_k_o => open,
ch0_rx_enc_err_o => open,
ch0_rx_bitslide_o => open,
ch0_rst_i => '1',
ch0_loopen_i => '0',
ch1_ref_clk_i => clk_125m_pllref,
ch1_tx_data_i => phy_tx_data,
ch1_tx_k_i => phy_tx_k(0),
ch1_tx_disparity_o => phy_tx_disparity,
ch1_tx_enc_err_o => phy_tx_enc_err,
ch1_rx_data_o => phy_rx_data,
ch1_rx_rbclk_o => phy_rx_rbclk,
ch1_rx_k_o => phy_rx_k(0),
ch1_rx_enc_err_o => phy_rx_enc_err,
ch1_rx_bitslide_o => phy_rx_bitslide,
ch1_rst_i => phy_rst,
ch1_loopen_i => '0', --phy_loopen,
pad_txn0_o => open,
pad_txp0_o => open,
pad_rxn0_i => '0',
pad_rxp0_i => '0',
pad_txn1_o => sfp_txn_o,
pad_txp1_o => sfp_txp_o,
pad_rxn1_i => sfp_rxn_i,
pad_rxp1_i => sfp_rxp_i);
end generate gen_with_phy;
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- FINE DELAY 0 INSTANTIATION -- FINE DELAY 0 INSTANTIATION
...@@ -919,8 +564,8 @@ begin ...@@ -919,8 +564,8 @@ begin
) )
port map ( port map (
O => fd0_tdc_start_predelay, -- Buffer output O => fd0_tdc_start_predelay, -- Buffer output
I => fd0_tdc_start_p_i, -- Diff_p buffer input (connect directly to top-level port) I => fmc0_fd_tdc_start_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => fd0_tdc_start_n_i -- Diff_n buffer input (connect directly to top-level port) IB => fmc0_fd_tdc_start_n_i -- Diff_n buffer input (connect directly to top-level port)
); );
cmp_fd_tdc_start_delay0 : IODELAY2 cmp_fd_tdc_start_delay0 : IODELAY2
...@@ -948,62 +593,63 @@ begin ...@@ -948,62 +593,63 @@ begin
port map ( port map (
RST => ddr0_pll_reset, RST => ddr0_pll_reset,
LOCKED => ddr0_pll_locked, LOCKED => ddr0_pll_locked,
CLK_IN1_P => fd0_clk_ref_p_i, CLK_IN1_P => fmc0_fd_clk_ref_p_i,
CLK_IN1_N => fd0_clk_ref_n_i, CLK_IN1_N => fmc0_fd_clk_ref_n_i,
CLK_OUT1 => dcm0_clk_ref_0, CLK_OUT1 => dcm0_clk_ref_0,
CLK_OUT2 => dcm0_clk_ref_180); CLK_OUT2 => dcm0_clk_ref_180);
ddr0_pll_reset <= not fd0_pll_status_i; ddr0_pll_reset <= not fmc0_fd_pll_status_i;
fd0_pll_status <= fd0_pll_status_i and ddr0_pll_locked; fd0_pll_status <= fmc0_fd_pll_status_i and ddr0_pll_locked;
U_FineDelay_Core0 : fine_delay_core U_FineDelay_Core0 : fine_delay_core
generic map ( generic map (
g_with_wr_core => true, g_with_wr_core => true,
g_simulation => f_int2bool(g_simulation), g_simulation => f_int2bool(g_simulation),
g_interface_mode => PIPELINED, g_interface_mode => PIPELINED,
g_address_granularity => BYTE) g_address_granularity => BYTE,
g_fmc_slot_id => 0)
port map ( port map (
clk_ref_0_i => dcm0_clk_ref_0, clk_ref_0_i => dcm0_clk_ref_0,
clk_ref_180_i => dcm0_clk_ref_180, clk_ref_180_i => dcm0_clk_ref_180,
clk_sys_i => clk_sys, clk_sys_i => clk_sys_62m5,
clk_dmtd_i => clk_dmtd, clk_dmtd_i => clk_dmtd_125m,
rst_n_i => local_reset_n, rst_n_i => rst_sys_62m5_n,
dcm_reset_o => open, dcm_reset_o => open,
dcm_locked_i => ddr0_pll_locked, dcm_locked_i => ddr0_pll_locked,
trig_a_i => fd0_trig_a_i, trig_a_i => fmc0_fd_trig_a_i,
tdc_cal_pulse_o => fd0_tdc_cal_pulse_o, tdc_cal_pulse_o => fmc0_fd_tdc_cal_pulse_o,
tdc_start_i => fd0_tdc_start, tdc_start_i => fd0_tdc_start,
dmtd_fb_in_i => fd0_dmtd_fb_in_i, dmtd_fb_in_i => fmc0_fd_dmtd_fb_in_i,
dmtd_fb_out_i => fd0_dmtd_fb_out_i, dmtd_fb_out_i => fmc0_fd_dmtd_fb_out_i,
dmtd_samp_o => fd0_dmtd_clk_o, dmtd_samp_o => fmc0_fd_dmtd_clk_o,
led_trig_o => fd0_led_trig_o, led_trig_o => fmc0_fd_led_trig_o,
ext_rst_n_o => fd0_ext_rst_n_o, ext_rst_n_o => fmc0_fd_ext_rst_n_o,
pll_status_i => fd0_pll_status, pll_status_i => fd0_pll_status,
acam_d_o => tdc0_data_out, acam_d_o => tdc0_data_out,
acam_d_i => tdc0_data_in, acam_d_i => tdc0_data_in,
acam_d_oen_o => tdc0_data_oe, acam_d_oen_o => tdc0_data_oe,
acam_emptyf_i => fd0_tdc_emptyf_i, acam_emptyf_i => fmc0_fd_tdc_emptyf_i,
acam_alutrigger_o => fd0_tdc_alutrigger_o, acam_alutrigger_o => fmc0_fd_tdc_alutrigger_o,
acam_wr_n_o => fd0_tdc_wr_n_o, acam_wr_n_o => fmc0_fd_tdc_wr_n_o,
acam_rd_n_o => fd0_tdc_rd_n_o, acam_rd_n_o => fmc0_fd_tdc_rd_n_o,
acam_start_dis_o => fd0_tdc_start_dis_o, acam_start_dis_o => fmc0_fd_tdc_start_dis_o,
acam_stop_dis_o => fd0_tdc_stop_dis_o, acam_stop_dis_o => fmc0_fd_tdc_stop_dis_o,
spi_cs_dac_n_o => fd0_spi_cs_dac_n_o, spi_cs_dac_n_o => fmc0_fd_spi_cs_dac_n_o,
spi_cs_pll_n_o => fd0_spi_cs_pll_n_o, spi_cs_pll_n_o => fmc0_fd_spi_cs_pll_n_o,
spi_cs_gpio_n_o => fd0_spi_cs_gpio_n_o, spi_cs_gpio_n_o => fmc0_fd_spi_cs_gpio_n_o,
spi_sclk_o => fd0_spi_sclk_o, spi_sclk_o => fmc0_fd_spi_sclk_o,
spi_mosi_o => fd0_spi_mosi_o, spi_mosi_o => fmc0_fd_spi_mosi_o,
spi_miso_i => fd0_spi_miso_i, spi_miso_i => fmc0_fd_spi_miso_i,
delay_len_o => fd0_delay_len_o, delay_len_o => fmc0_fd_delay_len_o,
delay_val_o => fd0_delay_val_o, delay_val_o => fmc0_fd_delay_val_o,
delay_pulse_o => fd0_delay_pulse_o, delay_pulse_o => fmc0_fd_delay_pulse_o,
tm_link_up_i => tm_link_up, tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid, tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles, tm_cycles_i => tm_cycles,
tm_utc_i => tm_utc, tm_utc_i => tm_tai,
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en(0), tm_clk_aux_lock_en_o => tm_clk_aux_lock_en(0),
tm_clk_aux_locked_i => tm_clk_aux_locked(0), tm_clk_aux_locked_i => tm_clk_aux_locked(0),
tm_clk_dmtd_locked_i => '1', tm_clk_dmtd_locked_i => '1',
...@@ -1016,36 +662,35 @@ begin ...@@ -1016,36 +662,35 @@ begin
i2c_scl_i => fd0_scl_in, i2c_scl_i => fd0_scl_in,
i2c_sda_oen_o => fd0_sda_out, i2c_sda_oen_o => fd0_sda_out,
i2c_sda_i => fd0_sda_in, i2c_sda_i => fd0_sda_in,
fmc_present_n_i => fmc0_prsntm2c_n_i, fmc_present_n_i => fmc0_prsnt_m2c_n_i,
idelay_cal_o => fd0_tdc_start_iodelay_cal, idelay_cal_o => fd0_tdc_start_iodelay_cal,
idelay_rst_o => fd0_tdc_start_iodelay_rst, idelay_rst_o => fd0_tdc_start_iodelay_rst,
idelay_ce_o => fd0_tdc_start_iodelay_ce, idelay_ce_o => fd0_tdc_start_iodelay_ce,
idelay_inc_o => fd0_tdc_start_iodelay_inc, idelay_inc_o => fd0_tdc_start_iodelay_inc,
wb_adr_i => cnx_master_out(c_SLAVE_FD0).adr, wb_adr_i => cnx_slave_in(c_WB_SLAVE_FD0).adr,
wb_dat_i => cnx_master_out(c_SLAVE_FD0).dat, wb_dat_i => cnx_slave_in(c_WB_SLAVE_FD0).dat,
wb_dat_o => cnx_master_in(c_SLAVE_FD0).dat, wb_dat_o => cnx_slave_out(c_WB_SLAVE_FD0).dat,
wb_sel_i => cnx_master_out(c_SLAVE_FD0).sel, wb_sel_i => cnx_slave_in(c_WB_SLAVE_FD0).sel,
wb_cyc_i => cnx_master_out(c_SLAVE_FD0).cyc, wb_cyc_i => cnx_slave_in(c_WB_SLAVE_FD0).cyc,
wb_stb_i => cnx_master_out(c_SLAVE_FD0).stb, wb_stb_i => cnx_slave_in(c_WB_SLAVE_FD0).stb,
wb_we_i => cnx_master_out(c_SLAVE_FD0).we, wb_we_i => cnx_slave_in(c_WB_SLAVE_FD0).we,
wb_ack_o => cnx_master_in(c_SLAVE_FD0).ack, wb_ack_o => cnx_slave_out(c_WB_SLAVE_FD0).ack,
wb_stall_o => cnx_master_in(c_SLAVE_FD0).stall, wb_stall_o => cnx_slave_out(c_WB_SLAVE_FD0).stall,
wb_irq_o => fd0_irq, wb_irq_o => fd0_irq);
dbg_o => fd0_dbg);
cnx_slave_out(c_WB_SLAVE_FD0).err <= '0';
cnx_master_in(c_SLAVE_FD0).err <= '0'; cnx_slave_out(c_WB_SLAVE_FD0).rty <= '0';
cnx_master_in(c_SLAVE_FD0).rty <= '0';
-- tristate buffer for the TDC data bus: -- tristate buffer for the TDC data bus:
fd0_tdc_d_b <= tdc0_data_out when tdc0_data_oe = '1' else (others => 'Z'); fmc0_fd_tdc_d_b <= tdc0_data_out when tdc0_data_oe = '1' else (others => 'Z');
fd0_tdc_oe_n_o <= '1'; fmc0_fd_tdc_oe_n_o <= '1';
tdc0_data_in <= fd0_tdc_d_b; tdc0_data_in <= fmc0_fd_tdc_d_b;
fd0_onewire_b <= '0' when fd0_owr_en = '1' else 'Z'; fmc0_fd_onewire_b <= '0' when fd0_owr_en = '1' else 'Z';
fd0_owr_in <= fd0_onewire_b; fd0_owr_in <= fmc0_fd_onewire_b;
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -1059,8 +704,8 @@ begin ...@@ -1059,8 +704,8 @@ begin
) )
port map ( port map (
O => fd1_tdc_start_predelay, -- Buffer output O => fd1_tdc_start_predelay, -- Buffer output
I => fd1_tdc_start_p_i, -- Diff_p buffer input (connect directly to top-level port) I => fmc1_fd_tdc_start_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => fd1_tdc_start_n_i -- Diff_n buffer input (connect directly to top-level port) IB => fmc1_fd_tdc_start_n_i -- Diff_n buffer input (connect directly to top-level port)
); );
cmp_fd_tdc_start_delay1 : IODELAY2 cmp_fd_tdc_start_delay1 : IODELAY2
...@@ -1088,62 +733,63 @@ begin ...@@ -1088,62 +733,63 @@ begin
port map ( port map (
RST => ddr1_pll_reset, RST => ddr1_pll_reset,
LOCKED => ddr1_pll_locked, LOCKED => ddr1_pll_locked,
CLK_IN1_P => fd1_clk_ref_p_i, CLK_IN1_P => fmc1_fd_clk_ref_p_i,
CLK_IN1_N => fd1_clk_ref_n_i, CLK_IN1_N => fmc1_fd_clk_ref_n_i,
CLK_OUT1 => dcm1_clk_ref_0, CLK_OUT1 => dcm1_clk_ref_0,
CLK_OUT2 => dcm1_clk_ref_180); CLK_OUT2 => dcm1_clk_ref_180);
ddr1_pll_reset <= not fd1_pll_status_i; ddr1_pll_reset <= not fmc1_fd_pll_status_i;
fd1_pll_status <= fd1_pll_status_i and ddr1_pll_locked; fd1_pll_status <= fmc1_fd_pll_status_i and ddr1_pll_locked;
U_FineDelay_Core1 : fine_delay_core U_FineDelay_Core1 : fine_delay_core
generic map ( generic map (
g_with_wr_core => true, g_with_wr_core => true,
g_simulation => f_int2bool(g_simulation), g_simulation => f_int2bool(g_simulation),
g_interface_mode => PIPELINED, g_interface_mode => PIPELINED,
g_address_granularity => BYTE) g_address_granularity => BYTE,
g_fmc_slot_id => 1)
port map ( port map (
clk_ref_0_i => dcm1_clk_ref_0, clk_ref_0_i => dcm1_clk_ref_0,
clk_ref_180_i => dcm1_clk_ref_180, clk_ref_180_i => dcm1_clk_ref_180,
clk_sys_i => clk_sys, clk_sys_i => clk_sys_62m5,
clk_dmtd_i => clk_dmtd, clk_dmtd_i => clk_dmtd_125m,
rst_n_i => local_reset_n, rst_n_i => rst_sys_62m5_n,
dcm_reset_o => open, dcm_reset_o => open,
dcm_locked_i => ddr1_pll_locked, dcm_locked_i => ddr1_pll_locked,
trig_a_i => fd1_trig_a_i, trig_a_i => fmc1_fd_trig_a_i,
tdc_cal_pulse_o => fd1_tdc_cal_pulse_o, tdc_cal_pulse_o => fmc1_fd_tdc_cal_pulse_o,
tdc_start_i => fd1_tdc_start, tdc_start_i => fd1_tdc_start,
dmtd_fb_in_i => fd1_dmtd_fb_in_i, dmtd_fb_in_i => fmc1_fd_dmtd_fb_in_i,
dmtd_fb_out_i => fd1_dmtd_fb_out_i, dmtd_fb_out_i => fmc1_fd_dmtd_fb_out_i,
dmtd_samp_o => fd1_dmtd_clk_o, dmtd_samp_o => fmc1_fd_dmtd_clk_o,
led_trig_o => fd1_led_trig_o, led_trig_o => fmc1_fd_led_trig_o,
ext_rst_n_o => fd1_ext_rst_n_o, ext_rst_n_o => fmc1_fd_ext_rst_n_o,
pll_status_i => fd1_pll_status, pll_status_i => fd1_pll_status,
acam_d_o => tdc1_data_out, acam_d_o => tdc1_data_out,
acam_d_i => tdc1_data_in, acam_d_i => tdc1_data_in,
acam_d_oen_o => tdc1_data_oe, acam_d_oen_o => tdc1_data_oe,
acam_emptyf_i => fd1_tdc_emptyf_i, acam_emptyf_i => fmc1_fd_tdc_emptyf_i,
acam_alutrigger_o => fd1_tdc_alutrigger_o, acam_alutrigger_o => fmc1_fd_tdc_alutrigger_o,
acam_wr_n_o => fd1_tdc_wr_n_o, acam_wr_n_o => fmc1_fd_tdc_wr_n_o,
acam_rd_n_o => fd1_tdc_rd_n_o, acam_rd_n_o => fmc1_fd_tdc_rd_n_o,
acam_start_dis_o => fd1_tdc_start_dis_o, acam_start_dis_o => fmc1_fd_tdc_start_dis_o,
acam_stop_dis_o => fd1_tdc_stop_dis_o, acam_stop_dis_o => fmc1_fd_tdc_stop_dis_o,
spi_cs_dac_n_o => fd1_spi_cs_dac_n_o, spi_cs_dac_n_o => fmc1_fd_spi_cs_dac_n_o,
spi_cs_pll_n_o => fd1_spi_cs_pll_n_o, spi_cs_pll_n_o => fmc1_fd_spi_cs_pll_n_o,
spi_cs_gpio_n_o => fd1_spi_cs_gpio_n_o, spi_cs_gpio_n_o => fmc1_fd_spi_cs_gpio_n_o,
spi_sclk_o => fd1_spi_sclk_o, spi_sclk_o => fmc1_fd_spi_sclk_o,
spi_mosi_o => fd1_spi_mosi_o, spi_mosi_o => fmc1_fd_spi_mosi_o,
spi_miso_i => fd1_spi_miso_i, spi_miso_i => fmc1_fd_spi_miso_i,
delay_len_o => fd1_delay_len_o, delay_len_o => fmc1_fd_delay_len_o,
delay_val_o => fd1_delay_val_o, delay_val_o => fmc1_fd_delay_val_o,
delay_pulse_o => fd1_delay_pulse_o, delay_pulse_o => fmc1_fd_delay_pulse_o,
tm_link_up_i => tm_link_up, tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid, tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles, tm_cycles_i => tm_cycles,
tm_utc_i => tm_utc, tm_utc_i => tm_tai,
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en(1), tm_clk_aux_lock_en_o => tm_clk_aux_lock_en(1),
tm_clk_aux_locked_i => tm_clk_aux_locked(1), tm_clk_aux_locked_i => tm_clk_aux_locked(1),
tm_clk_dmtd_locked_i => '1', -- FIXME: fan out real signal from the tm_clk_dmtd_locked_i => '1', -- FIXME: fan out real signal from the
...@@ -1157,122 +803,116 @@ begin ...@@ -1157,122 +803,116 @@ begin
i2c_scl_i => fd1_scl_in, i2c_scl_i => fd1_scl_in,
i2c_sda_oen_o => fd1_sda_out, i2c_sda_oen_o => fd1_sda_out,
i2c_sda_i => fd1_sda_in, i2c_sda_i => fd1_sda_in,
fmc_present_n_i => fmc1_prsntm2c_n_i, fmc_present_n_i => fmc1_prsnt_m2c_n_i,
idelay_cal_o => fd1_tdc_start_iodelay_cal, idelay_cal_o => fd1_tdc_start_iodelay_cal,
idelay_rst_o => fd1_tdc_start_iodelay_rst, idelay_rst_o => fd1_tdc_start_iodelay_rst,
idelay_ce_o => fd1_tdc_start_iodelay_ce, idelay_ce_o => fd1_tdc_start_iodelay_ce,
idelay_inc_o => fd1_tdc_start_iodelay_inc, idelay_inc_o => fd1_tdc_start_iodelay_inc,
wb_adr_i => cnx_master_out(c_SLAVE_FD1).adr, wb_adr_i => cnx_slave_in(c_WB_SLAVE_FD1).adr,
wb_dat_i => cnx_master_out(c_SLAVE_FD1).dat, wb_dat_i => cnx_slave_in(c_WB_SLAVE_FD1).dat,
wb_dat_o => cnx_master_in(c_SLAVE_FD1).dat, wb_dat_o => cnx_slave_out(c_WB_SLAVE_FD1).dat,
wb_sel_i => cnx_master_out(c_SLAVE_FD1).sel, wb_sel_i => cnx_slave_in(c_WB_SLAVE_FD1).sel,
wb_cyc_i => cnx_master_out(c_SLAVE_FD1).cyc, wb_cyc_i => cnx_slave_in(c_WB_SLAVE_FD1).cyc,
wb_stb_i => cnx_master_out(c_SLAVE_FD1).stb, wb_stb_i => cnx_slave_in(c_WB_SLAVE_FD1).stb,
wb_we_i => cnx_master_out(c_SLAVE_FD1).we, wb_we_i => cnx_slave_in(c_WB_SLAVE_FD1).we,
wb_ack_o => cnx_master_in(c_SLAVE_FD1).ack, wb_ack_o => cnx_slave_out(c_WB_SLAVE_FD1).ack,
wb_stall_o => cnx_master_in(c_SLAVE_FD1).stall, wb_stall_o => cnx_slave_out(c_WB_SLAVE_FD1).stall,
wb_irq_o => fd1_irq); wb_irq_o => fd1_irq);
cnx_master_in(c_SLAVE_FD1).err <= '0'; cnx_slave_out(c_WB_SLAVE_FD1).err <= '0';
cnx_master_in(c_SLAVE_FD1).rty <= '0'; cnx_slave_out(c_WB_SLAVE_FD1).rty <= '0';
-- tristate buffer for the TDC data bus: -- tristate buffer for the TDC data bus:
fd1_tdc_d_b <= tdc1_data_out when tdc1_data_oe = '1' else (others => 'Z'); fmc1_fd_tdc_d_b <= tdc1_data_out when tdc1_data_oe = '1' else (others => 'Z');
fd1_tdc_oe_n_o <= '1'; fmc1_fd_tdc_oe_n_o <= '1';
tdc1_data_in <= fd1_tdc_d_b; tdc1_data_in <= fmc1_fd_tdc_d_b;
fd1_onewire_b <= '0' when fd1_owr_en = '1' else 'Z'; fmc1_fd_onewire_b <= '0' when fd1_owr_en = '1' else 'Z';
fd1_owr_in <= fd1_onewire_b; fd1_owr_in <= fmc1_fd_onewire_b;
U_LED_Controller : bicolor_led_ctrl cmp_vme_led_extend : gc_extend_pulse
generic map (
g_width => 5000000)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
pulse_i => cnx_slave_in(c_WB_MASTER_VME).cyc,
extended_o => vme_access_led);
-----------------------------------------------------------------------------
-- Carrier front panel LEDs and LEMOs
-----------------------------------------------------------------------------
cmp_led_controller : gc_bicolor_led_ctrl
generic map( generic map(
g_NB_COLUMN => 4, g_NB_COLUMN => 4,
g_NB_LINE => 2, g_NB_LINE => 2,
g_CLK_FREQ => 62500000, -- in Hz g_CLK_FREQ => 62500000, -- in Hz
g_REFRESH_RATE => 250 -- in Hz g_REFRESH_RATE => 250 -- in Hz
) )
port map( port map(
rst_n_i => local_reset_n, rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys, clk_i => clk_sys_62m5,
led_intensity_i => "1100100", -- in % led_intensity_i => "1100100", -- in %
led_state_i => led_state, led_state_i => svec_led,
column_o => fp_led_column_o, column_o => fp_led_column_o,
line_o => fp_led_line_o, line_o => fp_led_line_o,
line_oen_o => fp_led_line_oen_o line_oen_o => fp_led_line_oen_o);
);
U_Drive_VME_Access_Led : gc_extend_pulse
generic map (
g_width => 5000000)
port map (
clk_i => clk_sys,
rst_n_i => local_reset_n,
pulse_i => cnx_slave_in(c_MASTER_VME).cyc,
extended_o => vme_access);
U_Drive_PPS : gc_extend_pulse
generic map (
g_width => 5000000)
port map (
clk_i => clk_125m_pllref,
rst_n_i => local_reset_n,
pulse_i => pps,
extended_o => pps_ext);
-- Drive the front panel LEDs: -- Drive the front panel LEDs:
-- LED 1: WR Link status -- LED 1: WR Link status
led_state(6) <= led_link; svec_led(6) <= wr_led_link;
led_state(7) <= '0'; svec_led(7) <= '0';
-- LED 2: WR Link activity status -- LED 2: WR Link activity status
led_state(4) <= led_act; svec_led(4) <= wr_led_act;
led_state(5) <= '0'; svec_led(5) <= '0';
-- LED 3: WR PPS blink -- LED 3: WR PPS blink
led_state(2) <= pps_ext; svec_led(2) <= pps_led;
led_state(3) <= '0'; svec_led(3) <= '0';
-- LED 4: WR Time validity -- LED 4: WR Time validity
led_state(0) <= tm_time_valid; svec_led(0) <= tm_time_valid;
led_state(1) <= '0'; svec_led(1) <= '0';
-- LED 5: VME access -- LED 5: VME access
led_state(14) <= vme_access; svec_led(14) <= vme_access_led;
led_state(15) <= '0'; svec_led(15) <= '0';
-- LED 6: FD0 locked to WR -- LED 6: FD0 locked to WR
led_state(12) <= tm_clk_aux_locked(0); svec_led(12) <= tm_clk_aux_locked(0);
led_state(13) <= '0'; svec_led(13) <= '0';
-- LED 6: FD1 locked to WR -- LED 6: FD1 locked to WR
led_state(10) <= tm_clk_aux_locked(1); svec_led(10) <= tm_clk_aux_locked(1);
led_state(11) <= '0'; svec_led(11) <= '0';
led_state(8) <= '0'; svec_led(8) <= '0';
led_state(9) <= '0'; svec_led(9) <= '0';
-- The SFP is permanently enabled. -- Div by 2 reference clock to LEMO connector
sfp_tx_disable_o <= '0'; process(clk_ref_125m)
begin
-- Debug signals assignments (FP lemos) if rising_edge(clk_ref_125m) then
clk_ref_div2 <= not clk_ref_div2;
end if;
end process;
-- Front panel IO configuration
fp_gpio1_b <= pps;
fp_gpio2_b <= clk_ref_div2;
fp_term_en_o <= (others => '0');
fp_gpio1_a2b_o <= '1'; fp_gpio1_a2b_o <= '1';
fp_gpio2_a2b_o <= '1'; fp_gpio2_a2b_o <= '1';
fp_gpio34_a2b_o <= '1'; fp_gpio34_a2b_o <= '0';
fp_gpio1_b <= fd0_dbg(0);
fp_gpio2_b <= fd0_dbg(1);
fp_gpio3_b <= fd0_dbg(2);
fp_gpio4_b <= fd0_dbg(3);
end rtl;
end architecture arch;
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