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FMC DEL 1ns 4cha
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FMC DEL 1ns 4cha
Commits
a9d3e9cc
Commit
a9d3e9cc
authored
Apr 26, 2012
by
Tomasz Wlostowski
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software/lib: applied Matthieu's patches, fixing operation of multiple cards in the same PC
parent
a072a95e
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5 changed files
with
35 additions
and
11 deletions
+35
-11
Makefile
software/lib/Makefile
+3
-3
fdelay_bus.c
software/lib/fdelay_bus.c
+13
-2
fdelay_cal.c
software/lib/fdelay_cal.c
+1
-1
fdelay_lib.c
software/lib/fdelay_lib.c
+12
-5
rr_io.c
software/lib/rr_io.c
+6
-0
No files found.
software/lib/Makefile
View file @
a9d3e9cc
...
...
@@ -5,7 +5,7 @@ CFLAGS = -I../include -g -Imini_bone -Ispll
OBJS_LIB
=
fdelay_lib.o fdelay_bus.o rr_io.o i2c_master.o onewire.o mini_bone/minibone_lib.o mini_bone/ptpd_netif.o spec_common.o
all
:
testprog lib testprog
2 testprog
3 testprog4
all
:
testprog lib testprog3 testprog4
lib
:
$(OBJS_LIB)
gcc
-shared
-o
libfinedelay.so
$(OBJS_LIB)
...
...
@@ -13,8 +13,8 @@ lib: $(OBJS_LIB)
testprog
:
lib fdelay_test.o
gcc
-o
fdelay_test
$(OBJS_LIB)
fdelay_test.o
-lm
testprog2
:
lib fdelay_cal.o
gcc
-o
fdelay_cal
$(OBJS_LIB)
fdelay_cal.o
-lm
#
testprog2: lib fdelay_cal.o
#
gcc -o fdelay_cal $(OBJS_LIB) fdelay_cal.o -lm
testprog3
:
lib fdelay_pps_demo.o
gcc
-o
fdelay_pps_demo
$(OBJS_LIB)
fdelay_pps_demo.o
-lm
...
...
software/lib/fdelay_bus.c
View file @
a9d3e9cc
...
...
@@ -36,10 +36,10 @@ uint32_t d = mbn_readl(priv, addr >> 2);
return
d
;
}
fdelay_device_t
*
fdelay_create_rawrabbit
(
uint32_t
base_addr
)
fdelay_device_t
*
fdelay_create_rawrabbit
(
int
fd
,
uint32_t
base_addr
)
{
fdelay_device_t
*
dev
=
malloc
(
sizeof
(
fdelay_device_t
));
rr_
init
(
RR_DEVSEL_UNUSED
,
RR_DEVSEL_UNUSED
);
rr_
bind
(
fd
);
dev
->
writel
=
my_rr_writel
;
dev
->
readl
=
my_rr_readl
;
dev
->
base_addr
=
base_addr
;
...
...
@@ -68,3 +68,14 @@ fdelay_device_t *fdelay_create_minibone(char *iface, char *mac_addr, uint32_t ba
return
dev
;
}
int
fdelay_load_firmware
(
const
char
*
path
)
{
fprintf
(
stderr
,
"Booting up the FPGA with %s.
\n
"
,
path
);
if
(
rr_load_bitstream_from_file
(
path
)
<
0
)
{
fprintf
(
stderr
,
"Failed to load FPGA bitstream.
\n
"
);
return
-
1
;
}
return
0
;
}
\ No newline at end of file
software/lib/fdelay_cal.c
View file @
a9d3e9cc
...
...
@@ -71,7 +71,7 @@ main()
{
fdelay_device_t
*
dev
=
malloc
(
sizeof
(
fdelay_device_t
));
rr_init
();
rr_init
(
RR_DEVSEL_UNUSED
,
RR_DEVSEL_UNUSED
);
dev
->
writel
=
my_writel
;
dev
->
readl
=
my_readl
;
...
...
software/lib/fdelay_lib.c
View file @
a9d3e9cc
...
...
@@ -1173,6 +1173,7 @@ int fdelay_configure_output(fdelay_device_t *dev, int channel, int enable, int64
end
=
fdelay_from_picos
(
delay_ps
+
width_ps
);
delta
=
fdelay_from_picos
(
delta_ps
);
// printf("Start: %lld: %d:%d\n", start.utc, start.coarse, start.frac);
...
...
@@ -1222,11 +1223,17 @@ int fdelay_configure_pulse_gen(fdelay_device_t *dev, int channel, int enable, fd
if
(
channel
<
1
||
channel
>
4
)
return
-
1
;
start
=
t_start
;
end
=
ts_add
(
start
,
fdelay_from_picos
(
width_ps
)
);
end
=
fdelay_from_picos
(
fdelay_to_picos
(
start
)
+
width_ps
-
4000
);
delta
=
fdelay_from_picos
(
delta_ps
);
// printf("Start: %lld: %d:%d\n", start.utc, start.coarse, start.frac);
//start = t_start;
//end = ts_add(start, fdelay_from_picos(width_ps));
//delta = fdelay_from_picos(delta_ps);
//printf("Start: %lld: %d:%d\n", start.utc, start.coarse, start.frac);
//printf("width: %lld delta: %lld rep: %d\n", width_ps, delta_ps, rep_count);
chan_writel
(
hw
->
frr_cur
[
channel
-
1
],
FD_REG_FRR
);
...
...
software/lib/rr_io.c
View file @
a9d3e9cc
...
...
@@ -18,6 +18,12 @@
static
int
fd
;
int
rr_bind
(
int
a_fd
)
{
fd
=
a_fd
;
return
0
;
}
int
rr_init
(
int
bus
,
int
devfn
)
{
struct
rr_devsel
devsel
;
...
...
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