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FMC DEL 1ns 4cha
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FMC DEL 1ns 4cha
Commits
7141e6e3
Commit
7141e6e3
authored
Feb 18, 2013
by
Tomasz Wlostowski
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acam: work in G mode instead of R mode (appears to fix 1.5 ns bug)
parent
ef47a7bd
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5 changed files
with
163 additions
and
57 deletions
+163
-57
acam_gpx.h
software/include/acam_gpx.h
+9
-1
fd_channel_regs.h
software/include/fd_channel_regs.h
+3
-3
fd_main_regs.h
software/include/fd_main_regs.h
+24
-24
fdelay_private.h
software/include/fdelay_private.h
+1
-0
fdelay_lib.c
software/lib/fdelay_lib.c
+126
-29
No files found.
software/include/acam_gpx.h
View file @
7141e6e3
...
@@ -20,7 +20,15 @@
...
@@ -20,7 +20,15 @@
#define AR2_Disable(chan) (1<<(3+chan))
#define AR2_Disable(chan) (1<<(3+chan))
#define AR2_Adj(chan, value) (((value)&0xf)<<(12+4*(chan-7)))
#define AR2_Adj(chan, value) (((value)&0xf)<<(12+4*(chan-7)))
#define AR3_RaSpeed(num,val) (val << (num*2 + 21))
#define AR2_DelRise1(value) (((value)&0x3)<<(20))
#define AR2_DelFall1(value) (((value)&0x3)<<(22))
#define AR2_DelRise2(value) (((value)&0x3)<<(24))
#define AR2_DelFall2(value) (((value)&0x3)<<(26))
#define AR3_DelTx(chan, value) (((value)&0x3)<<(5 + (chan -1 ) * 2))
#define AR3_RaSpeed(chan, value) (((value)&0x3)<<(21 + (chan ) * 2))
#define AR4_RaSpeed(chan, value) (((value)&0x3)<<(10 + (chan-3) * 2))
#define AR3_Zero (0) // nothing interesting for the Fine Delay
#define AR3_Zero (0) // nothing interesting for the Fine Delay
...
...
software/include/fd_channel_regs.h
View file @
7141e6e3
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
* File : fd_channel_regs.h
* File : fd_channel_regs.h
* Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
* Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
* Created :
Wed Apr 11 11:05:22 2012
* Created :
Fri Feb 15 12:07:17 2013
* Standard : ANSI C
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
...
@@ -57,7 +57,7 @@
...
@@ -57,7 +57,7 @@
/* definitions for field: Disable Fine Part update in reg: Delay Control Register */
/* definitions for field: Disable Fine Part update in reg: Delay Control Register */
#define FD_DCR_NO_FINE WBGEN2_GEN_MASK(7, 1)
#define FD_DCR_NO_FINE WBGEN2_GEN_MASK(7, 1)
/* definitions for field:
Disable Fine Part update
in reg: Delay Control Register */
/* definitions for field:
Force Output High
in reg: Delay Control Register */
#define FD_DCR_FORCE_HI WBGEN2_GEN_MASK(8, 1)
#define FD_DCR_FORCE_HI WBGEN2_GEN_MASK(8, 1)
/* definitions for register: Fine Range Register */
/* definitions for register: Fine Range Register */
...
...
software/include/fd_main_regs.h
View file @
7141e6e3
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
* File : fd_main_regs.h
* File : fd_main_regs.h
* Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
* Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
* Created :
Mon Jun 4 13:42:20 2012
* Created :
Fri Feb 15 12:07:16 2013
* Standard : ANSI C
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
...
@@ -64,7 +64,7 @@
...
@@ -64,7 +64,7 @@
/* definitions for field: PLL Locked in reg: Global Control Register */
/* definitions for field: PLL Locked in reg: Global Control Register */
#define FD_GCR_DDR_LOCKED WBGEN2_GEN_MASK(2, 1)
#define FD_GCR_DDR_LOCKED WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Mezzani
c
e Present in reg: Global Control Register */
/* definitions for field: Mezzani
n
e Present in reg: Global Control Register */
#define FD_GCR_FMC_PRESENT WBGEN2_GEN_MASK(3, 1)
#define FD_GCR_FMC_PRESENT WBGEN2_GEN_MASK(3, 1)
/* definitions for register: Timing Control Register */
/* definitions for register: Timing Control Register */
...
@@ -99,46 +99,46 @@
...
@@ -99,46 +99,46 @@
/* definitions for register: Time Register - sub-second 125 MHz clock cycles */
/* definitions for register: Time Register - sub-second 125 MHz clock cycles */
/* definitions for register: TDC Data Register */
/* definitions for register:
Host-driven
TDC Data Register */
/* definitions for register:
TDC control/status reg
*/
/* definitions for register:
Host-driven TDC Control/Status
*/
/* definitions for field:
Start TDC write in reg: TDC control/status reg
*/
/* definitions for field:
Write to TDC in reg: Host-driven TDC Control/Status
*/
#define FD_TDCSR_WRITE WBGEN2_GEN_MASK(0, 1)
#define FD_TDCSR_WRITE WBGEN2_GEN_MASK(0, 1)
/* definitions for field:
Start TDC read in reg: TDC control/status reg
*/
/* definitions for field:
Read from TDC in reg: Host-driven TDC Control/Status
*/
#define FD_TDCSR_READ WBGEN2_GEN_MASK(1, 1)
#define FD_TDCSR_READ WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Empty flag in reg:
TDC control/status reg
*/
/* definitions for field: Empty flag in reg:
Host-driven TDC Control/Status
*/
#define FD_TDCSR_EMPTY WBGEN2_GEN_MASK(2, 1)
#define FD_TDCSR_EMPTY WBGEN2_GEN_MASK(2, 1)
/* definitions for field: St
art enable in reg: TDC control/status reg
*/
/* definitions for field: St
op enable in reg: Host-driven TDC Control/Status
*/
#define FD_TDCSR_STOP_EN WBGEN2_GEN_MASK(3, 1)
#define FD_TDCSR_STOP_EN WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Start disable in reg:
TDC control/status reg
*/
/* definitions for field: Start disable in reg:
Host-driven TDC Control/Status
*/
#define FD_TDCSR_START_DIS WBGEN2_GEN_MASK(4, 1)
#define FD_TDCSR_START_DIS WBGEN2_GEN_MASK(4, 1)
/* definitions for field: St
op enable in reg: TDC control/status reg
*/
/* definitions for field: St
art enable in reg: Host-driven TDC Control/Status
*/
#define FD_TDCSR_START_EN WBGEN2_GEN_MASK(5, 1)
#define FD_TDCSR_START_EN WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Stop disable in reg:
TDC control/status reg
*/
/* definitions for field: Stop disable in reg:
Host-driven TDC Control/Status
*/
#define FD_TDCSR_STOP_DIS WBGEN2_GEN_MASK(6, 1)
#define FD_TDCSR_STOP_DIS WBGEN2_GEN_MASK(6, 1)
/* definitions for field:
write 1: Pulse the Alutrigger line in reg: TDC control/status reg
*/
/* definitions for field:
Pulse <code>Alutrigger</code> line in reg: Host-driven TDC Control/Status
*/
#define FD_TDCSR_ALUTRIG WBGEN2_GEN_MASK(7, 1)
#define FD_TDCSR_ALUTRIG WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Calibration register */
/* definitions for register: Calibration register */
/* definitions for field:
Triggers calibration pulses
in reg: Calibration register */
/* definitions for field:
Generate calibration pulses (type 1 calibration)
in reg: Calibration register */
#define FD_CALR_CAL_PULSE WBGEN2_GEN_MASK(0, 1)
#define FD_CALR_CAL_PULSE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: PPS Calibration output enable in reg: Calibration register */
/* definitions for field: PPS Calibration output enable in reg: Calibration register */
#define FD_CALR_CAL_PPS WBGEN2_GEN_MASK(1, 1)
#define FD_CALR_CAL_PPS WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Produce DDMTD calibration pattern in reg: Calibration register */
/* definitions for field: Produce DDMTD calibration pattern
(type 2 calibration)
in reg: Calibration register */
#define FD_CALR_CAL_DMTD WBGEN2_GEN_MASK(2, 1)
#define FD_CALR_CAL_DMTD WBGEN2_GEN_MASK(2, 1)
/* definitions for field:
Enable pulse generation
in reg: Calibration register */
/* definitions for field:
Calibration pulse output select/mask
in reg: Calibration register */
#define FD_CALR_PSEL_MASK WBGEN2_GEN_MASK(3, 4)
#define FD_CALR_PSEL_MASK WBGEN2_GEN_MASK(3, 4)
#define FD_CALR_PSEL_SHIFT 3
#define FD_CALR_PSEL_SHIFT 3
#define FD_CALR_PSEL_W(value) WBGEN2_GEN_WRITE(value, 3, 4)
#define FD_CALR_PSEL_W(value) WBGEN2_GEN_WRITE(value, 3, 4)
...
@@ -171,16 +171,16 @@
...
@@ -171,16 +171,16 @@
/* definitions for register: Acam Timestamp Merging Control Register */
/* definitions for register: Acam Timestamp Merging Control Register */
/* definitions for field: Wraparound Coarse Threshold in reg: Acam Timestamp Merging Control Register */
/* definitions for field: Wraparound Coarse Threshold in reg: Acam Timestamp Merging Control Register */
#define FD_ATMCR_C_THR_MASK WBGEN2_GEN_MASK(0,
4
)
#define FD_ATMCR_C_THR_MASK WBGEN2_GEN_MASK(0,
8
)
#define FD_ATMCR_C_THR_SHIFT 0
#define FD_ATMCR_C_THR_SHIFT 0
#define FD_ATMCR_C_THR_W(value) WBGEN2_GEN_WRITE(value, 0,
4
)
#define FD_ATMCR_C_THR_W(value) WBGEN2_GEN_WRITE(value, 0,
8
)
#define FD_ATMCR_C_THR_R(reg) WBGEN2_GEN_READ(reg, 0,
4
)
#define FD_ATMCR_C_THR_R(reg) WBGEN2_GEN_READ(reg, 0,
8
)
/* definitions for field: Wraparound Fine Threshold in reg: Acam Timestamp Merging Control Register */
/* definitions for field: Wraparound Fine Threshold in reg: Acam Timestamp Merging Control Register */
#define FD_ATMCR_F_THR_MASK WBGEN2_GEN_MASK(
4
, 23)
#define FD_ATMCR_F_THR_MASK WBGEN2_GEN_MASK(
8
, 23)
#define FD_ATMCR_F_THR_SHIFT
4
#define FD_ATMCR_F_THR_SHIFT
8
#define FD_ATMCR_F_THR_W(value) WBGEN2_GEN_WRITE(value,
4
, 23)
#define FD_ATMCR_F_THR_W(value) WBGEN2_GEN_WRITE(value,
8
, 23)
#define FD_ATMCR_F_THR_R(reg) WBGEN2_GEN_READ(reg,
4
, 23)
#define FD_ATMCR_F_THR_R(reg) WBGEN2_GEN_READ(reg,
8
, 23)
/* definitions for register: Acam Start Offset Register */
/* definitions for register: Acam Start Offset Register */
...
@@ -399,9 +399,9 @@
...
@@ -399,9 +399,9 @@
#define FD_REG_TM_SECL 0x00000014
#define FD_REG_TM_SECL 0x00000014
/* [0x18]: REG Time Register - sub-second 125 MHz clock cycles */
/* [0x18]: REG Time Register - sub-second 125 MHz clock cycles */
#define FD_REG_TM_CYCLES 0x00000018
#define FD_REG_TM_CYCLES 0x00000018
/* [0x1c]: REG TDC Data Register */
/* [0x1c]: REG
Host-driven
TDC Data Register */
#define FD_REG_TDR 0x0000001c
#define FD_REG_TDR 0x0000001c
/* [0x20]: REG
TDC control/status reg
*/
/* [0x20]: REG
Host-driven TDC Control/Status
*/
#define FD_REG_TDCSR 0x00000020
#define FD_REG_TDCSR 0x00000020
/* [0x24]: REG Calibration register */
/* [0x24]: REG Calibration register */
#define FD_REG_CALR 0x00000024
#define FD_REG_CALR 0x00000024
...
...
software/include/fdelay_private.h
View file @
7141e6e3
...
@@ -31,6 +31,7 @@
...
@@ -31,6 +31,7 @@
/* ACAM TDC operation modes */
/* ACAM TDC operation modes */
#define ACAM_RMODE 0
#define ACAM_RMODE 0
#define ACAM_IMODE 1
#define ACAM_IMODE 1
#define ACAM_GMODE 2
/* MCP23S17 register addresses (only ones which are used by the lib) */
/* MCP23S17 register addresses (only ones which are used by the lib) */
#define MCP_IODIR 0x0
#define MCP_IODIR 0x0
...
...
software/lib/fdelay_lib.c
View file @
7141e6e3
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