Commit 1c5ffa8d authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

hdl/fd_channel_wb_slave: DCR.PG_ARM bit should be MONOSTABLE

parent feae54fb
...@@ -388,7 +388,7 @@ wb_dat_o[31:0] ...@@ -388,7 +388,7 @@ wb_dat_o[31:0]
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
fd_channel_dcr_pg_arm_i fd_channel_dcr_pg_trig_i
</td> </td>
<td class="td_arrow_right"> <td class="td_arrow_right">
&larr; &larr;
...@@ -405,7 +405,7 @@ wb_cyc_i ...@@ -405,7 +405,7 @@ wb_cyc_i
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
fd_channel_dcr_pg_arm_load_o fd_channel_dcr_update_o
</td> </td>
<td class="td_arrow_right"> <td class="td_arrow_right">
&rarr; &rarr;
...@@ -422,7 +422,7 @@ wb_sel_i[3:0] ...@@ -422,7 +422,7 @@ wb_sel_i[3:0]
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
fd_channel_dcr_pg_trig_i fd_channel_dcr_upd_done_i
</td> </td>
<td class="td_arrow_right"> <td class="td_arrow_right">
&larr; &larr;
...@@ -439,7 +439,7 @@ wb_stb_i ...@@ -439,7 +439,7 @@ wb_stb_i
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
fd_channel_dcr_update_o fd_channel_dcr_force_dly_o
</td> </td>
<td class="td_arrow_right"> <td class="td_arrow_right">
&rarr; &rarr;
...@@ -454,40 +454,6 @@ wb_we_i ...@@ -454,40 +454,6 @@ wb_we_i
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
</td>
<td class="td_pblock_right">
fd_channel_dcr_upd_done_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_ack_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fd_channel_dcr_force_dly_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_stall_o
</td>
<td class="td_sym_center">
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
fd_channel_dcr_no_fine_o fd_channel_dcr_no_fine_o
...@@ -498,10 +464,10 @@ fd_channel_dcr_no_fine_o ...@@ -498,10 +464,10 @@ fd_channel_dcr_no_fine_o
</tr> </tr>
<tr> <tr>
<td class="td_arrow_left"> <td class="td_arrow_left">
&larr;
</td> </td>
<td class="td_pblock_left"> <td class="td_pblock_left">
wb_ack_o
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
&nbsp; &nbsp;
...@@ -515,10 +481,10 @@ fd_channel_dcr_no_fine_o ...@@ -515,10 +481,10 @@ fd_channel_dcr_no_fine_o
</tr> </tr>
<tr> <tr>
<td class="td_arrow_left"> <td class="td_arrow_left">
&larr;
</td> </td>
<td class="td_pblock_left"> <td class="td_pblock_left">
wb_stall_o
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
...@@ -1442,7 +1408,7 @@ MODE ...@@ -1442,7 +1408,7 @@ MODE
<br>0: Channel will work as a delay generator, producing delayed copies of pulses comming to the trigger input<br>1: Channel will work as a programmable pulse generator - producing a pulse which begins at UTC time [U_START, C_START, F_START] and ends at [U_END, C_END, F_END].<br> <b>Warning:</b> MODE_DLY bit can be safely set only when the TDC and the delay logic are disabled (i.e. when GCR.BYPASS = 1) <br>0: Channel will work as a delay generator, producing delayed copies of pulses comming to the trigger input<br>1: Channel will work as a programmable pulse generator - producing a pulse which begins at UTC time [U_START, C_START, F_START] and ends at [U_END, C_END, F_END].<br> <b>Warning:</b> MODE_DLY bit can be safely set only when the TDC and the delay logic are disabled (i.e. when GCR.BYPASS = 1)
<li><b> <li><b>
PG_ARM PG_ARM
</b>[<i>read/write</i>]: Pulse generator arm </b>[<i>write-only</i>]: Pulse generator arm
<br>write 1: arms the pulse generator. <br> write 0: no effect.<br> Note that the time written to [U/C/F]START must be bigger by at least 200 ns than the value of the UTC counter at the moment of arming the pulse generator. In practice, the safety margin should be much bigger, as it's affected by the non-determinism of the operating system. <br>write 1: arms the pulse generator. <br> write 0: no effect.<br> Note that the time written to [U/C/F]START must be bigger by at least 200 ns than the value of the UTC counter at the moment of arming the pulse generator. In practice, the safety margin should be much bigger, as it's affected by the non-determinism of the operating system.
<li><b> <li><b>
PG_TRIG PG_TRIG
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : fd_channel_wbgen2_pkg.vhd -- File : fd_channel_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb -- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Sun Feb 26 22:33:04 2012 -- Created : Wed Feb 29 12:04:02 2012
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
...@@ -20,13 +20,11 @@ package fd_channel_wbgen2_pkg is ...@@ -20,13 +20,11 @@ package fd_channel_wbgen2_pkg is
-- Input registers (user design -> WB slave) -- Input registers (user design -> WB slave)
type t_fd_channel_in_registers is record type t_fd_channel_in_registers is record
dcr_pg_arm_i : std_logic;
dcr_pg_trig_i : std_logic; dcr_pg_trig_i : std_logic;
dcr_upd_done_i : std_logic; dcr_upd_done_i : std_logic;
end record; end record;
constant c_fd_channel_in_registers_init_value: t_fd_channel_in_registers := ( constant c_fd_channel_in_registers_init_value: t_fd_channel_in_registers := (
dcr_pg_arm_i => '0',
dcr_pg_trig_i => '0', dcr_pg_trig_i => '0',
dcr_upd_done_i => '0' dcr_upd_done_i => '0'
); );
...@@ -37,7 +35,6 @@ package fd_channel_wbgen2_pkg is ...@@ -37,7 +35,6 @@ package fd_channel_wbgen2_pkg is
dcr_enable_o : std_logic; dcr_enable_o : std_logic;
dcr_mode_o : std_logic; dcr_mode_o : std_logic;
dcr_pg_arm_o : std_logic; dcr_pg_arm_o : std_logic;
dcr_pg_arm_load_o : std_logic;
dcr_update_o : std_logic; dcr_update_o : std_logic;
dcr_force_dly_o : std_logic; dcr_force_dly_o : std_logic;
dcr_no_fine_o : std_logic; dcr_no_fine_o : std_logic;
...@@ -61,7 +58,6 @@ package fd_channel_wbgen2_pkg is ...@@ -61,7 +58,6 @@ package fd_channel_wbgen2_pkg is
dcr_enable_o => '0', dcr_enable_o => '0',
dcr_mode_o => '0', dcr_mode_o => '0',
dcr_pg_arm_o => '0', dcr_pg_arm_o => '0',
dcr_pg_arm_load_o => '0',
dcr_update_o => '0', dcr_update_o => '0',
dcr_force_dly_o => '0', dcr_force_dly_o => '0',
dcr_no_fine_o => '0', dcr_no_fine_o => '0',
...@@ -96,7 +92,6 @@ end function; ...@@ -96,7 +92,6 @@ end function;
function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers is function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers is
variable tmp: t_fd_channel_in_registers; variable tmp: t_fd_channel_in_registers;
begin begin
tmp.dcr_pg_arm_i := left.dcr_pg_arm_i or right.dcr_pg_arm_i;
tmp.dcr_pg_trig_i := left.dcr_pg_trig_i or right.dcr_pg_trig_i; tmp.dcr_pg_trig_i := left.dcr_pg_trig_i or right.dcr_pg_trig_i;
tmp.dcr_upd_done_i := left.dcr_upd_done_i or right.dcr_upd_done_i; tmp.dcr_upd_done_i := left.dcr_upd_done_i or right.dcr_upd_done_i;
return tmp; return tmp;
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : fd_channel_wishbone_slave.vhd -- File : fd_channel_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb -- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Sun Feb 26 22:33:04 2012 -- Created : Wed Feb 29 12:04:02 2012
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
...@@ -42,15 +42,11 @@ signal fd_channel_dcr_enable_int : std_logic ; ...@@ -42,15 +42,11 @@ signal fd_channel_dcr_enable_int : std_logic ;
signal fd_channel_dcr_enable_sync0 : std_logic ; signal fd_channel_dcr_enable_sync0 : std_logic ;
signal fd_channel_dcr_enable_sync1 : std_logic ; signal fd_channel_dcr_enable_sync1 : std_logic ;
signal fd_channel_dcr_mode_int : std_logic ; signal fd_channel_dcr_mode_int : std_logic ;
signal fd_channel_dcr_pg_arm_int_read : std_logic ; signal fd_channel_dcr_pg_arm_int : std_logic ;
signal fd_channel_dcr_pg_arm_int_write : std_logic ; signal fd_channel_dcr_pg_arm_int_delay : std_logic ;
signal fd_channel_dcr_pg_arm_lw : std_logic ; signal fd_channel_dcr_pg_arm_sync0 : std_logic ;
signal fd_channel_dcr_pg_arm_lw_delay : std_logic ; signal fd_channel_dcr_pg_arm_sync1 : std_logic ;
signal fd_channel_dcr_pg_arm_lw_read_in_progress : std_logic ; signal fd_channel_dcr_pg_arm_sync2 : std_logic ;
signal fd_channel_dcr_pg_arm_lw_s0 : std_logic ;
signal fd_channel_dcr_pg_arm_lw_s1 : std_logic ;
signal fd_channel_dcr_pg_arm_lw_s2 : std_logic ;
signal fd_channel_dcr_pg_arm_rwsel : std_logic ;
signal fd_channel_dcr_pg_trig_sync0 : std_logic ; signal fd_channel_dcr_pg_trig_sync0 : std_logic ;
signal fd_channel_dcr_pg_trig_sync1 : std_logic ; signal fd_channel_dcr_pg_trig_sync1 : std_logic ;
signal fd_channel_dcr_update_int : std_logic ; signal fd_channel_dcr_update_int : std_logic ;
...@@ -109,11 +105,8 @@ begin ...@@ -109,11 +105,8 @@ begin
rddata_reg <= "00000000000000000000000000000000"; rddata_reg <= "00000000000000000000000000000000";
fd_channel_dcr_enable_int <= '0'; fd_channel_dcr_enable_int <= '0';
fd_channel_dcr_mode_int <= '0'; fd_channel_dcr_mode_int <= '0';
fd_channel_dcr_pg_arm_lw <= '0'; fd_channel_dcr_pg_arm_int <= '0';
fd_channel_dcr_pg_arm_lw_delay <= '0'; fd_channel_dcr_pg_arm_int_delay <= '0';
fd_channel_dcr_pg_arm_lw_read_in_progress <= '0';
fd_channel_dcr_pg_arm_rwsel <= '0';
fd_channel_dcr_pg_arm_int_write <= '0';
fd_channel_dcr_update_int <= '0'; fd_channel_dcr_update_int <= '0';
fd_channel_dcr_update_int_delay <= '0'; fd_channel_dcr_update_int_delay <= '0';
fd_channel_dcr_force_dly_int <= '0'; fd_channel_dcr_force_dly_int <= '0';
...@@ -141,12 +134,8 @@ begin ...@@ -141,12 +134,8 @@ begin
if (ack_sreg(0) = '1') then if (ack_sreg(0) = '1') then
ack_in_progress <= '0'; ack_in_progress <= '0';
else else
fd_channel_dcr_pg_arm_lw <= fd_channel_dcr_pg_arm_lw_delay; fd_channel_dcr_pg_arm_int <= fd_channel_dcr_pg_arm_int_delay;
fd_channel_dcr_pg_arm_lw_delay <= '0'; fd_channel_dcr_pg_arm_int_delay <= '0';
if ((ack_sreg(1) = '1') and (fd_channel_dcr_pg_arm_lw_read_in_progress = '1')) then
rddata_reg(2) <= fd_channel_dcr_pg_arm_int_read;
fd_channel_dcr_pg_arm_lw_read_in_progress <= '0';
end if;
fd_channel_dcr_update_int <= fd_channel_dcr_update_int_delay; fd_channel_dcr_update_int <= fd_channel_dcr_update_int_delay;
fd_channel_dcr_update_int_delay <= '0'; fd_channel_dcr_update_int_delay <= '0';
fd_channel_dcr_force_dly_int <= fd_channel_dcr_force_dly_int_delay; fd_channel_dcr_force_dly_int <= fd_channel_dcr_force_dly_int_delay;
...@@ -159,11 +148,8 @@ begin ...@@ -159,11 +148,8 @@ begin
if (wb_we_i = '1') then if (wb_we_i = '1') then
fd_channel_dcr_enable_int <= wrdata_reg(0); fd_channel_dcr_enable_int <= wrdata_reg(0);
fd_channel_dcr_mode_int <= wrdata_reg(1); fd_channel_dcr_mode_int <= wrdata_reg(1);
fd_channel_dcr_pg_arm_int_write <= wrdata_reg(2); fd_channel_dcr_pg_arm_int <= wrdata_reg(2);
fd_channel_dcr_pg_arm_lw <= '1'; fd_channel_dcr_pg_arm_int_delay <= wrdata_reg(2);
fd_channel_dcr_pg_arm_lw_delay <= '1';
fd_channel_dcr_pg_arm_lw_read_in_progress <= '0';
fd_channel_dcr_pg_arm_rwsel <= '1';
fd_channel_dcr_update_int <= wrdata_reg(4); fd_channel_dcr_update_int <= wrdata_reg(4);
fd_channel_dcr_update_int_delay <= wrdata_reg(4); fd_channel_dcr_update_int_delay <= wrdata_reg(4);
fd_channel_dcr_force_dly_int <= wrdata_reg(6); fd_channel_dcr_force_dly_int <= wrdata_reg(6);
...@@ -172,13 +158,7 @@ begin ...@@ -172,13 +158,7 @@ begin
end if; end if;
rddata_reg(0) <= fd_channel_dcr_enable_int; rddata_reg(0) <= fd_channel_dcr_enable_int;
rddata_reg(1) <= fd_channel_dcr_mode_int; rddata_reg(1) <= fd_channel_dcr_mode_int;
if (wb_we_i = '0') then
rddata_reg(2) <= 'X'; rddata_reg(2) <= 'X';
fd_channel_dcr_pg_arm_lw <= '1';
fd_channel_dcr_pg_arm_lw_delay <= '1';
fd_channel_dcr_pg_arm_lw_read_in_progress <= '1';
fd_channel_dcr_pg_arm_rwsel <= '0';
end if;
rddata_reg(3) <= fd_channel_dcr_pg_trig_sync1; rddata_reg(3) <= fd_channel_dcr_pg_trig_sync1;
rddata_reg(4) <= 'X'; rddata_reg(4) <= 'X';
rddata_reg(5) <= fd_channel_dcr_upd_done_sync1; rddata_reg(5) <= fd_channel_dcr_upd_done_sync1;
...@@ -208,7 +188,7 @@ begin ...@@ -208,7 +188,7 @@ begin
rddata_reg(29) <= 'X'; rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X'; rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(5) <= '1'; ack_sreg(4) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "0001" => when "0001" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
...@@ -520,31 +500,18 @@ begin ...@@ -520,31 +500,18 @@ begin
-- Delay mode select -- Delay mode select
regs_o.dcr_mode_o <= fd_channel_dcr_mode_int; regs_o.dcr_mode_o <= fd_channel_dcr_mode_int;
-- Pulse generator arm -- Pulse generator arm
process (clk_ref_i, rst_n_i) process (clk_ref_i, rst_n_i)
begin begin
if (rst_n_i = '0') then if (rst_n_i = '0') then
if (rst_n_i = '0') then
fd_channel_dcr_pg_arm_lw_s0 <= '0';
fd_channel_dcr_pg_arm_lw_s1 <= '0';
fd_channel_dcr_pg_arm_lw_s2 <= '0';
fd_channel_dcr_pg_arm_int_read <= '0';
regs_o.dcr_pg_arm_o <= '0'; regs_o.dcr_pg_arm_o <= '0';
fd_channel_dcr_pg_arm_sync0 <= '0';
fd_channel_dcr_pg_arm_sync1 <= '0';
fd_channel_dcr_pg_arm_sync2 <= '0';
elsif rising_edge(clk_ref_i) then elsif rising_edge(clk_ref_i) then
elsif rising_edge(clk_ref_i) then fd_channel_dcr_pg_arm_sync0 <= fd_channel_dcr_pg_arm_int;
fd_channel_dcr_pg_arm_lw_s0 <= fd_channel_dcr_pg_arm_lw; fd_channel_dcr_pg_arm_sync1 <= fd_channel_dcr_pg_arm_sync0;
fd_channel_dcr_pg_arm_lw_s1 <= fd_channel_dcr_pg_arm_lw_s0; fd_channel_dcr_pg_arm_sync2 <= fd_channel_dcr_pg_arm_sync1;
fd_channel_dcr_pg_arm_lw_s2 <= fd_channel_dcr_pg_arm_lw_s1; regs_o.dcr_pg_arm_o <= fd_channel_dcr_pg_arm_sync2 and (not fd_channel_dcr_pg_arm_sync1);
if ((fd_channel_dcr_pg_arm_lw_s2 = '0') and (fd_channel_dcr_pg_arm_lw_s1 = '1')) then
if (fd_channel_dcr_pg_arm_rwsel = '1') then
regs_o.dcr_pg_arm_o <= fd_channel_dcr_pg_arm_int_write;
regs_o.dcr_pg_arm_load_o <= '1';
else
regs_o.dcr_pg_arm_load_o <= '0';
fd_channel_dcr_pg_arm_int_read <= regs_i.dcr_pg_arm_i;
end if;
else
regs_o.dcr_pg_arm_load_o <= '0';
end if; end if;
end process; end process;
......
...@@ -79,10 +79,7 @@ peripheral { ...@@ -79,10 +79,7 @@ peripheral {
description = "write 1: arms the pulse generator. \ description = "write 1: arms the pulse generator. \
write 0: no effect.\ write 0: no effect.\
Note that the time written to [U/C/F]START must be bigger by at least 200 ns than the value of the UTC counter at the moment of arming the pulse generator. In practice, the safety margin should be much bigger, as it's affected by the non-determinism of the operating system."; Note that the time written to [U/C/F]START must be bigger by at least 200 ns than the value of the UTC counter at the moment of arming the pulse generator. In practice, the safety margin should be much bigger, as it's affected by the non-determinism of the operating system.";
type = BIT; type = MONOSTABLE;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
clock = "clk_ref_i"; clock = "clk_ref_i";
}; };
......
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