Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
F
FMC DEL 1ns 4cha
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
2
Issues
2
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
FMC DEL 1ns 4cha
Commits
03ada2f9
Commit
03ada2f9
authored
Oct 27, 2011
by
Tomasz Wlostowski
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
fd_acam_timestamp_postprocessor: added extra pipeline reg on ADSFR register to improve timing
parent
e502cb54
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
19 additions
and
4 deletions
+19
-4
fd_acam_timestamp_postprocessor.vhd
hdl/rtl/fd_acam_timestamp_postprocessor.vhd
+19
-4
No files found.
hdl/rtl/fd_acam_timestamp_postprocessor.vhd
View file @
03ada2f9
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-29
-- Last update: 2011-
09-07
-- Last update: 2011-
10-20
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -105,8 +105,20 @@ architecture behavioral of fd_acam_timestamp_postprocessor is
signal
post_frac_multiplied_d0
:
signed
(
c_SCALER_SHIFT
+
g_frac_bits
+
8
downto
0
);
signal
post_frac_start_adj
:
signed
(
22
downto
0
);
signal
adsfr_d0
:
signed
(
17
downto
0
);
begin
-- behavioral
p_buffer_adsfr
:
process
(
clk_ref_i
)
begin
if
rising_edge
(
clk_ref_i
)
then
if
rst_n_i
=
'0'
then
adsfr_d0
<=
(
others
=>
'0'
);
else
adsfr_d0
<=
signed
(
regs_i
.
adsfr_o
);
end
if
;
end
if
;
end
process
;
p_postprocess_tags
:
process
(
clk_ref_i
)
...
...
@@ -147,9 +159,12 @@ begin -- behavioral
-- rescale the fractional part to our internal time base
pp_pipe
(
2
)
<=
pp_pipe
(
1
);
post_frac_multiplied
<=
resize
(
signed
(
post_frac_start_adj
)
*
signed
(
regs_i
.
adsfr_o
),
post_frac_multiplied
'length
);
--post_frac_multiplied
<= resize(signed(post_frac_start_adj) * signed(regs_i.adsfr_o), post_frac_multiplied'length);
-- post_frac_multiplied_d0 <= post_frac_multiplied;
post_frac_multiplied
<=
resize
(
signed
(
post_frac_start_adj
)
*
adsfr_d0
,
post_frac_multiplied
'length
);
-- pipeline stage 4:
-- - split the rescaled fractional part into the (mod 4096) tag_frac_o and add
-- the rest to the coarse part, along with the start-to-timescale offset
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment