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- 8 individually controllable outputs
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- Input and outputs are LVDS, all in a single LVDS connector. Level
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translation will be performed in a separate active patch panel.
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- Delay circuit reacts on input rising edge. Minimum input pulse
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width: 100 ns.
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- Output pulse width is programmable in steps of system clock ticks
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(~125 MHz) with a 16-bit register per output channel.
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