... | @@ -111,11 +111,12 @@ v2.0 release firmwares. **All offsets are referenced to PCI BAR0.** |
... | @@ -111,11 +111,12 @@ v2.0 release firmwares. **All offsets are referenced to PCI BAR0.** |
|
| \* Offset (bytes) **|** Description **|** Peripherals **|** Internal
|
|
| \* Offset (bytes) **|** Description **|** Peripherals **|** Internal
|
|
mapping **|** Status \*|
|
|
mapping **|** Status \*|
|
|
| 0x00000 | SDB descriptor | SDB descriptor base, used for automagic
|
|
| 0x00000 | SDB descriptor | SDB descriptor base, used for automagic
|
|
enumeration of the builtin cores. | | Available |
|
|
enumeration of the builtin cores. | see SDB documentation | Available
|
|
|
|
|
|
|
| 0x80000 | Fine Delay Core | FD Core for FMC 1 | see table above |
|
|
| 0x80000 | Fine Delay Core | FD Core for FMC 1 | see table above |
|
|
Available |
|
|
Available |
|
|
| 0x90000 | Vectored Interrupt Controller | Interrupt controller |
|
|
| 0x90000 | Vectored Interrupt Controller | Interrupt controller |
|
|
*xxx** | Available |
|
|
[Wiki](http://somewhere) | Available |
|
|
| 0xc0000 | White Rabbit PTP core | WR PTP core, provides distributed
|
|
| 0xc0000 | White Rabbit PTP core | WR PTP core, provides distributed
|
|
synchronization | [Wiki](http://somewhere) |
|
|
synchronization | [Wiki](http://somewhere) |
|
|
Available |
|
|
Available |
|
... | @@ -133,7 +134,7 @@ Available | |
... | @@ -133,7 +134,7 @@ Available | |
|
</tr>
|
|
</tr>
|
|
<tr class="even">
|
|
<tr class="even">
|
|
<td align="center">0</td>
|
|
<td align="center">0</td>
|
|
<td>Fine Delay Core 0 multiplexed interrupt</td>
|
|
<td>Fine Delay Core multiplexed interrupt</td>
|
|
</tr>
|
|
</tr>
|
|
</tbody>
|
|
</tbody>
|
|
</table>
|
|
</table>
|
... | @@ -163,7 +164,7 @@ A24/A32/D32 accesses ONLY.** |
... | @@ -163,7 +164,7 @@ A24/A32/D32 accesses ONLY.** |
|
<td align="center">0x00000</td>
|
|
<td align="center">0x00000</td>
|
|
<td>SDB descriptor</td>
|
|
<td>SDB descriptor</td>
|
|
<td>SDB descriptor base, used for automagic enumeration of the builtin cores.</td>
|
|
<td>SDB descriptor base, used for automagic enumeration of the builtin cores.</td>
|
|
<td></td>
|
|
<td>see SDB documentation</td>
|
|
<td>Available</td>
|
|
<td>Available</td>
|
|
</tr>
|
|
</tr>
|
|
<tr class="odd">
|
|
<tr class="odd">
|
... | @@ -184,7 +185,7 @@ A24/A32/D32 accesses ONLY.** |
... | @@ -184,7 +185,7 @@ A24/A32/D32 accesses ONLY.** |
|
<td align="center">0x30000</td>
|
|
<td align="center">0x30000</td>
|
|
<td>Vectored Interrupt Controller</td>
|
|
<td>Vectored Interrupt Controller</td>
|
|
<td>Interrupt controller</td>
|
|
<td>Interrupt controller</td>
|
|
<td><strong>xxx</strong></td>
|
|
<td>[Wiki](http://somewhere)</td>
|
|
<td>Available</td>
|
|
<td>Available</td>
|
|
</tr>
|
|
</tr>
|
|
<tr class="even">
|
|
<tr class="even">
|
... | @@ -197,3 +198,25 @@ A24/A32/D32 accesses ONLY.** |
... | @@ -197,3 +198,25 @@ A24/A32/D32 accesses ONLY.** |
|
</tbody>
|
|
</tbody>
|
|
</table>
|
|
</table>
|
|
|
|
|
|
|
|
<table>
|
|
|
|
<thead>
|
|
|
|
<tr class="header">
|
|
|
|
<th align="center">VIC Interrupt assignment</th>
|
|
|
|
</tr>
|
|
|
|
</thead>
|
|
|
|
<tbody>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">* IRQ line *</td>
|
|
|
|
<td><b> Description </b></td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">0</td>
|
|
|
|
<td>Fine Delay Core (FMC1) multiplexed interrupt</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">1</td>
|
|
|
|
<td>Fine Delay Core (FMC2) multiplexed interrupt</td>
|
|
|
|
</tr>
|
|
|
|
</tbody>
|
|
|
|
</table>
|
|
|
|
|