... | @@ -104,6 +104,40 @@ PCI BAR0.** |
... | @@ -104,6 +104,40 @@ PCI BAR0.** |
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This is the proposed mapping of the top level SPEC interconnect in the
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v2.0 release firmwares. **All offsets are referenced to PCI BAR0.**
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|\_\\5=. Wishbone Cores |
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| \* Offset (bytes) **|** Description **|** Peripherals **|** Internal
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mapping **|** Status \*|
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| 0x00000 | SDB Descriptor | SDB Descriptor of the whole card | |
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Available |
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| 0x80000 | Fine Delay Core | FD Core for FMC 1 | see table above |
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Available |
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| 0x90000 | Vectored Interrupt Controller | Interrupt controller |
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*xxx** | Available |
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| 0xc0000 | White Rabbit PTP core | WR PTP core, provides distributed
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synchronization | [Wiki](http://somewhere) |
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Available |
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<table>
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<thead>
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<tr class="header">
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<th align="center">VIC Interrupt assignment</th>
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</tr>
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</thead>
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<tbody>
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<tr class="odd">
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<td align="center">* IRQ line *</td>
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<td><b> Description </b></td>
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</tr>
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<tr class="even">
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<td align="center">0</td>
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<td>Fine Delay Core 0 multiplexed interrupt</td>
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</tr>
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</tbody>
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</table>
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### SVEC carrier bitstream
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### SVEC carrier bitstream
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This is the mapping of the top level SVEC interconnect (internal release
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This is the mapping of the top level SVEC interconnect (internal release
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