... | @@ -7,9 +7,10 @@ |
... | @@ -7,9 +7,10 @@ |
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This is the mapping of the internal FD core components with respect to
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This is the mapping of the internal FD core components with respect to
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the core's base address
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the core's base address
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|**Wishbone Cores**| | | | |
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#### Wishbone Cores
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|-------|---|---|---|---|
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|**Offset (bytes)**|**Description**|**Peripherals**|**Internal mapping**|**Status**|
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|**Offset (bytes)**|**Description**|**Peripherals**|**Internal mapping**|**Status**|
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|-------|---|---|---|---|
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|0x000|Main Registers|FD Core shared control registers (TDC and global configuration)|[wbgen2 doc](https://www.ohwr.org/project/fmc-delay-1ns-8cha/blob/master/hdl/rtl/doc/fd_main_regs.html)|Available|
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|0x000|Main Registers|FD Core shared control registers (TDC and global configuration)|[wbgen2 doc](https://www.ohwr.org/project/fmc-delay-1ns-8cha/blob/master/hdl/rtl/doc/fd_main_regs.html)|Available|
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|0x100|Channel 1 Registers|FD Core output channel 1 control registers (delay/pulse gen settings)|[wbgen2 doc](https://www.ohwr.org/project/fmc-delay-1ns-8cha/blob/master/hdl/rtl/doc/fd_channel_regs.html)|Available|
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|0x100|Channel 1 Registers|FD Core output channel 1 control registers (delay/pulse gen settings)|[wbgen2 doc](https://www.ohwr.org/project/fmc-delay-1ns-8cha/blob/master/hdl/rtl/doc/fd_channel_regs.html)|Available|
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|0x200|Channel 2 Registers|FD Core output channel 2 control registers (delay/pulse gen settings)|[wbgen2 doc](https://www.ohwr.org/project/fmc-delay-1ns-8cha/blob/master/hdl/rtl/doc/fd_channel_regs.html)|Available|
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|0x200|Channel 2 Registers|FD Core output channel 2 control registers (delay/pulse gen settings)|[wbgen2 doc](https://www.ohwr.org/project/fmc-delay-1ns-8cha/blob/master/hdl/rtl/doc/fd_channel_regs.html)|Available|
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... | @@ -25,9 +26,10 @@ release firmwares. Future releases will have all blocks starting at |
... | @@ -25,9 +26,10 @@ release firmwares. Future releases will have all blocks starting at |
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offset 0x00000 (update of Gennum core). **All offsets are referenced to
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offset 0x00000 (update of Gennum core). **All offsets are referenced to
|
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PCI BAR0.**
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PCI BAR0.**
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|**Wishbone Cores**| | | | |
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#### Wishbone Cores
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|**Offset (bytes)**|**Description**|**Peripherals**|**Internal mapping**|**Status**|
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|-------|---|---|---|---|
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|-------|---|---|---|---|
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|* Offset (bytes) *|**Description**|**Peripherals**|**Internal mapping**|**Status**|
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|0x80000|Fine Delay Core|FD Core for FMC 1|see table above|Available|
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|0x80000|Fine Delay Core|FD Core for FMC 1|see table above|Available|
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|0xc0000|White Rabbit PTP core|WR PTP core, provides distributed synchronization|[Wiki](http://somewhere)|Available|
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|0xc0000|White Rabbit PTP core|WR PTP core, provides distributed synchronization|[Wiki](http://somewhere)|Available|
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... | @@ -35,9 +37,10 @@ PCI BAR0.** |
... | @@ -35,9 +37,10 @@ PCI BAR0.** |
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This is the proposed mapping of the top level SPEC interconnect in the
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This is the proposed mapping of the top level SPEC interconnect in the
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v2.0 release firmwares. **All offsets are referenced to PCI BAR0.**
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v2.0 release firmwares. **All offsets are referenced to PCI BAR0.**
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|**Wishbone Cores**| | | | |
|
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#### Wishbone Cores
|
|
|-------|---|---|---|---|
|
|
|
|
| **Offset (bytes)**|**Description**|**Peripherals**|**Internal mapping**|**Status**|
|
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| **Offset (bytes)**|**Description**|**Peripherals**|**Internal mapping**|**Status**|
|
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|
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|-------|---|---|---|---|
|
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| 0x00000 | SDB descriptor | SDB descriptor base, used for automagic enumeration of the builtin cores. | see SDB documentation | Available|
|
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| 0x00000 | SDB descriptor | SDB descriptor base, used for automagic enumeration of the builtin cores. | see SDB documentation | Available|
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| 0x80000 | Fine Delay Core | FD Core for FMC 1 | see table above |
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| 0x80000 | Fine Delay Core | FD Core for FMC 1 | see table above |
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Available |
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Available |
|
... | @@ -47,9 +50,11 @@ Available | |
... | @@ -47,9 +50,11 @@ Available | |
|
synchronization | [Wiki](http://somewhere) |
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synchronization | [Wiki](http://somewhere) |
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Available |
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Available |
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|VIC interrupt assignment||
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|
|
|----|----|
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#### VIC interrupt assignment
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|**IRQ line**|**Description**|
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|**IRQ line**|**Description**|
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|----|----|
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|0|Fine Delay Core multiplexed interrupt|
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|0|Fine Delay Core multiplexed interrupt|
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... | @@ -60,17 +65,23 @@ for driver development purposes). **All offsets are referenced to the |
... | @@ -60,17 +65,23 @@ for driver development purposes). **All offsets are referenced to the |
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VME base address set in the VME64x core's CSR space. Card supports
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VME base address set in the VME64x core's CSR space. Card supports
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A24/A32/D32 accesses ONLY.**
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A24/A32/D32 accesses ONLY.**
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|Wishbone Cores|||||
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|
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#### Wishbone Cores
|
|
|
|
|
|
|**Offset (bytes)**|**Description**|**Peripherals**|**Internal mapping**|**Status**|
|
|
|**Offset (bytes)**|**Description**|**Peripherals**|**Internal mapping**|**Status**|
|
|
|
|
|---|---|---|---|---|
|
|
|0x00000|SDB descriptor|SDB descriptor base, used for automagic enumeration of the builtin cores.|see SDB documentation|Available|
|
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|0x00000|SDB descriptor|SDB descriptor base, used for automagic enumeration of the builtin cores.|see SDB documentation|Available|
|
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|0x10000|Fine Delay Core (FMC1)|FD Core for FMC 1|see table above|Available|
|
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|0x10000|Fine Delay Core (FMC1)|FD Core for FMC 1|see table above|Available|
|
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|0x20000|Fine Delay Core (FMC2)|FD Core for FMC 2|see table above|Available|
|
|
|0x20000|Fine Delay Core (FMC2)|FD Core for FMC 2|see table above|Available|
|
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|0x30000|Vectored Interrupt Controller|Interrupt controller|[Wiki](http://somewhere)|Available|
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|0x30000|Vectored Interrupt Controller|Interrupt controller|[Wiki](http://somewhere)|Available|
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|0x40000|White Rabbit PTP core|WR PTP core, provides distributed synchronization|[Wiki](http://somewhere)|Available|
|
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|0x40000|White Rabbit PTP core|WR PTP core, provides distributed synchronization|[Wiki](http://somewhere)|Available|
|
|
|
|
|
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|VIC interrupt assignment||
|
|
|
|
|----|----|
|
|
#### VIC interrupt assignment**
|
|
|
|
|
|
|**IRQ line**|**Description**|
|
|
|**IRQ line**|**Description**|
|
|
|
|
|----|----|
|
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|0|Fine Delay Core (FMC1) multiplexed interrupt|
|
|
|0|Fine Delay Core (FMC1) multiplexed interrupt|
|
|
|1|Fine Delay Core (FMC2) multiplexed interrupt|
|
|
|1|Fine Delay Core (FMC2) multiplexed interrupt|
|
|
|
|
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... | | ... | |