... | @@ -7,64 +7,16 @@ |
... | @@ -7,64 +7,16 @@ |
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This is the mapping of the internal FD core components with respect to
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This is the mapping of the internal FD core components with respect to
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the core's base address
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the core's base address
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<table>
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<thead>
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<tr class="header">
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|* Offset (bytes) *|**Description**|**Peripherals**|**Internal mapping**|**Status**|
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<th align="center">Wishbone Cores</th>
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|0x000|Main Registers|FD Core shared control registers (TDC and global configuration)|[wbgen2 doc](https://www.ohwr.org/project/fmc-delay-1ns-8cha/blob/master/hdl/rtl/doc/fd_main_regs.html)|Available|
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</tr>
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|0x100|Channel 1 Registers|FD Core output channel 1 control registers (delay/pulse gen settings)|[wbgen2 doc](https://www.ohwr.org/project/fmc-delay-1ns-8cha/blob/master/hdl/rtl/doc/fd_channel_regs.html)|Available|
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</thead>
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|0x200|Channel 2 Registers|FD Core output channel 2 control registers (delay/pulse gen settings)|[wbgen2 doc](https://www.ohwr.org/project/fmc-delay-1ns-8cha/blob/master/hdl/rtl/doc/fd_channel_regs.html)|Available|
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<tbody>
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|0x300|Channel 3 Registers|FD Core output channel 3 control registers (delay/pulse gen settings)|[wbgen2 doc](https://www.ohwr.org/project/fmc-delay-1ns-8cha/blob/master/hdl/rtl/doc/fd_channel_regs.html)|Available|
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<tr class="odd">
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|0x400|Channel 4 Registers|FD Core output channel 4 control registers (delay/pulse gen settings)|[wbgen2 doc](https://www.ohwr.org/project/fmc-delay-1ns-8cha/blob/master/hdl/rtl/doc/fd_channel_regs.html)|Available|
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<td align="center">* Offset (bytes) *</td>
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|0x500|FMC 1-wire master|Thermometer + unique ID (on the respective FMC)|[registers](http://opencores.org/websvn,filedetails?repname=sockit_owm&path=%2Fsockit_owm%2Ftrunk%2Fdoc%2Fsockit_owr.pdf)|Available|
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<td><b> Description </b></td>
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<td><b> Peripherals </b></td>
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<td><b> Internal mapping </b></td>
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<td><b> Status </b></td>
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</tr>
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<tr class="even">
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<td align="center">0x000</td>
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<td>Main Registers</td>
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<td>FD Core shared control registers (TDC and global configuration)</td>
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<td>[wbgen2 doc](https://www.ohwr.org/project/fmc-delay-1ns-8cha/blob/master/hdl/rtl/doc/fd_main_regs.html)</td>
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<td>Available</td>
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</tr>
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<tr class="odd">
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<td align="center">0x100</td>
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<td>Channel 1 Registers</td>
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<td>FD Core output channel 1 control registers (delay/pulse gen settings)</td>
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<td>[wbgen2 doc](https://www.ohwr.org/project/fmc-delay-1ns-8cha/blob/master/hdl/rtl/doc/fd_channel_regs.html)</td>
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<td>Available</td>
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</tr>
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<tr class="even">
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<td align="center">0x200</td>
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<td>Channel 2 Registers</td>
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<td>FD Core output channel 2 control registers (delay/pulse gen settings)</td>
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<td>[wbgen2 doc](https://www.ohwr.org/project/fmc-delay-1ns-8cha/blob/master/hdl/rtl/doc/fd_channel_regs.html)</td>
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<td>Available</td>
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</tr>
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<tr class="odd">
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<td align="center">0x300</td>
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<td>Channel 3 Registers</td>
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<td>FD Core output channel 3 control registers (delay/pulse gen settings)</td>
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<td>[wbgen2 doc](https://www.ohwr.org/project/fmc-delay-1ns-8cha/blob/master/hdl/rtl/doc/fd_channel_regs.html)</td>
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<td>Available</td>
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</tr>
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<tr class="even">
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<td align="center">0x400</td>
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<td>Channel 4 Registers</td>
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<td>FD Core output channel 4 control registers (delay/pulse gen settings)</td>
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<td>[wbgen2 doc](https://www.ohwr.org/project/fmc-delay-1ns-8cha/blob/master/hdl/rtl/doc/fd_channel_regs.html)</td>
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<td>Available</td>
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</tr>
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<tr class="odd">
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<td align="center">0x500</td>
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<td>FMC 1-wire master</td>
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<td>Thermometer + unique ID (on the respective FMC)</td>
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<td>[registers](http://opencores.org/websvn,filedetails?repname=sockit_owm&path=%2Fsockit_owm%2Ftrunk%2Fdoc%2Fsockit_owr.pdf)</td>
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<td>Available</td>
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</tr>
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</tbody>
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</table>
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### SPEC carrier bitstream
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### SPEC carrier bitstream
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... | @@ -73,36 +25,12 @@ release firmwares. Future releases will have all blocks starting at |
... | @@ -73,36 +25,12 @@ release firmwares. Future releases will have all blocks starting at |
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offset 0x00000 (update of Gennum core). **All offsets are referenced to
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offset 0x00000 (update of Gennum core). **All offsets are referenced to
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PCI BAR0.**
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PCI BAR0.**
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<table>
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<thead>
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<tr class="header">
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|* Offset (bytes) *|**Description**|**Peripherals**|**Internal mapping**|**Status**|
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<th align="center">Wishbone Cores</th>
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|0x80000|Fine Delay Core|FD Core for FMC 1|see table above|Available|
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</tr>
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|0xc0000|White Rabbit PTP core|WR PTP core, provides distributed synchronization|[Wiki](http://somewhere)|Available|
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</thead>
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<tbody>
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<tr class="odd">
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<td align="center">* Offset (bytes) *</td>
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<td><b> Description </b></td>
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<td><b> Peripherals </b></td>
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<td><b> Internal mapping </b></td>
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<td><b> Status </b></td>
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</tr>
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<tr class="even">
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<td align="center">0x80000</td>
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<td>Fine Delay Core</td>
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<td>FD Core for FMC 1</td>
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<td>see table above</td>
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<td>Available</td>
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</tr>
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<tr class="odd">
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<td align="center">0xc0000</td>
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<td>White Rabbit PTP core</td>
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<td>WR PTP core, provides distributed synchronization</td>
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<td>[Wiki](http://somewhere)</td>
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<td>Available</td>
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</tr>
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</tbody>
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</table>
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This is the proposed mapping of the top level SPEC interconnect in the
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This is the proposed mapping of the top level SPEC interconnect in the
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v2.0 release firmwares. **All offsets are referenced to PCI BAR0.**
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v2.0 release firmwares. **All offsets are referenced to PCI BAR0.**
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... | @@ -121,23 +49,11 @@ Available | |
... | @@ -121,23 +49,11 @@ Available | |
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synchronization | [Wiki](http://somewhere) |
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synchronization | [Wiki](http://somewhere) |
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Available |
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Available |
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<table>
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<thead>
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<tr class="header">
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|* IRQ line *|**Description**|
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<th align="center">VIC Interrupt assignment</th>
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|0|Fine Delay Core multiplexed interrupt|
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</tr>
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</thead>
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<tbody>
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<tr class="odd">
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<td align="center">* IRQ line *</td>
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<td><b> Description </b></td>
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</tr>
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<tr class="even">
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<td align="center">0</td>
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<td>Fine Delay Core multiplexed interrupt</td>
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</tr>
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</tbody>
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</table>
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### SVEC carrier bitstream
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### SVEC carrier bitstream
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... | @@ -146,77 +62,21 @@ for driver development purposes). **All offsets are referenced to the |
... | @@ -146,77 +62,21 @@ for driver development purposes). **All offsets are referenced to the |
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VME base address set in the VME64x core's CSR space. Card supports
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VME base address set in the VME64x core's CSR space. Card supports
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A24/A32/D32 accesses ONLY.**
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A24/A32/D32 accesses ONLY.**
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<table>
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<thead>
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<tr class="header">
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|* Offset (bytes) *|**Description**|**Peripherals**|**Internal mapping**|**Status**|
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<th align="center">Wishbone Cores</th>
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|0x00000|SDB descriptor|SDB descriptor base, used for automagic enumeration of the builtin cores.|see SDB documentation|Available|
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</tr>
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|0x10000|Fine Delay Core (FMC1)|FD Core for FMC 1|see table above|Available|
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</thead>
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|0x20000|Fine Delay Core (FMC2)|FD Core for FMC 2|see table above|Available|
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<tbody>
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|0x30000|Vectored Interrupt Controller|Interrupt controller|[Wiki](http://somewhere)|Available|
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<tr class="odd">
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|0x40000|White Rabbit PTP core|WR PTP core, provides distributed synchronization|[Wiki](http://somewhere)|Available|
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<td align="center">* Offset (bytes) *</td>
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<td><b> Description </b></td>
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<td><b> Peripherals </b></td>
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<td><b> Internal mapping </b></td>
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<td><b> Status </b></td>
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|* IRQ line *|**Description**|
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</tr>
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|0|Fine Delay Core (FMC1) multiplexed interrupt|
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<tr class="even">
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|1|Fine Delay Core (FMC2) multiplexed interrupt|
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<td align="center">0x00000</td>
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<td>SDB descriptor</td>
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<td>SDB descriptor base, used for automagic enumeration of the builtin cores.</td>
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<td>see SDB documentation</td>
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<td>Available</td>
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</tr>
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<tr class="odd">
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<td align="center">0x10000</td>
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<td>Fine Delay Core (FMC1)</td>
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<td>FD Core for FMC 1</td>
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<td>see table above</td>
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<td>Available</td>
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</tr>
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<tr class="even">
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<td align="center">0x20000</td>
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<td>Fine Delay Core (FMC2)</td>
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<td>FD Core for FMC 2</td>
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<td>see table above</td>
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<td>Available</td>
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</tr>
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<tr class="odd">
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<td align="center">0x30000</td>
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<td>Vectored Interrupt Controller</td>
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<td>Interrupt controller</td>
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<td>[Wiki](http://somewhere)</td>
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<td>Available</td>
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</tr>
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<tr class="even">
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<td align="center">0x40000</td>
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<td>White Rabbit PTP core</td>
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<td>WR PTP core, provides distributed synchronization</td>
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<td>[Wiki](http://somewhere)</td>
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<td>Available</td>
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</tr>
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</tbody>
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</table>
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<table>
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<thead>
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<tr class="header">
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<th align="center">VIC Interrupt assignment</th>
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</tr>
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</thead>
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<tbody>
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<tr class="odd">
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<td align="center">* IRQ line *</td>
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<td><b> Description </b></td>
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</tr>
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<tr class="even">
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<td align="center">0</td>
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<td>Fine Delay Core (FMC1) multiplexed interrupt</td>
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</tr>
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<tr class="odd">
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<td align="center">1</td>
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<td>Fine Delay Core (FMC2) multiplexed interrupt</td>
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</tr>
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</tbody>
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</table>
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