... | ... | @@ -23,86 +23,30 @@ rates. |
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## Specifications
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Parameter</strong></td>
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<td><strong>Value</strong></td>
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</tr>
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<tr class="even">
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<td>Channels</td>
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<td>Two independently programmable output channels sharing a clock and trigger input.</td>
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</tr>
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<tr class="odd">
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<td>Signal connectors</td>
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<td>SMA for all signals, can be replaced by LEMO 00 if required</td>
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</tr>
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<tr class="even">
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<td>FMC connector</td>
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<td>Low Pin Count (LPC), Vadj >= 2.5V</td>
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</tr>
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<tr class="odd">
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<td>Input signal level</td>
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<td><strong>Clock</strong>: 150mVpp to 2Vpp.<br />
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<strong>Trigger</strong>: 5V maximum, adjustable input threshold.</td>
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</tr>
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<tr class="even">
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<td>Output signal level</td>
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<td><strong>Clock</strong>: 800mVpp square wave.<br />
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<strong>Output</strong>: TTL, outputs capable of driving a 50 Ohm load, > 2 V/ns slew rate</td>
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</tr>
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<tr class="odd">
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<td>Operating modes</td>
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<td>TBC</td>
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</tr>
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<tr class="even">
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<td>Maximum input clock frequency</td>
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<td>1.2GHz to clock divider<br />
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~200MHz after divider (for SVEC)</td>
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</tr>
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<tr class="odd">
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<td>Minimum input clock frequency</td>
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<td>100 MHz after divider</td>
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</tr>
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<tr class="even">
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<td>Clock divider ratio</td>
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<td>1..32</td>
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</tr>
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<tr class="odd">
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<td>Minimum input pulse width</td>
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<td>Depends on input clock frequency (1x clock period)</td>
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</tr>
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<tr class="even">
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<td>Maximum input pulse rate</td>
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<td>Depends on input clock frequency (1x clock period)</td>
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</tr>
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<tr class="odd">
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<td>Output pulse width</td>
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<td>2ns (min) to maintain 2.5Vpkpk output level</td>
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</tr>
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<tr class="even">
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<td>Output pulse spacing</td>
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<td>Depends on input clock frequency (1x clock period)</td>
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</tr>
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<tr class="odd">
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<td>Trigger to output delay</td>
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<td>TBC</td>
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</tr>
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<tr class="even">
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<td>Timebase accuracy</td>
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<td>±10ppm with onboard VCXO</td>
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</tr>
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<tr class="odd">
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<td>Delay accuracy</td>
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<td>TBC</td>
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</tr>
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<tr class="even">
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<td>Power consumption</td>
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<td><strong>P3V3</strong>: 1.5 A<br />
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<strong>P12V</strong>: 50 mA</td>
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</tr>
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</tbody>
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</table>
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|**Parameter**|**Value**|
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|----|----|
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|Channels|Two independently programmable output channels sharing a clock and trigger input.|
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|Signal connectors|SMA for all signals, can be replaced by LEMO 00 if required|
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|FMC connector|Low Pin Count (LPC), Vadj >= 2.5V|
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|Input signal level|**Clock**: 150mVpp to 2Vpp.
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**Trigger**: 5V maximum, adjustable input threshold.|
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|Output signal level|**Clock**: 800mVpp square wave.
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**Output**: TTL, outputs capable of driving a 50 Ohm load, > 2 V/ns slew rate|
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|Operating modes|TBC|
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|Maximum input clock frequency|1.2GHz to clock divider
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~200MHz after divider (for SVEC)|
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|Minimum input clock frequency|100 MHz after divider|
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|Clock divider ratio|1..32|
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|Minimum input pulse width|Depends on input clock frequency (1x clock period)|
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|Maximum input pulse rate|Depends on input clock frequency (1x clock period)|
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|Output pulse width|2ns (min) to maintain 2.5Vpkpk output level|
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|Output pulse spacing|Depends on input clock frequency (1x clock period)|
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|Trigger to output delay|TBC|
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|Timebase accuracy|±10ppm with onboard VCXO|
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|Delay accuracy|TBC|
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|Power consumption|**P3V3**: 1.5 A
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**P12V**: 50 mA|
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-----
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... | ... | @@ -129,69 +73,26 @@ rates. |
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## Project Status
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Date</strong></td>
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<td><b> Event </b></td>
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</tr>
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<tr class="even">
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<td>04-01-2016</td>
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<td>Work on schematics started.</td>
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</tr>
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<tr class="odd">
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<td>27-01-2016</td>
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<td>First version of schematics ready for review.</td>
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</tr>
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<tr class="even">
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<td>05-02-2016</td>
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<td>Layout started by CERN design office.</td>
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</tr>
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<tr class="odd">
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<td>08-02-2016</td>
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<td>Inclusion of project on OHWR.</td>
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</tr>
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<tr class="even">
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<td>15-03-2016</td>
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<td>Layout completed.</td>
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</tr>
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<tr class="odd">
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<td>27-05-2016</td>
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<td>First two prototype boards received.</td>
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</tr>
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<tr class="even">
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<td>10-08-2016</td>
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<td>First prototype boards under test.</td>
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</tr>
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<tr class="odd">
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<td>12-08-2016</td>
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<td>Some small <a href="https://www.ohwr.org/project/fmc-del-1ns-2cha/versions/135">issues</a> found but the board is functional.</td>
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</tr>
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<tr class="even">
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<td>03-11-2016</td>
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<td>First two prototype boards deployed (on a SVEC) in LHC for control of Schottky Monitor fast gates.</td>
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</tr>
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<tr class="odd">
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<td>19-01-2017</td>
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<td>Module presented at the BI Technical Board ([slides](https://indico.cern.ch/event/587494/contributions/2367714/1394441)).</td>
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</tr>
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<tr class="even">
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<td>01-05-2017</td>
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<td>Decision to change from surface mount SMA connectors to through hole due to reliability issues.<br />
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<a href="http://www.amphenolrf.com/901-10138.html">Amphenol 901-10138</a> selected as a replacement.</td>
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</tr>
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<tr class="odd">
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<td>22-05-2017</td>
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<td>Version 3 design changes finished.</td>
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</tr>
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<tr class="even">
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<td>14-09-2017</td>
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<td>12 assembled PCBs received and tested.</td>
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</tr>
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</tbody>
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</table>
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|**Date**|**Event**|
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|----|----|
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|
|04-01-2016|Work on schematics started.|
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|
|
|27-01-2016|First version of schematics ready for review.|
|
|
|
|05-02-2016|Layout started by CERN design office.|
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|08-02-2016|Inclusion of project on OHWR.|
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|
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|15-03-2016|Layout completed.|
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|27-05-2016|First two prototype boards received.|
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|10-08-2016|First prototype boards under test.|
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|12-08-2016|Some small [issues](https://www.ohwr.org/project/fmc-del-1ns-2cha/versions/135) found but the board is functional.|
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|03-11-2016|First two prototype boards deployed (on a SVEC) in LHC for control of Schottky Monitor fast gates.|
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|19-01-2017|Module presented at the BI Technical Board ([slides](https://indico.cern.ch/event/587494/contributions/2367714/1394441)).|
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|01-05-2017|Decision to change from surface mount SMA connectors to through hole due to reliability issues.
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[Amphenol 901-10138](http://www.amphenolrf.com/901-10138.html) selected as a replacement.|
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|22-05-2017|Version 3 design changes finished.|
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|14-09-2017|12 assembled PCBs received and tested.|
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-----
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Michael Betz, Tom Levens - 09 February 2016
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