... | ... | @@ -107,7 +107,7 @@ Accuracy is as good as the time base, e.g. for a delay of 1 s using internal tim |
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## Detailed project information
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- **Official production documentation (schematics, PCB, etc.):**
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[EDMS: EDA-02267](http://edms.cern.ch/nav/EDA-02267)
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[EDMS: EDA-03339](http://edms.cern.ch/nav/EDA-03339)
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- [Users](Users)
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- [Software](Software)
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- [CERN specific information](CERN)
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... | ... | @@ -120,30 +120,15 @@ Accuracy is as good as the time base, e.g. for a delay of 1 s using internal tim |
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-----
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## Releases
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- Hardware: FMC Delay 1ns 4cha -
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[EDA-02267-V6-1](https://edms.cern.ch/nav/EDA-02267-V6-1)
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- Gateware: [Releases](releases) page.
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- Linux driver: see [Software support for FMC
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Delay 1ns 4cha](https://www.ohwr.org/project/fine-delay-sw/wiki)
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(Project)
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-----
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## Contacts
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### Commercial producers
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- [Fine
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Delay](http://www.incaacomputers.com/component/resource/article/products/by-function/17-timing-gen/169-fine-delay)
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- [INCAA Computers](http://incaacomputers.nl), Netherlands
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- [Fine Delay](http://www.sevensols.com/en/products/fmc-del.html) -
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[Seven Solutions](http://www.sevensols.com/index.php), Spain
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- The card is not yet commercially produced.
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### General question about project
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- [Erik van der Bij](mailto:Erik.van.der.Bij@cern.ch) - CERN
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- [Michael Betz](mailto:mbetz@cern.ch) - CERN
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-----
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... | ... | @@ -156,237 +141,25 @@ Accuracy is as good as the time base, e.g. for a delay of 1 s using internal tim |
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<td><b> Event </b></td>
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</tr>
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<tr class="even">
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<td>22-04-2010</td>
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<td>Start working on project.</td>
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</tr>
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<tr class="odd">
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<td>30-04-2010</td>
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<td>First meeting with N. Voumard to fine-tune functional specs.</td>
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</tr>
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<tr class="even">
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<td>20-05-2010</td>
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<td>Second functional specs meeting with the ABT team.</td>
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</tr>
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<tr class="odd">
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<td>11-06-2010</td>
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<td>Order <a href="https://edh.cern.ch/Document/SupplyChain/DAI/4384595">4384595</a> made for design of the module.</td>
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</tr>
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<tr class="even">
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<td>15-06-2010</td>
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<td>Final functional specification review meeting held. Resulted in minor modifications.</td>
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</tr>
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<tr class="odd">
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<td>30-06-2010</td>
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<td><a href="https://www.ohwr.org/project/fmc-delay-1ns-8cha/uploads/364be2448542f8ef28b8da276df0436c/FMC_delay_1ns_4_CH_spec.pdf">Technical specification draft</a> finished.</td>
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</tr>
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<tr class="even">
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<td>17-08-2010</td>
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<td>First schematics review held. [ReviewFineDelayFMC17082010](ReviewFineDelayFMC17082010)</td>
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</tr>
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<tr class="odd">
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<td>03-09-2010</td>
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<td>Schematics revised. Waiting for a new design review.</td>
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</tr>
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<tr class="even">
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|
<td>10-11-2010</td>
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<td>Second schematics review held. [ReviewFineDelayFMC10112010](ReviewFineDelayFMC10112010)</td>
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</tr>
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<tr class="odd">
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<td>12-11-2010</td>
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<td>Comments on review received. Re-commented on it. [FMC10112010_improvements v5](https://www.ohwr.org/project/fmc-delay-1ns-8cha/wikis/ReviewFineDelayFMC10112010_improvements?version=5)</td>
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</tr>
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<tr class="even">
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<td>25-11-2010</td>
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<td>Updated schematics and comments received. [ReviewFineDelayFMC10112010-improvements](ReviewFineDelayFMC10112010-improvements)</td>
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</tr>
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<tr class="odd">
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<td>25-11-2010</td>
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<td>Comments on updated schematics. [ReviewFineDelayFMC25112010](ReviewFineDelayFMC25112010)</td>
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</tr>
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<tr class="even">
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<td>30-11-2010</td>
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|
<td>Updated schematics and comments received. [ReviewFineDelayFMC25112010-improvements](ReviewFineDelayFMC25112010-improvements)</td>
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</tr>
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<tr class="odd">
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<td>13-12-2010</td>
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<td>First version of PCB layout expected by 17 December.</td>
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</tr>
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<tr class="even">
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<td>14-01-2011</td>
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<td>Spec change for minimum delay: 500 ns. PCB layout almost finished, waiting for some symbols.</td>
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</tr>
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<tr class="odd">
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<td>18-01-2011</td>
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<td>PCB layout received. Review on 19-01-2011.</td>
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</tr>
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<tr class="even">
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<td>18-01-2011</td>
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<td>Changelog for the PCB/schematics published: [Changelog-19012010](Changelog-19012010)</td>
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</tr>
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<tr class="odd">
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<td>20-01-2011</td>
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<td>PCB review held. V1 layout ready (SVN revision: 18) [Changelog-20012011](Changelog-20012011)</td>
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</tr>
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<tr class="even">
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<td>28-01-2011</td>
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<td>Empty PCB should arrive on 1 February. Requested design office to review files.</td>
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</tr>
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<tr class="odd">
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<td>03-02-2011</td>
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<td>Prototype PCB assembled and ready for HDL development. ID EEPROM works.</td>
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</tr>
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<tr class="even">
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<td>14-02-2011</td>
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<td>Design being reviewed by CERN's design office.</td>
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</tr>
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<tr class="odd">
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<td>21-02-2011</td>
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<td>HDL development on-going.</td>
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</tr>
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<tr class="even">
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<td>02-03-2011</td>
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<td>Returned corrections in schematics to design office.</td>
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</tr>
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<tr class="odd">
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<td>18-03-2011</td>
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<td>Design checked and available in [EDMS](http://edms.cern.ch/nav/EDA-02267-V1-0).</td>
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</tr>
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<tr class="even">
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<td>19-04-2011</td>
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<td>Rather high jitter in prototype. Will improve layout of supply to ACCAM chip.</td>
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</tr>
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<tr class="odd">
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<td>05-05-2011</td>
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<td>V2 schematics and layout available for review: [Changelog-05052011](Changelog-05052011)</td>
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</tr>
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<tr class="even">
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|
<td>06-05-2011</td>
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|
<td>V2 review held. Reduce number of R values, no large ceramic C, 20 MHz osc instead of 25 MHz.</td>
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</tr>
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<tr class="odd">
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<td>08-06-2011</td>
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<td>Files sent to CERN's design office for review and front-panel design.</td>
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</tr>
|
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<tr class="even">
|
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|
<td>14-07-2011</td>
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<td>V2 design ready. Will produce 4 prototypes, after correcting OHL licence and removal of CERN logo.</td>
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</tr>
|
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|
<tr class="odd">
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|
<td>16-08-2011</td>
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|
<td>PCB ready by 19-08-2011. Assembly can start.</td>
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</tr>
|
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|
<tr class="even">
|
|
|
<td>31-08-2011</td>
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|
<td>Received assembled prototype of V2.</td>
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</tr>
|
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<tr class="odd">
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<td>02-09-2011</td>
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<td>V2 works.</td>
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</tr>
|
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<tr class="even">
|
|
|
<td>16-11-2011</td>
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|
<td>V2 demoed on SPEC. Considering changing output driver to have less cross-talk.</td>
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</tr>
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<tr class="odd">
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<td>09-01-2012</td>
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<td>V3 proto with changed output driver being tested. Preparing price enquiry.</td>
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</tr>
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<tr class="even">
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|
<td>26-01-2012</td>
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<td>Price enquiry sent out. Deadline 24 February. 40 cards expected by 24 August.</td>
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</tr>
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<tr class="odd">
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<td>03-02-2012</td>
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<td>In parallel assemble 10 boards for urgent project.</td>
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</tr>
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<tr class="even">
|
|
|
<td>24-02-2012</td>
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|
<td>One card sent for writing Linux driver. Firmware available, but needs finalisation.</td>
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|
<td>04-01-2016</td>
|
|
|
<td>Work on schematics started.</td>
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|
</tr>
|
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|
<tr class="odd">
|
|
|
<td>01-03-2012</td>
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|
|
<td>Third schematics and PCB review held. [ReviewFineDelayFMC02032012](ReviewFineDelayFMC02032012)</td>
|
|
|
<td>27-01-2016</td>
|
|
|
<td>First version of schematics ready for review.</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>07-03-2012</td>
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|
|
<td>Order placed with INCAA for 40 cards (V4-0). Delivery: preseries (10) end June; series (30) end August.</td>
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|
<td>05-02-2016</td>
|
|
|
<td>Layout started by CERN design office.</td>
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|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>15-03-2012</td>
|
|
|
<td>INCAA reviewed the design. Modifications will be made. [ReviewFineDelayFMC15032012](ReviewFineDelayFMC15032012)</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>28-03-2012</td>
|
|
|
<td>New version 4-0 given to design office for verification.</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>29-03-2012</td>
|
|
|
<td>Received 15 V3 boards for use in CNGS and prototyping purposes.</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>04-06-2012</td>
|
|
|
<td>During running in CNGS found two issues that need change of components (<a href="https://www.ohwr.org/project/fmc-delay-1ns-8cha/issues/19">515</a>, [516](https://www.ohwr.org/project/fmc-delay-1ns-8cha/issues/18))</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>17-08-2012</td>
|
|
|
<td>Received 10 pre-series cards from order to INCAA.</td>
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|
</tr>
|
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|
<tr class="even">
|
|
|
<td>10-09-2012</td>
|
|
|
<td>CERN entered the modules in the stock for later use in LHC and other accelerators.</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>27-09-2012</td>
|
|
|
<td>Order placed with INCAA for additional 30 cards (V4-0).</td>
|
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|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>15-01-2013</td>
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|
|
<td>30+30 cards received at CERN (in addition to the 10 pre-series cards).</td>
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|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>06-02-2013</td>
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|
|
<td>Change of spec: Maximum input pulse rate lowered to 1 MHz and minimum pulse spacing increased to 1 us.</td>
|
|
|
</tr>
|
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|
<tr class="even">
|
|
|
<td>18-06-2013</td>
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|
|
<td>V5-1 of design published. Improves jitter (<a href="https://www.ohwr.org/project/fmc-delay-1ns-8cha/issues/14)">740</a>. Issue <a href="https://www.ohwr.org/project/fmc-delay-1ns-8cha/issues/16">608</a> not handled.</td>
|
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</tr>
|
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|
<tr class="odd">
|
|
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<td>20-06-2013</td>
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|
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<td>Spec change for minimum delay: 600 ns (was 500 ns).</td>
|
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|
</tr>
|
|
|
<tr class="even">
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|
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<td>03-09-2013</td>
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|
|
<td>Ordered 10 additional cards for CERN EN/ICE.</td>
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</tr>
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<tr class="odd">
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<td>27-09-2013</td>
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<td>A third company is producing and supporting the card.</td>
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</tr>
|
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<tr class="even">
|
|
|
<td>27-05-2014</td>
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|
|
<td>V6-0 of design published, contains manufacturability improvements (issue [770](https://www.ohwr.org/project/fmc-delay-1ns-8cha/issues/10)).</td>
|
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|
</tr>
|
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|
<tr class="odd">
|
|
|
<td>13-06-2014</td>
|
|
|
<td>Order placed for 80 cards (V6-0): 30 by 26/9/14, 50 by 28/11/14.</td>
|
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|
</tr>
|
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|
<tr class="even">
|
|
|
<td>27-10-2014</td>
|
|
|
<td>V6-1 design required (for new productions only) to solve [issue](https://www.ohwr.org/project/fmc-delay-1ns-8cha/issues/4).</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>18-12-2014</td>
|
|
|
<td>Gateware v.2.1 released.</td>
|
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|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>19-01-2015</td>
|
|
|
<td><a href="https://edms.cern.ch/nav/EDA-02267-V6-1">V6-1</a> hardware design released.</td>
|
|
|
<td>08-02-2016</td>
|
|
|
<td>Inclusion of project on OHWR.</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
|
|
|
-----
|
|
|
|
|
|
Tomasz Wlostowski, Erik van der Bij - 20 January 2015
|
|
|
Michael Betz, Tom Levens - 08 February 2016
|
|
|
|