The fmc-adc-subsamp125m14b4cha is a 4 channel 125MSPS 14 bit ADC low pin
count FPGA Mezzanine Card (VITA 57). It was designed within the
framework of the WR-D3S-ADC project to bandpass
sampling signals with a
carrier frequency higher than 125 MHz, but BW of only a few MHz. The
design was based on the
but two main changes were applied:
- the ADC LTC2174 was replaced with the pin compatible LTC2175 in order
to increase the sampling frequency to 125MHz and synchronize it using
the WR clock.
- the input acquisition circuitry of every adc channel was
simplified and replaced by RF transformers as recommended into the ADC
max. sample rate
3 MHz. AC-coupled
4 x LEMO 00 for signals, 1 x LEMO 00 for trigger
FMC to carrier interface
FMC high pin count connector (HPC only used if external clock is selected)
Internal: from programmable on-board oscillator.
External: from dedicated FMC connector pins (HPC) when changing two capacitors.