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# Project description
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fmc-adc-subsamp125m14b4cha is a 4 channel 125MSPS 14 bit ADC low pin
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count FPGA Mezzanine Card (VITA 57). It is designed for undersampling
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(also called bandpass sampling) signals with a carrier frequency higher
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than 125 MHz. The design is based on the
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[fmc-adc-100m14b4cha](https://www.ohwr.org/project/fmc-adc-100m14b4cha/wiki).
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## UNDER CONSTRUCTION...
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*TEMPLATE - NEEDS UPDATING**
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# Project description
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The FmcAdc100M14b4cha is a 4 channel 100MSPS 14 bit ADC card in FMC
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(FPGA Mezzanine Card) format. By default it uses only signals from the
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LPC rows of the HPC connector that is mounted. The gain can be set by
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software in three steps: */-50mV,*/-0.5V, */-5V. An advanced offset
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circuit is used in the front-end design of the ADC board, and allows a
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voltage shift in the range of*/- 5V that is independent on the chosen
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gain range.
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The fmc-adc-subsamp125m14b4cha is a 4 channel 125MSPS 14 bit ADC low pin
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count FPGA Mezzanine Card (VITA 57). It was designed within the
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framework of the WR-D3S-ADC project to "bandpass
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sampling"https://en.wikipedia.org/wikis/Undersampling signals with a
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carrier frequency higher than 125 MHz, but BW of only a few MHz. The
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design was based on the
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[fmc-adc-100m14b4cha](https://www.ohwr.org/project/fmc-adc-100m14b4cha/wiki),
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but 2 main changes were applied:
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\- the ADC LTC2174 was replaced with the pin compatible LTC2175 in order
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to increase the sampling frequency to 125MHz and synchronize it using
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the WR clock.
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\- and the input acquisition circuitry of every adc chanel was
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simplified and replaced by RF transformers as recommended into the ADC
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datasheet.
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Please refer to the corresponding sub-project for detailed
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information.
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... | ... | @@ -32,55 +34,33 @@ information. |
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</tr>
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<tr class="even">
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<td>max. sample rate</td>
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<td>105 MSPS (default 100MSPS)</td>
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<td>125 MSPS</td>
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</tr>
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<tr class="odd">
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<td>analog bandwidth</td>
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<td>30 MHz. DC-coupled (40 MHz possible by changing eight capacitors)</td>
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<td>3 MHz. AC-coupled</td>
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</tr>
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<tr class="even">
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<td>bits/sample</td>
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<td>14 bit</td>
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</tr>
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<tr class="odd">
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<td>ENOB</td>
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<td>11, 11.5, 11.7 bit (@ <em>/-50mV,</em>/-0.5V, +/-5V range)</td>
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</tr>
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<tr class="even">
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<td>channels</td>
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<td>4</td>
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</tr>
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<tr class="odd">
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<tr class="even">
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<td>connectors</td>
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<td>4 x LEMO 00 for signals, 1 x LEMO 00 for trigger</td>
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</tr>
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<tr class="even">
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<td>input impedance</td>
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<td>1 kOhm / 50 Ohm - software selectable</td>
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</tr>
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<tr class="odd">
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<td>gain steps</td>
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<td>+/-50 mV<br />
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+/-0.5 V<br />
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+/-5 V</td>
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</tr>
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<tr class="even">
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<td>offset correction range</td>
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<td>+/- 5 V for every input voltage range</td>
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</tr>
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<tr class="odd">
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<td>max. gain error</td>
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<td>+/- 1 %</td>
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<td>input impedance</td>
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<td>50 Ohm</td>
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</tr>
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<tr class="even">
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<td>SNR</td>
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<td>67.7 dB, 70.8 dB, 72.2 dB (@ <em>/-50mV,</em>/-0.5V, +/-5V range)</td>
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</tr>
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<tr class="odd">
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<td>FMC to carrier interface</td>
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<td>FMC high pin count connector (HPC only used if external clock is selected)</td>
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</tr>
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<tr class="even">
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<tr class="odd">
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<td>Clock source</td>
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<td>Internal: from programmable on-board oscillator.<br />
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External: from dedicated FMC connector pins (HPC) when changing two capacitors.</td>
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... | ... | @@ -93,21 +73,8 @@ External: from dedicated FMC connector pins (HPC) when changing two capacitors.< |
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## Releases
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- Hardware: see EDMS (CERN Electronic Document Management System)
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document [EDA-02063.](https://edms.cern.ch/nav/EDA-02063)
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- Gateware: see [gateware sub-project releases
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page.](https://www.ohwr.org/project/fmc-adc-100m14b4cha-gw/wikis/Releases)
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- Software: see [software sub-project releases
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page.](https://www.ohwr.org/project/fmc-adc-100m14b4cha-sw/wikis/Releases)
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-----
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## Project Information
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- [Users](Users)
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- [Frequently Asked Questions](FAQ)
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- [Mailing list
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fmc-adc-100m14b4cha@ohwr.org](https://www.ohwr.org/mailing_list/show?project_id=fmc-adc-100m14b4cha)
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and its archive.
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document [EDA-03502-V1-0
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v.0.](https://edms.cern.ch/item/EDA-03502-V1-0/0)
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-----
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... | ... | @@ -137,10 +104,14 @@ External: from dedicated FMC connector pins (HPC) when changing two capacitors.< |
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<td>15-11-2016</td>
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<td>Manufacturing of 3 assembled boards finished</td>
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</tr>
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<tr class="even">
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<td>21-11-2016</td>
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<td>Initial test of the 3 assembled boards finished</td>
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</tr>
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</tbody>
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</table>
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-----
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Eva Calvo - 19 October 2016
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Eva Calvo - 12 December 2016
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