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The fmc-adc-subsamp125m14b4cha is a 4 channel 125MSPS 14 bit ADC low pin
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The fmc-adc-subsamp125m14b4cha is a 4 channel 125MSPS 14 bit ADC low pin
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count FPGA Mezzanine Card (VITA 57). It was designed within the
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count FPGA Mezzanine Card (VITA 57). It was designed within the
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framework of the WR-D3S-ADC project to [bandpass
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framework of the WR-D3S-ADC project to [bandpass
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sampling](https://en.wikipedia.org/wikis/Undersampling) signals with a
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sampling](https://en.wikipedia.org/wiki/Undersampling) signals with a
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carrier frequency higher than 125 MHz, but BW of only a few MHz. The
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carrier frequency higher than 125 MHz, but BW of only a few MHz. The
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design was based on the
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design was based on the
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[fmc-adc-100m14b4cha](https://www.ohwr.org/project/fmc-adc-100m14b4cha/wiki),
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[fmc-adc-100m14b4cha](https://www.ohwr.org/project/fmc-adc-100m14b4cha/wiki),
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but 2 main changes were applied:
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but two main changes were applied:
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\- the ADC LTC2174 was replaced with the pin compatible LTC2175 in order
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\- the ADC LTC2174 was replaced with the pin compatible LTC2175 in order
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to increase the sampling frequency to 125MHz and synchronize it using
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to increase the sampling frequency to 125MHz and synchronize it using
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the WR clock.
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the WR clock.
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\- and the input acquisition circuitry of every adc channel was
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\- the input acquisition circuitry of every adc channel was
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simplified and replaced by RF transformers as recommended into the ADC
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simplified and replaced by RF transformers as recommended into the ADC
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datasheet.
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datasheet.
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