... | @@ -4,8 +4,8 @@ |
... | @@ -4,8 +4,8 @@ |
|
|
|
|
|
The fmc-adc-subsamp125m14b4cha is a 4 channel 125MSPS 14 bit ADC low pin
|
|
The fmc-adc-subsamp125m14b4cha is a 4 channel 125MSPS 14 bit ADC low pin
|
|
count FPGA Mezzanine Card (VITA 57). It was designed within the
|
|
count FPGA Mezzanine Card (VITA 57). It was designed within the
|
|
framework of the WR-D3S-ADC project to "bandpass
|
|
framework of the WR-D3S-ADC project to [bandpass
|
|
sampling"https://en.wikipedia.org/wikis/Undersampling signals with a
|
|
sampling](https://en.wikipedia.org/wikis/Undersampling) signals with a
|
|
carrier frequency higher than 125 MHz, but BW of only a few MHz. The
|
|
carrier frequency higher than 125 MHz, but BW of only a few MHz. The
|
|
design was based on the
|
|
design was based on the
|
|
[fmc-adc-100m14b4cha](https://www.ohwr.org/project/fmc-adc-100m14b4cha/wiki),
|
|
[fmc-adc-100m14b4cha](https://www.ohwr.org/project/fmc-adc-100m14b4cha/wiki),
|
... | @@ -18,9 +18,6 @@ the WR clock. |
... | @@ -18,9 +18,6 @@ the WR clock. |
|
simplified and replaced by RF transformers as recommended into the ADC
|
|
simplified and replaced by RF transformers as recommended into the ADC
|
|
datasheet.
|
|
datasheet.
|
|
|
|
|
|
Please refer to the corresponding sub-project for detailed
|
|
|
|
information.
|
|
|
|
|
|
|
|
[![](/project/fmc-adc-100m14b4cha/uploads/d48f899d27512044661f3f60d68afbf7/fmc-adc_v3_front_small.jpg)](/project/fmc-adc-100m14b4cha/uploads/669878f74ff69e386880d0d4394af9bd/fmc-adc_v3_front.jpg)
|
|
[![](/project/fmc-adc-100m14b4cha/uploads/d48f899d27512044661f3f60d68afbf7/fmc-adc_v3_front_small.jpg)](/project/fmc-adc-100m14b4cha/uploads/669878f74ff69e386880d0d4394af9bd/fmc-adc_v3_front.jpg)
|
|
/4760
|
|
/4760
|
|
|
|
|
... | | ... | |