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# FMC ADC 500M 14b 4cha
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## Project description
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The FmcAdc500M14b4cha is a 4-channel 500 MSPS 14 bit ADC card in FMC (FPGA
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Mezzanine Card, VITA 57.1) format using a High Pin-Count (HPC) connector.
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**Below is only a template.
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Please update using the [recommended setup and usage guide](https://www.ohwr.org/project/ohr-support/wikis/Administrator-guide#recommended-setup-usage)**
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**SPEC 1.1 first prototype**
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## Preliminary Specifications
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|**Parameter**|**Value**|
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|----|----|
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|PCB format|VITA 57.1 FMC LPC|
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|Connectors|SMA|
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|Sampling Rate|1 GSPS (preferably 2GSPS)|
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|Input Signal Type|single-ended|
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|Resolution|8 bits|
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|Number of Channels|2 (preferably 4)|
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|Bandwidth (-3dB)|50Ω: DC to 400MHz (or better) <br/> 1MΩ: DC to 300MHz (or better)|
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|Input Signal Coupling and Termination|AC (8 Hz LF limit, after 50 Ω termination) <br/> DC-50Ω <br/>DC-1MΩ|
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|Input Signal Range|+/- 50mV<br/>+/- 250mV<br/>+/- 500mV<br/>+/- 2.5V<br/>+/- 5V|
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|Max Input Signal Amplitude|+/- 10V|
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|SNR|> 40dB full bandwidth over all input ranges|
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|ENOB|> 6.5 full bandwidth over all input ranges|
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|Offset Adjustment Range|+/- 5V|
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|Offset Adjustment Resolution|16 bits|
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|Offset Adjustment Accuracy|< 1%|
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|Additional I/O|External TTL trigger in/out (bidirectional)<br/>External 10MHz clock input|
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|Self-calibration|Automatic zeroing of offset and gain|
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|ADC interface|serial/parallel LVDS|
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|Temperature sensor|via one-wire ds182x|
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|FMC EEPROM|24C02, as per VITA 57.1|
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|Power Consumption| specified as < 7W (design estimation 9.6W) |
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**Notes:**
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- The following features should be controllable by software:
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- Input signal range, coupling, termination and offset adjustment
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- Self-calibration
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- Sampling clock selection
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- Direction of external trigger in/out
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- ADC configuration and status
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- The offset adjustment must not clip the signal at the highest range
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(+/- 5V). That is why the "max input signal amplitude" has been
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specified as 10V, even though the selection of signal ranges only
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goes up to 5V. This way, a +10V pulse with -5V offset could still be
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digitised without clipping.
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- The sampling clock should be derived from a voltage-controllable
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125MHz clock source, controlled via an SPI DAC.
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- A copy of the 125MHz clock source should be available on the FMC
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connector pins.
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## Project information
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- [Available documentation](Documents)
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- [Design reviews](Design reviews)
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## Contacts
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### Commercial producers
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- FMC ADC 500M14b4cha - [IAM Electronic](http://iamelectronic.com), Germany
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### General questions about project
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- [Philipp Födisch](mailto:philipp.foedisch@iamelectronic.com) - I AM Electronic
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## Status
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| **Date** | **Event** |
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| :------: | :-------- |
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| 12-07-2019 | Start of project. |
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| 19-02-2020 | Revision C of project ready |
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| 12-01-2021 | CERN has received 60 cards for use in beam instrumentation systems |
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| 01-04-2021 | Decision to licence the project under CERN OHL |
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---
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1 April 2021 |
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\ No newline at end of file |
