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Update home: specification table authored by Philipp Foedisch's avatar Philipp Foedisch
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## Project description ## Project description
The FmcAdc500M14b4cha is a 4-channel 500 MSPS 14 bit ADC card in FMC (FPGA Mezzanine Card, VITA 57.1) format using a High Pin-Count (HPC) connector. The module has 4 DC-coupled input channels with 50 Ohm input impedance. The FmcAdc500M14b4cha is a 4-channel 500 MSPS 14 bit ADC card in FMC (FPGA Mezzanine Card, VITA 57.1) format using a High Pin-Count (HPC) connector. The module has 4 DC-coupled input channels with 50 Ω input impedance.
**Below is only a template. **Below is only a template.
Please update using the [recommended setup and usage guide](https://www.ohwr.org/project/ohr-support/wikis/Administrator-guide#recommended-setup-usage)** Please update using the [recommended setup and usage guide](https://www.ohwr.org/project/ohr-support/wikis/Administrator-guide#recommended-setup-usage)**
...@@ -10,31 +10,28 @@ Please update using the [recommended setup and usage guide](https://www.ohwr.org ...@@ -10,31 +10,28 @@ Please update using the [recommended setup and usage guide](https://www.ohwr.org
![](https://ohwr.org/erikvanderbij/template/uploads/23a127884e2820d707e58c6119cde69d/spec_v1.1_top.JPG) ![](https://ohwr.org/erikvanderbij/template/uploads/23a127884e2820d707e58c6119cde69d/spec_v1.1_top.JPG)
**SPEC 1.1 first prototype** **SPEC 1.1 first prototype**
## Preliminary Specifications ## Specifications
|**Parameter**|**Value**| |**Parameter**|**Value**|
|----|----| |----|----|
|PCB format|VITA 57.1 FMC LPC| |PCB format|VITA 57.1 FMC HPC (single width, ruggedized)|
|Connectors|SMA| |Connectors|SMA|
|Sampling Rate|1 GSPS (preferably 2GSPS)| |Sampling Rate|500 MSPS|
|Input Signal Type|single-ended| |Input Signal Type|single-ended|
|Resolution|8 bits| |Resolution|14 bits|
|Number of Channels|2 (preferably 4)| |Number of Channels|4|
|Bandwidth (-3dB)|50Ω: DC to 400MHz (or better) <br/> 1MΩ: DC to 300MHz (or better)| |Bandwidth (-3dB)|DC to 500&nbsp;MHz (or better)|
|Input Signal Coupling and Termination|AC (8 Hz LF limit, after 50 Ω termination) <br/> DC-50Ω <br/>DC-1MΩ| |Input Signal Coupling and Termination|DC 50&nbsp;Ω|
|Input Signal Range|+/- 50mV<br/>+/- 250mV<br/>+/- 500mV<br/>+/- 2.5V<br/>+/- 5V| |Input Signal Range|+/-&nbsp;500&nbsp;mV|
|Max Input Signal Amplitude|+/- 10V| |Max Input Signal Amplitude|+/-&nbsp;1&nbsp;V|
|SNR|> 40dB full bandwidth over all input ranges| |SNR|≥ 60&nbsp;dB full bandwidth|
|ENOB|> 6.5 full bandwidth over all input ranges| |ENOB|≥ 9.5 at 70-250&nbsp;MHz|
|Offset Adjustment Range|+/- 5V| |Offset Adjustment Range|N/A|
|Offset Adjustment Resolution|16 bits| |Additional I/O|External 10&nbsp;MHz clock input<br>5&nbsp;LEDs|
|Offset Adjustment Accuracy|< 1%| |Self-calibration|N/A|
|Additional I/O|External TTL trigger in/out (bidirectional)<br/>External 10MHz clock input| |ADC interface|JESD204B (8 lanes)|
|Self-calibration|Automatic zeroing of offset and gain| |FMC EEPROM|24LC64, as per VITA 57.1|
|ADC interface|serial/parallel LVDS| |Power Consumption| specified as < 11&nbsp;W|
|Temperature sensor|via one-wire ds182x|
|FMC EEPROM|24C02, as per VITA 57.1|
|Power Consumption| specified as < 7W (design estimation 9.6W) |
**Notes:** **Notes:**
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