... | @@ -24,11 +24,7 @@ The project is divided into four sub-projects: |
... | @@ -24,11 +24,7 @@ The project is divided into four sub-projects: |
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: Linux device driver, library and tools.
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: Linux device driver, library and tools.
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- Testing support : Production and functional tests.
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- Testing support : Production and functional tests.
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Please refer to the corresponding sub-project for detailed
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Please refer to the corresponding sub-project for detailed information.
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information.
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[![](/project/fmc-adc-100m14b4cha/uploads/d48f899d27512044661f3f60d68afbf7/fmc-adc_v3_front_small.jpg)](/project/fmc-adc-100m14b4cha/uploads/669878f74ff69e386880d0d4394af9bd/fmc-adc_v3_front.jpg)
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[![](/project/fmc-adc-100m14b4cha/uploads/a2dfe49c172c38146036b235e71b4c02/fmc-adc_v3_top_small.jpg)](/project/fmc-adc-100m14b4cha/uploads/c812d406ca2b548917d8ff6a4c9301f4/fmc-adc_v3_top.jpg)
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## Specifications
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## Specifications
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... | @@ -40,19 +36,11 @@ information. |
... | @@ -40,19 +36,11 @@ information. |
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
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<td>max. sample rate</td>
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<td>max. sample rate</td>
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<td>105 MSPS (default 100MSPS)</td>
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<td>400 kSPS (ADC has 200kSPS, but 2 ADC channels per input are used)</td>
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</tr>
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</tr>
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<tr class="odd">
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<tr class="odd">
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<td>analog bandwidth</td>
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<td>30 MHz. DC-coupled (40 MHz possible by changing eight capacitors)</td>
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</tr>
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<tr class="even">
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<td>bits/sample</td>
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<td>bits/sample</td>
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<td>14 bit</td>
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<td>18 bit</td>
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</tr>
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<tr class="odd">
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<td>ENOB</td>
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<td>11, 11.5, 11.7 bit (@ <em>/-50mV,</em>/-0.5V, +/-5V range)</td>
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
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<td>channels</td>
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<td>channels</td>
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... | @@ -60,38 +48,24 @@ information. |
... | @@ -60,38 +48,24 @@ information. |
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</tr>
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</tr>
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<tr class="odd">
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<tr class="odd">
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<td>connectors</td>
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<td>connectors</td>
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<td>4 x LEMO 00 for signals, 1 x LEMO 00 for trigger</td>
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<td>4 x LEMO 00 for signals, 2 x FFC 40P connectors</td>
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
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<td>input impedance</td>
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<td>input range</td>
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<td>1 kOhm / 50 Ohm - software selectable</td>
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<td>+/-5 V<br />
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+/-10 V</td>
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</tr>
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</tr>
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<tr class="odd">
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<tr class="odd">
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<td>gain steps</td>
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<td>Resistance between grounds</td>
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<td>+/-50 mV<br />
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<td>100MOhm</td>
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+/-0.5 V<br />
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+/-5 V</td>
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
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<td>offset correction range</td>
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<td>others</td>
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<td>+/- 5 V for every input voltage range</td>
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<td>10-bit ADC to measure the isolated voltage, temperature sensor</td>
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</tr>
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<tr class="odd">
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<td>max. gain error</td>
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<td>+/- 1 %</td>
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</tr>
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<tr class="even">
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<td>SNR</td>
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<td>67.7 dB, 70.8 dB, 72.2 dB (@ <em>/-50mV,</em>/-0.5V, +/-5V range)</td>
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</tr>
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</tr>
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<tr class="odd">
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<tr class="odd">
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<td>FMC to carrier interface</td>
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<td>FMC to carrier interface</td>
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<td>FMC high pin count connector (HPC only used if external clock is selected)</td>
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<td>FMC low pin count connector</td>
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</tr>
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<tr class="even">
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<td>Clock source</td>
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<td>Internal: from programmable on-board oscillator.<br />
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External: from dedicated FMC connector pins (HPC) when changing two capacitors.</td>
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</tr>
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</tr>
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</tbody>
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</tbody>
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</table>
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</table>
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... | @@ -100,8 +74,8 @@ External: from dedicated FMC connector pins (HPC) when changing two capacitors.< |
... | @@ -100,8 +74,8 @@ External: from dedicated FMC connector pins (HPC) when changing two capacitors.< |
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## Releases
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## Releases
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- Hardware: see EDMS (CERN Electronic Document Management System)
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- Hardware: see [hardware sub-project releases
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document [EDA-02063.](https://edms.cern.ch/nav/EDA-02063)
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page.](https://www.ohwr.org/project/fmc-adc-100m14b4cha-hw/wikis/Releases)
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- Gateware: see [gateware sub-project releases
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- Gateware: see [gateware sub-project releases
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page.](https://www.ohwr.org/project/fmc-adc-100m14b4cha-gw/wikis/Releases)
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page.](https://www.ohwr.org/project/fmc-adc-100m14b4cha-gw/wikis/Releases)
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- Software: see [software sub-project releases
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- Software: see [software sub-project releases
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... | @@ -111,32 +85,15 @@ External: from dedicated FMC connector pins (HPC) when changing two capacitors.< |
... | @@ -111,32 +85,15 @@ External: from dedicated FMC connector pins (HPC) when changing two capacitors.< |
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## Project Information
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## Project Information
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- [Users](Users)
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- [Frequently Asked Questions](FAQ)
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- [Mailing list
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fmc-adc-100m14b4cha@ohwr.org](https://www.ohwr.org/mailing_list/show?project_id=fmc-adc-100m14b4cha)
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and its archive.
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-----
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-----
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## Contacts
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## Contacts
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### Commercial producers
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### Commercial producers
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- [4ch 105 Msps 14 bit ADC 30
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MHz](http://www.incaacomputers.com/component/resource/article/products/by-formfactor/43-fpga-mezzanine-card/165-4ch-100msamples-14-bit-adc)
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[INCAA Computers](http://incaacomputers.nl), Netherlands. (standard
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design)
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- [4ch 105 Msps 14 bit ADC 40
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MHz](http://www.incaacomputers.com/component/resource/article/products/by-function/35-adc/170-4ch-105-msps-40mhz-14-bit-adc)
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[INCAA Computers](http://incaacomputers.nl), Netherlands.
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- [FMC
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ADC 100M 14b 4cha](http://www.creotech.pl/en/offer/white-rabbit/FMC_ADC_100M_14b_4cha)
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[Creotech](http://creotech.pl/), Poland
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### General question about project
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### General question about project
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- [Erik van der Bij](mailto:Erik.van.der.Bij@cern.ch) - CERN
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- [Oscar Matilla](mailto:omatilla@cells.es) - ALBA Synchrotron
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-----
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-----
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... | @@ -149,109 +106,21 @@ External: from dedicated FMC connector pins (HPC) when changing two capacitors.< |
... | @@ -149,109 +106,21 @@ External: from dedicated FMC connector pins (HPC) when changing two capacitors.< |
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<td><b> Event </b></td>
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<td><b> Event </b></td>
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
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<td>01-10-2009</td>
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<td>22-01-2014</td>
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<td>Start working on project</td>
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<td>Start working on project</td>
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</tr>
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</tr>
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<tr class="odd">
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<tr class="odd">
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<td>25-10-2009</td>
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<td>23-09-2014</td>
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<td>Functional specification written.</td>
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<td>First production of the board.</td>
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</tr>
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<tr class="even">
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<td>22-01-2010</td>
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<td>FmcAdc100M14b4cha upgrade. Design revised and modified, better parameters expected.</td>
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</tr>
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<tr class="odd">
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<td>10-02-2010</td>
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<td>New design made with 3 input ranges and programmable offset.</td>
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</tr>
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<tr class="even">
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<td>04-03-2010</td>
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<td>Improvements made, responding to design review. [fmc-adc-100m14b4cha-hw:V1ReviewImprov](https://www.ohwr.org/project/fmc-adc-100m14b4cha-hw/wikis)</td>
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</tr>
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<tr class="odd">
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<td>24-03-2010</td>
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<td>Design review of PCB layout done. [fmc-adc-100m14b4cha-hw:V1LayoutReview](https://www.ohwr.org/project/fmc-adc-100m14b4cha-hw/wikis)</td>
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</tr>
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<tr class="even">
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<td>09-06-2010</td>
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<td>3 assembled boards received.</td>
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</tr>
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<tr class="odd">
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<td>12-07-2010</td>
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<td>One board plugged in on Xilinx development kit and powered. Debugging start.</td>
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</tr>
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<tr class="even">
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<td>30-07-2010</td>
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<td>ENOB & SNR measured: >11 bits in all ranges.</td>
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</tr>
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<tr class="odd">
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<td>08-09-2010</td>
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<td>Issue with linearity in the 30-90 kHz region caused by offset compensation circuit being investigated.</td>
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</tr>
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<tr class="even">
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<td>29-09-2010</td>
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<td>Updates to PCB made (EDA-02063-V2). Ten boards ordered. Designer left CERN.</td>
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</tr>
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<tr class="odd">
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<td>07-01-2011</td>
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<td>Ten V2 boards arrived.</td>
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</tr>
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<tr class="even">
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<td>08-03-2011</td>
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<td>Basic HDL code written (single shot, no time stamps). Needs testing.</td>
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</tr>
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<tr class="odd">
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<td>04-07-2011</td>
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<td>V3 reviewed. <a href="https://www.ohwr.org/project/fmc-adc-100m14b4cha-hw/wikis">V3 review</a>. 3 prototypes will be built.</td>
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</tr>
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<tr class="even">
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<td>01-08-2011</td>
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<td>Price Enquiry sent out for first Open Hardware production.</td>
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</tr>
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<tr class="odd">
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<td>15-09-2011</td>
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<td>V4 design made. Corrected some textual problems and one BOM item order number.</td>
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</tr>
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<tr class="even">
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<td>20-09-2011</td>
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<td>Order for 40 cards placed with INCAA Computers (V5). Delivery in January 2012.</td>
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</tr>
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<tr class="odd">
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<td>20-12-2011</td>
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<td>Measured bandwidth is 30 MHz. 40 MHz bandwidth is possible by changing 2 capacitors per channel.</td>
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</tr>
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<tr class="even">
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<td>04-04-2012</td>
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<td>First production received: 40 V5 cards produced by INCAA Computers.</td>
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</tr>
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<tr class="odd">
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<td>12-03-2013</td>
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<td><a href="https://www.ohwr.org/project/fmc-adc-100m14b4cha-gw/wikis">Release 1.0</a> of the fmc-adc gateware for SPEC is available.</td>
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</tr>
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<tr class="even">
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<td>19-07-2013</td>
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<td>Firmware ported to work on the [SVEC VME carrier](https://www.ohwr.org/project/svec/wiki).</td>
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</tr>
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<tr class="odd">
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<td>17-01-2014</td>
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<td>Release 3.0 of the fmc-adc gateware for <a href="https://www.ohwr.org/project/fmc-adc-100m14b4cha-gw/wikis">SPEC</a> and <a href="https://www.ohwr.org/project/fmc-adc-100m14b4cha-gw/wikis">SVEC</a> is available.</td>
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</tr>
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<tr class="even">
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<td>24-03-2014</td>
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<td>Cards deployed in CERN's accelerator complex. Start of development to deployement: 4.5 year.</td>
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</tr>
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<tr class="odd">
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<td>22-04-2014</td>
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<td>CERN ordered 100 boards (V5-0) for delivery by 18/7/14 (20) and 19/9/14 (80).</td>
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
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<td>07-09-2015</td>
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<td>13-10-2015</td>
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<td>Over 40 installed in CERN's accelerator complex.</td>
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<td>First public realize.</td>
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</tr>
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</tr>
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</tbody>
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</tbody>
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</table>
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</table>
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-----
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-----
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Maciej Firmiarz, Matthieu Cattin, Erik van der Bij - 7 September 2015
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Xavier Serra - 13 October 2015
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