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# Review24032010 improvements
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# PCB Layout review of FMCADC100M14b4cha
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24 March 2010
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PCB layout of 2010-03-12 -
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https://www.ohwr.org/81
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# Present
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Maciej Fimiarz (designer, BE/CO), Pablo Alvarez (BE/CO), Matthieu Cattin
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(BE/CO), Erik van der Bij (BE/CO), Tomasz Wlostowski (BE/CO).
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# General description of the PCB layout.
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The detailed PCB layout has been made by the design office of the
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EN-ICE-DEM with input from Maciej. It is a 6-layer board. There are two
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solid ground planes, while the eight different supply voltages are
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carried by wide tracks. The four channels are somewhat spaced apart, no
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other measures are believed necessary for channel separation.
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# Detailed comments on the PCB layout
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The following sections give a global idea of the improvements proposed
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during the review. It is not an exhaustive list.
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## Signal quality
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- Make supply lines wider (plane like), possibly by making other
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signal lines smaller. Despite the fact that the currents are low,
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this will provide a small distributed decoupling capacitor (10's of
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pF).
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- Put more vias under the LDO in the top-right corner for better heat
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transfer.
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- Reroute clock input from the FMC connector. This allows removing of
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vias in the main clock line.
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- Swap the local clock oscillator outputs. This allows removing vias
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in the local clock line.
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- Move filter on P12V from the lower part of the card to the top. This
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was the long line carries a clean signal.
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- In the area of R29/R30/C13 cleanup so a via on P1V8 can be removed
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and power tracks can be widened (notably M8V).
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- Rotate L9 so can remove via in plane.
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- Space vias further apart (or make clearing smaller, to be checked
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with DEM) to remove large splits in ground planes and power tracks.
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## Production related
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- Vias of the FMC connector should be covered with solder mask.
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- Large metal pad under ADC: split into four smaller areas to have
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improved solderability.
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- LD1 silkscreen over a pad (possibly on wrong layer in PCB -
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mechanical).
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- Make all vias bigger.
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## Cosmetical
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- Move texts on silkscreen to be not on top of vias.
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- Add several texts with full name of card (FMCADC100M14b4ch) and also
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in full text: e.g. "100 MSPS, 14-bit, 4 channel ADC".
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- FMC connector: mark rows (A, B, C, ...) and pins 1, 10, 20, 30, 40.
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## To be verified
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- Verify if each IC and plane has correct decoupling capacitors.
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# Conclusions
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This has been a very useful review that introduced several improvements.
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Overall the layout was already fine and would have given a working
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board. Certain of the suggested changes will make the layout better,
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likely improving SNR and EMC features. Other changes will improve the
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production process or are just cosmetical.
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To gain time, it has been decided that Maciej and Tomasz will do the
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changes before submitting them to the design office again.
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We thank all people involved in the review.
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\- Erik van der Bij - 24 March 2010
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