... | @@ -14,73 +14,26 @@ range. |
... | @@ -14,73 +14,26 @@ range. |
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## Specifications
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## Specifications
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<table>
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|**Parameter**|**Value**|
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<tbody>
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|----|----|
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<tr class="odd">
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|max. sample rate|105 MSPS (default 100MSPS)|
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<td><strong>Parameter</strong></td>
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|analog bandwidth|30 MHz. DC-coupled (40 MHz possible by changing eight capacitors)|
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<td><strong>Value</strong></td>
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|bits/sample|14 bit|
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</tr>
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|ENOB|original specification: 11.0, 11.5, 11.7 bit (@ /-50mV,/-0.5V, +/-5V range) see below for actual 2017 measurements|
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<tr class="even">
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|SNR|original specification: 67.7 dB, 70.8 dB, 72.2 dB (@ /-50mV,/-0.5V, +/-5V range) see below for actual 2017 measurements|
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<td>max. sample rate</td>
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|channels|4|
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<td>105 MSPS (default 100MSPS)</td>
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|connectors|4 x LEMO 00 for signals, 1 x LEMO 00 for trigger|
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</tr>
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|input impedance|1 kOhm / 50 Ohm - software selectable|
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<tr class="odd">
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|gain steps|+/-50 mV
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<td>analog bandwidth</td>
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+/-0.5 V
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<td>30 MHz. DC-coupled (40 MHz possible by changing eight capacitors)</td>
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+/-5 V|
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</tr>
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|offset correction range|+/- 5 V for every input voltage range|
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<tr class="even">
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|max. gain error|/- 1 % (30-70°C);/- 2 % (0-70°C)|
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<td>bits/sample</td>
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|max. offset error|/- 0.4 % (30-70°C);/- 0.5 % (0-70°C)|
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<td>14 bit</td>
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|FMC to carrier interface|FMC high pin count connector (HPC only used if external clock is selected)|
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</tr>
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|Clock source|Internal: from programmable on-board oscillator.
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<tr class="odd">
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External: from dedicated FMC connector pins (HPC) when changing two capacitors.|
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<td>ENOB</td>
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<td>original specification: <del>11.0, 11.5, 11.7 bit (@ <em>/-50mV,</em>/-0.5V, +/-5V range)</del> see below for actual 2017 measurements</td>
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</tr>
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<tr class="even">
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<td>SNR</td>
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<td>original specification: <del>67.7 dB, 70.8 dB, 72.2 dB (@ <em>/-50mV,</em>/-0.5V, +/-5V range)</del> see below for actual 2017 measurements</td>
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</tr>
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<tr class="odd">
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<td>channels</td>
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<td>4</td>
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</tr>
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<tr class="even">
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<td>connectors</td>
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<td>4 x LEMO 00 for signals, 1 x LEMO 00 for trigger</td>
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</tr>
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<tr class="odd">
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<td>input impedance</td>
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<td>1 kOhm / 50 Ohm - software selectable</td>
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</tr>
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<tr class="even">
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<td>gain steps</td>
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<td>+/-50 mV<br />
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+/-0.5 V<br />
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+/-5 V</td>
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</tr>
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<tr class="odd">
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<td>offset correction range</td>
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<td>+/- 5 V for every input voltage range</td>
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</tr>
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<tr class="even">
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<td>max. gain error</td>
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<td><em>/- 1 % (30-70°C);</em>/- 2 % (0-70°C)</td>
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</tr>
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<tr class="odd">
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<td>max. offset error</td>
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<td><em>/- 0.4 % (30-70°C);</em>/- 0.5 % (0-70°C)</td>
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</tr>
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<tr class="even">
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<td>FMC to carrier interface</td>
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<td>FMC high pin count connector (HPC only used if external clock is selected)</td>
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</tr>
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<tr class="odd">
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<td>Clock source</td>
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<td>Internal: from programmable on-board oscillator.<br />
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External: from dedicated FMC connector pins (HPC) when changing two capacitors.</td>
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</tr>
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</tbody>
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</table>
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*2017 measurements**
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*2017 measurements**
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... | @@ -165,130 +118,38 @@ Other information: |
... | @@ -165,130 +118,38 @@ Other information: |
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## Status
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## Status
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<table>
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|**Date**|**Event**|
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<tbody>
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|----|----|
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<tr class="odd">
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|01-10-2009|Start working on project|
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<td><strong>Date</strong></td>
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|25-10-2009|Functional specification written.|
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<td><b> Event </b></td>
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|22-01-2010|FmcAdc100M14b4cha upgrade. Design revised and modified, better parameters expected.|
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</tr>
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|10-02-2010|New design made with 3 input ranges and programmable offset.|
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<tr class="even">
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|04-03-2010|Improvements made, responding to design review. [fmc-adc-100m14b4cha-hw:V1ReviewImprov](https://www.ohwr.org/project/fmc-adc-100m14b4cha-hw/wikis)|
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<td>01-10-2009</td>
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|24-03-2010|Design review of PCB layout done. [fmc-adc-100m14b4cha-hw:V1LayoutReview](https://www.ohwr.org/project/fmc-adc-100m14b4cha-hw/wikis)|
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<td>Start working on project</td>
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|09-06-2010|3 assembled boards received.|
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</tr>
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|12-07-2010|One board plugged in on Xilinx development kit and powered. Debugging start.|
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<tr class="odd">
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|30-07-2010|ENOB & SNR measured: >11 bits in all ranges.|
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<td>25-10-2009</td>
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|08-09-2010|Issue with linearity in the 30-90 kHz region caused by offset compensation circuit being investigated.|
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<td>Functional specification written.</td>
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|29-09-2010|Updates to PCB made (EDA-02063-V2). Ten boards ordered. Designer left CERN.|
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</tr>
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|07-01-2011|Ten V2 boards arrived.|
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<tr class="even">
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|08-03-2011|Basic HDL code written (single shot, no time stamps). Needs testing.|
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<td>22-01-2010</td>
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|04-07-2011|V3 reviewed. [V3 review](https://www.ohwr.org/project/fmc-adc-100m14b4cha-hw/wikis). 3 prototypes will be built.|
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<td>FmcAdc100M14b4cha upgrade. Design revised and modified, better parameters expected.</td>
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|01-08-2011|Price Enquiry sent out for first Open Hardware production.|
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</tr>
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|15-09-2011|V4 design made. Corrected some textual problems and one BOM item order number.|
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<tr class="odd">
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|20-09-2011|Order for 40 cards placed with INCAA Computers (V5). Delivery in January 2012.|
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<td>10-02-2010</td>
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|20-12-2011|Measured bandwidth is 30 MHz. 40 MHz bandwidth is possible by changing 2 capacitors per channel.|
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<td>New design made with 3 input ranges and programmable offset.</td>
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|04-04-2012|First production received: 40 V5 cards produced by INCAA Computers.|
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</tr>
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|12-03-2013|[Release 1.0](https://www.ohwr.org/project/fmc-adc-100m14b4cha-gw/wikis) of the fmc-adc gateware for SPEC is available.|
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<tr class="even">
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|19-07-2013|Firmware ported to work on the [SVEC VME carrier](https://www.ohwr.org/project/svec/wiki).|
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<td>04-03-2010</td>
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|17-01-2014|Release 3.0 of the fmc-adc gateware for [SPEC](https://www.ohwr.org/project/fmc-adc-100m14b4cha-gw/wikis) and [SVEC](https://www.ohwr.org/project/fmc-adc-100m14b4cha-gw/wikis) is available.|
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<td>Improvements made, responding to design review. [fmc-adc-100m14b4cha-hw:V1ReviewImprov](https://www.ohwr.org/project/fmc-adc-100m14b4cha-hw/wikis)</td>
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|24-03-2014|Cards deployed in CERN's accelerator complex. Start of development to deployement: 4.5 year.|
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</tr>
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|22-04-2014|CERN ordered 100 boards (V5-0) for delivery by 18/7/14 (20) and 19/9/14 (80).|
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<tr class="odd">
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|07-09-2015|Over 40 installed in CERN's accelerator complex.|
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<td>24-03-2010</td>
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|08-09-2017|New performance measurements being made.|
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<td>Design review of PCB layout done. [fmc-adc-100m14b4cha-hw:V1LayoutReview](https://www.ohwr.org/project/fmc-adc-100m14b4cha-hw/wikis)</td>
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|09-10-2017|[Detailed performance measurements made.](https://www.ohwr.org/documents/712)|
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</tr>
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|16-11-2017|"CERN ADC Development report for FMC-ADC-100M" draft received. Shows frequency response is OK.|
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<tr class="even">
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|25-07-2018|Extra stability measurements made: [2017 and 2018 Integration and Measurement results](https://www.ohwr.org/documents/712)|
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<td>09-06-2010</td>
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<td>3 assembled boards received.</td>
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</tr>
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<tr class="odd">
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<td>12-07-2010</td>
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<td>One board plugged in on Xilinx development kit and powered. Debugging start.</td>
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</tr>
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<tr class="even">
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<td>30-07-2010</td>
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<td>ENOB & SNR measured: >11 bits in all ranges.</td>
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</tr>
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<tr class="odd">
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<td>08-09-2010</td>
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<td>Issue with linearity in the 30-90 kHz region caused by offset compensation circuit being investigated.</td>
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</tr>
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<tr class="even">
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<td>29-09-2010</td>
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<td>Updates to PCB made (EDA-02063-V2). Ten boards ordered. Designer left CERN.</td>
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</tr>
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<tr class="odd">
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<td>07-01-2011</td>
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<td>Ten V2 boards arrived.</td>
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</tr>
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<tr class="even">
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<td>08-03-2011</td>
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<td>Basic HDL code written (single shot, no time stamps). Needs testing.</td>
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</tr>
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<tr class="odd">
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<td>04-07-2011</td>
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<td>V3 reviewed. <a href="https://www.ohwr.org/project/fmc-adc-100m14b4cha-hw/wikis">V3 review</a>. 3 prototypes will be built.</td>
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</tr>
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<tr class="even">
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<td>01-08-2011</td>
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<td>Price Enquiry sent out for first Open Hardware production.</td>
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</tr>
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<tr class="odd">
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<td>15-09-2011</td>
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<td>V4 design made. Corrected some textual problems and one BOM item order number.</td>
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</tr>
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<tr class="even">
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<td>20-09-2011</td>
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<td>Order for 40 cards placed with INCAA Computers (V5). Delivery in January 2012.</td>
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</tr>
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<tr class="odd">
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<td>20-12-2011</td>
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<td>Measured bandwidth is 30 MHz. 40 MHz bandwidth is possible by changing 2 capacitors per channel.</td>
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</tr>
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<tr class="even">
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<td>04-04-2012</td>
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<td>First production received: 40 V5 cards produced by INCAA Computers.</td>
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</tr>
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<tr class="odd">
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<td>12-03-2013</td>
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<td><a href="https://www.ohwr.org/project/fmc-adc-100m14b4cha-gw/wikis">Release 1.0</a> of the fmc-adc gateware for SPEC is available.</td>
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</tr>
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<tr class="even">
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<td>19-07-2013</td>
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<td>Firmware ported to work on the [SVEC VME carrier](https://www.ohwr.org/project/svec/wiki).</td>
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</tr>
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<tr class="odd">
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<td>17-01-2014</td>
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<td>Release 3.0 of the fmc-adc gateware for <a href="https://www.ohwr.org/project/fmc-adc-100m14b4cha-gw/wikis">SPEC</a> and <a href="https://www.ohwr.org/project/fmc-adc-100m14b4cha-gw/wikis">SVEC</a> is available.</td>
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</tr>
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<tr class="even">
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<td>24-03-2014</td>
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<td>Cards deployed in CERN's accelerator complex. Start of development to deployement: 4.5 year.</td>
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</tr>
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<tr class="odd">
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<td>22-04-2014</td>
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<td>CERN ordered 100 boards (V5-0) for delivery by 18/7/14 (20) and 19/9/14 (80).</td>
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</tr>
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<tr class="even">
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<td>07-09-2015</td>
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<td>Over 40 installed in CERN's accelerator complex.</td>
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</tr>
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<tr class="odd">
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<td>08-09-2017</td>
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<td>New performance measurements being made.</td>
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</tr>
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<tr class="even">
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<td>09-10-2017</td>
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<td>[Detailed performance measurements made.](https://www.ohwr.org/documents/712)</td>
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</tr>
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<tr class="odd">
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<td>16-11-2017</td>
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<td>"CERN ADC Development report for FMC-ADC-100M" draft received. Shows frequency response is OK.</td>
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</tr>
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<tr class="even">
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<td>25-07-2018</td>
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<td>Extra stability measurements made: [2017 and 2018 Integration and Measurement results](https://www.ohwr.org/documents/712)</td>
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</tr>
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</tbody>
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</table>
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[Complete status](complete-status)
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[Complete status](complete-status)
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... | @@ -298,3 +159,4 @@ Other information: |
... | @@ -298,3 +159,4 @@ Other information: |
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Maciej Firmiarz, Matthieu Cattin, Erik van der Bij - 25 October 2018
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Maciej Firmiarz, Matthieu Cattin, Erik van der Bij - 25 October 2018
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