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FMC ADC 100M 14b 4cha - Testing
Commit c48ae8d9 authored by Matthieu Cattin's avatar Matthieu Cattin
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fmc_adc: Exception handling added, common modules interface updated. 

Most of the function still needs to be tested.
parent 5aae3b2f
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Showing with 296 additions and 214 deletions
test/fmcadc100m14b4cha/python/fmc_adc.py
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...@@ -157,8 +157,6 @@ class CFmcAdc100m: ...@@ -157,8 +157,6 @@ class CFmcAdc100m:
CTL_MASK = 0xEC CTL_MASK = 0xEC
FSM_CMD_MASK = 0x00000003 FSM_CMD_MASK = 0x00000003
FSM_CMD_START = 0x1
FSM_CMD_STOP = 0x2
STA_FSM = 0 STA_FSM = 0
STA_SERDES_SYNCED = 4 STA_SERDES_SYNCED = 4
...@@ -166,6 +164,8 @@ class CFmcAdc100m: ...@@ -166,6 +164,8 @@ class CFmcAdc100m:
FSM_MASK = 0x00000007 FSM_MASK = 0x00000007
""" """
FSM_CMD_START = 0x1
FSM_CMD_STOP = 0x2
FSM_STATES = ['N/A','IDLE','PRE_TRIG','WAIT_TRIG', FSM_STATES = ['N/A','IDLE','PRE_TRIG','WAIT_TRIG',
'POST_TRIG','DECR_SHOT','N/A','others'] 'POST_TRIG','DECR_SHOT','N/A','others']
...@@ -190,6 +190,8 @@ class CFmcAdc100m: ...@@ -190,6 +190,8 @@ class CFmcAdc100m:
'100mV':{'offset':[0x0,0x0,0x0,0x0],'gain':[0x8000,0x8000,0x8000,0x8000]}} '100mV':{'offset':[0x0,0x0,0x0,0x0],'gain':[0x8000,0x8000,0x8000,0x8000]}}
WAIT_TIME_OUT = 2
def channel_addr(self, channel, reg): def channel_addr(self, channel, reg):
if(channel < 1 or channel > 4): if(channel < 1 or channel > 4):
...@@ -202,39 +204,42 @@ class CFmcAdc100m: ...@@ -202,39 +204,42 @@ class CFmcAdc100m:
def __init__(self, bus): def __init__(self, bus):
self.bus = bus self.bus = bus
# Objects declaration
try: try:
# Objects declaration
self.fmc_sys_i2c = COpenCoresI2C(self.bus, self.FMC_SYS_I2C_ADDR, 249) self.fmc_sys_i2c = COpenCoresI2C(self.bus, self.FMC_SYS_I2C_ADDR, 249)
self.fmc_i2c = COpenCoresI2C(self.bus, self.FMC_I2C_ADDR, 249) self.fmc_i2c = COpenCoresI2C(self.bus, self.FMC_I2C_ADDR, 249)
except I2CDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
self.eeprom_24aa64 = C24AA64(self.fmc_sys_i2c, self.EEPROM_ADDR)
self.si570 = CSi57x(self.fmc_i2c, self.SI570_ADDR)
self.fmc_onewire = COpenCoresOneWire(self.bus, self.FMC_ONEWIRE_ADDR, 624, 124) self.eeprom_24aa64 = C24AA64(self.fmc_sys_i2c, self.EEPROM_ADDR)
self.ds18b20 = CDS18B20(self.fmc_onewire, 0) self.si570 = CSi57x(self.fmc_i2c, self.SI570_ADDR)
self.fmc_onewire = COpenCoresOneWire(self.bus, self.FMC_ONEWIRE_ADDR, 624, 124)
self.ds18b20 = CDS18B20(self.fmc_onewire, 0)
self.fmc_adc_csr = CCSR(self.bus, self.FMC_CSR_ADDR, FMCADC100M_CSR) self.fmc_spi = COpenCoresSPI(self.bus, self.FMC_SPI_ADDR, self.FMC_SPI_DIV)
self.adc_cfg = CLTC217x(self.fmc_spi, self.FMC_SPI_SS['ADC'])
self.dac_ch = []
self.dac_ch.append(CMAX5442(self.fmc_spi, self.FMC_SPI_SS['DAC1']))
self.dac_ch.append(CMAX5442(self.fmc_spi, self.FMC_SPI_SS['DAC2']))
self.dac_ch.append(CMAX5442(self.fmc_spi, self.FMC_SPI_SS['DAC3']))
self.dac_ch.append(CMAX5442(self.fmc_spi, self.FMC_SPI_SS['DAC4']))
self.fmc_spi = COpenCoresSPI(self.bus, self.FMC_SPI_ADDR, self.FMC_SPI_DIV) self.fmc_adc_csr = CCSR(self.bus, self.FMC_CSR_ADDR, FMCADC100M_CSR)
self.adc_cfg = CLTC217x(self.fmc_spi, self.FMC_SPI_SS['ADC'])
self.dac_ch[1] = CMAX5442(self.fmc_spi, self.FMC_SPI_SS['DAC1'])
self.dac_ch[2] = CMAX5442(self.fmc_spi, self.FMC_SPI_SS['DAC2'])
self.dac_ch[3] = CMAX5442(self.fmc_spi, self.FMC_SPI_SS['DAC3'])
self.dac_ch[4] = CMAX5442(self.fmc_spi, self.FMC_SPI_SS['DAC4'])
# Set channels gain to 1 # Set channels gain to 1
self.fmc_adc_csr.set_field('CH1_GAIN', 'VAL', 0x8000) self.fmc_adc_csr.set_field('CH1_GAIN', 'VAL', 0x8000)
self.fmc_adc_csr.set_field('CH2_GAIN', 'VAL', 0x8000) self.fmc_adc_csr.set_field('CH2_GAIN', 'VAL', 0x8000)
self.fmc_adc_csr.set_field('CH3_GAIN', 'VAL', 0x8000) self.fmc_adc_csr.set_field('CH3_GAIN', 'VAL', 0x8000)
self.fmc_adc_csr.set_field('CH4_GAIN', 'VAL', 0x8000) self.fmc_adc_csr.set_field('CH4_GAIN', 'VAL', 0x8000)
# Enable mezzanine clock and offset DACs # Enable mezzanine clock and offset DACs
self.fmc_adc_csr.set_field('CTL', 'FMC_CLK_OE', 1) self.en_sampfreq()
self.fmc_adc_csr.set_field('CTL', 'OFFSET_DAC_CLR_N', 1) self.dc_offset_reset()
# Disable ADC test pattern # Disable ADC test pattern
self.adc_cfg.dis_testpat() self.adc_cfg.dis_testpat()
except (I2CDeviceOperationError, CSRDeviceOperationError, LTC217xOperationError) as e:
raise FmcAdc100mOperationError(e)
def channel_check(self, channel): def channel_check(self, channel):
...@@ -367,18 +372,20 @@ class CFmcAdc100m: ...@@ -367,18 +372,20 @@ class CFmcAdc100m:
raise FmcAdc100mOperationError(e) raise FmcAdc100mOperationError(e)
# Set channel DC offset (MAX5442 DAC) # Set channel DC offset (MAX5442 DAC)
def set_dc_offset(self, channel, offset): def set_dc_offset(self, channel, value):
ch = self.channel_check(channel) ch = self.channel_check(channel)
try: try:
self.dac_ch[ch].set_value(offset) self.dac_ch[ch-1].set_value(value)
except MAX5442OperationError as e: except MAX5442OperationError as e:
raise FmcAdc100mOperationError(e) raise FmcAdc100mOperationError(e)
# Save a copy of the correction data locally
def set_dac_corr(self, corr_data): def set_dac_corr(self, corr_data):
self.dac_corr_data = corr_data self.dac_corr_data = corr_data
# Apply correction factors to DAC data
def dac_apply_corr(self, value, gain_corr, offset_corr): def dac_apply_corr(self, value, gain_corr, offset_corr):
#print "dac_apply_corr: value:%d offset:%d gain:%d"%(value, hex2signed(offset_corr), gain_corr) #print "[FmcAdc100m] dac_apply_corr: value:%d offset:%d gain:%d"%(value, hex2signed(offset_corr), gain_corr)
value_corr = (((((value - 0x8000) + hex2signed(offset_corr)) << 15) * gain_corr) >> 30) + 0x8000 value_corr = (((((value - 0x8000) + hex2signed(offset_corr)) << 15) * gain_corr) >> 30) + 0x8000
return value_corr return value_corr
...@@ -386,103 +393,132 @@ class CFmcAdc100m: ...@@ -386,103 +393,132 @@ class CFmcAdc100m:
# value = DAC unsigned integer value # value = DAC unsigned integer value
def set_dc_offset_corrected(self, channel, in_range, value, print_value=False): def set_dc_offset_corrected(self, channel, in_range, value, print_value=False):
uncorr_value = value uncorr_value = value
value = self.dac_apply_corr(value, self.dac_corr_data[in_range]['gain'][channel-1],self.dac_corr_data[in_range]['offset'][channel-1]) value = self.dac_apply_corr(value,
self.dac_corr_data[in_range]['gain'][channel-1],
self.dac_corr_data[in_range]['offset'][channel-1])
if(print_value): if(print_value):
print('CH%d DAC uncorrected value: 0x%.4X')%(channel, uncorr_value) print('[FmcAdc100m] CH%d DAC uncorrected value: 0x%.4X')%(channel, uncorr_value)
print('CH%d DAC corrected value : 0x%.4X')%(channel, value) print('[FmcAdc100m] CH%d DAC corrected value : 0x%.4X')%(channel, value)
if(1 == channel): ch = self.channel_check(channel)
self.dac_ch1.set_offset(value) try:
elif(2 == channel): self.dac_ch[ch-1].set_value(value)
self.dac_ch2.set_offset(value) except MAX5442OperationError as e:
elif(3 == channel): raise FmcAdc100mOperationError(e)
self.dac_ch3.set_offset(value)
elif(4 == channel):
self.dac_ch4.set_offset(value)
else:
raise Exception('Unsupported parameter, channel number from 1 to 4')
# Reset DC offset DACs # Reset DC offset DACs
def dc_offset_reset(self): def dc_offset_reset(self):
reg = self.fmc_adc_csr.rd_reg(self.R_CTL) try:
#print("R_CTL:%.8X")%reg self.fmc_adc_csr.set_field('CTL', 'OFFSET_DAC_CLR_N', 0)
reg &= ~(1<<self.CTL_OFFSET_DAC_CLR_N) self.fmc_adc_csr.set_field('CTL', 'OFFSET_DAC_CLR_N', 1)
#print("R_CTL:%.8X")%reg except CSRDeviceOperationError as e:
self.fmc_adc_csr.wr_reg(self.R_CTL, reg) raise FmcAdc100mOperationError(e)
reg |= (1<<self.CTL_OFFSET_DAC_CLR_N)
#print("R_CTL:%.8X")%reg
self.fmc_adc_csr.wr_reg(self.R_CTL, reg)
# Set 50ohms termination # Set 50ohms termination
# channel: integer (1 to 4)
# state: string ('ON' or 'OFF')
def set_input_term(self, channel, state): def set_input_term(self, channel, state):
addr = self.channel_addr(channel,self.R_CH1_SSR) reg_name = 'CH'+str(self.channel_check(channel))+"_CTL"
reg = self.fmc_adc_csr.rd_reg(addr) try:
#print("ssr reg ch%1d: %.8X") %(channel, reg) # Read channel control register
if('ON' == state): reg_val = self.fmc_adc_csr.get_reg(reg_name)
reg |= self.IN_TERM #print "[FmcAdc100m] ssr reg ch%1d: %.8X" % (channel, reg_val)
elif('OFF' == state): if('ON' == state):
reg &= ~(self.IN_TERM) reg_val |= self.IN_TERM
else: elif('OFF' == state):
raise Exception('Unsupported parameter, should be ON or OFF.') reg_val &= ~(self.IN_TERM)
#print("ssr reg ch%1d: %.8X") %(channel, reg) else:
self.fmc_adc_csr.wr_reg(addr, reg) raise FmcAdc100mOperationError("Unsupported state parameter (%s), should be ON or OFF." % state)
#print("ssr reg ch%1d: %.8X") %(channel, self.fmc_adc_csr.rd_reg(addr)) #print "[FmcAdc100m] ssr reg ch%1d: %.8X" % (channel, reg_vale)
self.fmc_adc_csr.set_reg(reg_name, reg_val)
#print "[FmcAdc100m] ssr reg ch%1d: %.8X" % (channel, self.fmc_adc_csr.get_reg(reg_name))
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Set decimation factor # Set decimation factor
def set_decimation(self, factor): def set_decimation(self, factor):
self.fmc_adc_csr.wr_reg(self.R_SRATE, factor) try:
self.fmc_adc_csr.set_field('SR', 'DECI', factor)
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Get decimation factor # Get decimation factor
def get_decimation(self): def get_decimation(self):
return self.fmc_adc_csr.rd_reg(self.R_SRATE) try:
return self.fmc_adc_csr.get_field('SR', 'DECI')
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Enable Sampling clock (Si570) # Enable Sampling clock (Si570)
def en_sampfreq(self): def en_sampfreq(self):
self.fmc_adc_csr.wr_bit(self.R_CTL, self.CTL_CLK_EN, 1) try:
self.fmc_adc_csr.set_field('CTL', 'FMC_CLK_OE', 1)
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Disable Sampling clock (Si570) # Disable Sampling clock (Si570)
def dis_sampfreq(self): def dis_sampfreq(self):
self.fmc_adc_csr.wr_bit(self.R_CTL, self.CTL_CLK_EN, 0) try:
self.fmc_adc_csr.set_field('CTL', 'FMC_CLK_OE', 0)
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Serdes calibration # Serdes 'manual' calibration
def serdes_sync(self): def serdes_sync(self):
print("\nStart serdes synchro") try:
pattern = 0x3456 print "\n[FmcAdc100m] Start serdes synchro"
self.adc_cfg.set_testpat(pattern) pattern = 0x3456
self.adc_cfg.en_testpat() self.adc_cfg.set_testpat(pattern)
print("Test pattern : %.4X") % self.adc_cfg.get_testpat() self.adc_cfg.en_testpat()
print("Test pattern status : %.1X") % self.adc_cfg.get_testpat_stat() print "[FmcAdc100m] Test pattern : %.4X" % self.adc_cfg.get_testpat()
while(pattern != self.fmc_adc_csr.rd_reg(self.R_CH1_VALUE)): print "[FmcAdc100m] Test pattern status : %.1X" % self.adc_cfg.get_testpat_stat()
print("CH1 value : %.4X")%self.fmc_adc_csr.rd_reg(self.R_CH1_VALUE) while(pattern != self.fmc_adc_csr.get_field('CH1_STA', 'VAL')):
print("CH2 value : %.4X")%self.fmc_adc_csr.rd_reg(self.R_CH2_VALUE) for ch in range(1,5,1):
print("CH3 value : %.4X")%self.fmc_adc_csr.rd_reg(self.R_CH3_VALUE) print "[FmcAdc100m] CH%d value : %.4X" % (ch, self.fmc_adc_csr.get_reg('CH'+str(ch)+'_STA', 'VAL'))
print("CH4 value : %.4X")%self.fmc_adc_csr.rd_reg(self.R_CH4_VALUE) self.fmc_adc_csr.set_field('CTL', 'MAN_BITSLIP', 1)
self.fmc_adc_csr.wr_bit(self.R_CTL, self.CTL_BSLIP, 1) time.sleep(.1)
time.sleep(.1) self.adc_cfg.dis_testpat()
self.adc_cfg.dis_testpat() print("[FmcAdc100m] Serdes synced!")
print("Serdes synced!") except (LTC217xOperationError, CSRDeviceOperationError) as e:
raise FmcAdc100mOperationError(e)
# Set test pattern # Set test pattern
def set_testpat(self, pattern): def set_testpat(self, pattern):
self.adc_cfg.set_testpat(pattern) try:
self.adc_cfg.set_testpat(pattern)
except LTC217xOperationError as e:
raise FmcAdc100mOperationError(e)
# Get test pattern # Get test pattern
def get_testpat(self): def get_testpat(self):
return self.adc_cfg.get_testpat() try:
return self.adc_cfg.get_testpat()
except LTC217xOperationError as e:
raise FmcAdc100mOperationError(e)
# Enable test pattern # Enable test pattern
def testpat_en(self, pattern): def testpat_en(self, pattern):
self.adc_cfg.set_testpat(pattern) try:
self.adc_cfg.en_testpat() self.adc_cfg.set_testpat(pattern)
self.adc_cfg.en_testpat()
except LTC217xOperationError as e:
raise FmcAdc100mOperationError(e)
# Disable test pattern # Disable test pattern
def testpat_dis(self): def testpat_dis(self):
self.adc_cfg.dis_testpat() try:
self.adc_cfg.dis_testpat()
except LTC217xOperationError as e:
raise FmcAdc100mOperationError(e)
# Print adc config regs # Print adc config regs
def print_adc_regs(self): def print_adc_regs(self):
self.adc_cfg.print_regs() try:
self.adc_cfg.print_regs()
except LTC217xOperationError as e:
raise FmcAdc100mOperationError(e)
# Set sampling frequency # Set sampling frequency (Si570)
#def set_sampfreq(self, freq): #def set_sampfreq(self, freq):
# Get sampling frequency # Get sampling frequency
...@@ -491,205 +527,254 @@ class CFmcAdc100m: ...@@ -491,205 +527,254 @@ class CFmcAdc100m:
#def get_channel_config(self, channel): #def get_channel_config(self, channel):
# Set trigger configuration # Set trigger configuration
def set_trig_config(self, hw_sel, ext_pol, hw_en, sw_en, int_sel, int_thres, delay): def set_trig_config(self, hw_sel, hw_pol, hw_en, sw_en, channel, int_thres, delay):
# Hardware trigger select (ext/int) ch = self.channel_check(channel)
self.fmc_adc_csr.wr_bit(self.R_TRIG_CFG, self.TRIG_CFG_HW_SEL, hw_sel) try:
# External trigger pulse polarity # Hardware trigger select (ext/int)
self.fmc_adc_csr.wr_bit(self.R_TRIG_CFG, self.TRIG_CFG_EXT_POL, ext_pol) self.fmc_adc_csr.set_field('TRIG_CFG', 'HW_TRIG_SEL', hw_sel)
# Hardware trigger enable # Hardware trigger polarity
self.fmc_adc_csr.wr_bit(self.R_TRIG_CFG, self.TRIG_CFG_HW_EN, hw_en) self.fmc_adc_csr.set_field('TRIG_CFG', 'HW_TRIG_POL', hw_pol)
# Software trigger enable # Hardware trigger enable
self.fmc_adc_csr.wr_bit(self.R_TRIG_CFG, self.TRIG_CFG_SW_EN, sw_en) self.fmc_adc_csr.set_field('TRIG_CFG', 'HW_TRIG_EN', hw_en)
# Internal trigger channel select (1 to 4) # Software trigger enable
reg = self.fmc_adc_csr.rd_reg(self.R_TRIG_CFG) self.fmc_adc_csr.set_field('TRIG_CFG', 'SW_TRIG_EN', sw_en)
reg &= self.INT_SEL_MASK # Internal trigger channel select (1 to 4)
reg += (int_sel<<self.TRIG_CFG_INT_SEL) self.fmc_adc_csr.set_field('TRIG_CFG', 'INT_TRIG_SEL', ch-1)
self.fmc_adc_csr.wr_reg(self.R_TRIG_CFG, reg) # Internal trigger threshold
# Internal trigger threshold self.fmc_adc_csr.set_field('TRIG_CFG', 'INT_TRIG_THRES', int_thres)
reg = self.fmc_adc_csr.rd_reg(self.R_TRIG_CFG) # Trigger delay (in sampling clock ticks)
reg &= self.INT_THRES_MASK self.fmc_adc_csr.set_field('TRIG_DLY', 'TRIG_DLY', delay)
reg += (int_thres<<self.TRIG_CFG_INT_THRES) except CSRDeviceOperationError as e:
self.fmc_adc_csr.wr_reg(self.R_TRIG_CFG, reg) raise FmcAdc100mOperationError(e)
# Trigger delay (in sampling clock ticks)
self.fmc_adc_csr.wr_reg(self.R_TRIG_DLY, delay)
# Get trigger configuration # Get trigger configuration
# Internal trigger # Internal trigger
def set_int_trig(self, channel, polarity, threshold): def set_int_trig(self, channel, polarity, threshold):
# Software trigger disable ch = self.channel_check(channel)
self.fmc_adc_csr.wr_bit(self.R_TRIG_CFG, self.TRIG_CFG_SW_EN, 0) try:
# Select internal hardware trigger # Software trigger disable
self.fmc_adc_csr.wr_bit(self.R_TRIG_CFG, self.TRIG_CFG_HW_SEL, 0) self.fmc_adc_csr.set_field('TRIG_CFG', 'SW_TRIG_EN', 0)
# Trigger polarity # Select internal hardware trigger
self.fmc_adc_csr.wr_bit(self.R_TRIG_CFG, self.TRIG_CFG_EXT_POL, polarity) self.fmc_adc_csr.set_field('TRIG_CFG', 'HW_TRIG_SEL', 0)
# Internal trigger channel select (1 to 4) # Trigger polarity
reg = self.fmc_adc_csr.rd_reg(self.R_TRIG_CFG) self.fmc_adc_csr.set_field('TRIG_CFG', 'HW_TRIG_POL', polarity)
reg &= self.INT_SEL_MASK # Internal trigger channel select (1 to 4)
reg += (int_sel<<self.TRIG_CFG_INT_SEL) self.fmc_adc_csr.set_field('TRIG_CFG', 'INT_TRIG_SEL', ch-1)
self.fmc_adc_csr.wr_reg(self.R_TRIG_CFG, reg) # Internal trigger threshold
# Internal trigger threshold self.fmc_adc_csr.set_field('TRIG_CFG', 'INT_TRIG_THRES', threshold)
reg = self.fmc_adc_csr.rd_reg(self.R_TRIG_CFG) # Hardware trigger enable
reg &= self.INT_THRES_MASK self.fmc_adc_csr.set_field('TRIG_CFG', 'HW_TRIG_EN', 1)
reg += (int_thres<<self.TRIG_CFG_INT_THRES) except CSRDeviceOperationError as e:
self.fmc_adc_csr.wr_reg(self.R_TRIG_CFG, reg) raise FmcAdc100mOperationError(e)
# Hardware trigger enable
self.fmc_adc_csr.wr_bit(self.R_TRIG_CFG, self.TRIG_CFG_HW_EN, 1)
# External trigger # External trigger
def set_ext_trig(self, polarity): def set_ext_trig(self, polarity):
# Software trigger disable try:
self.fmc_adc_csr.wr_bit(self.R_TRIG_CFG, self.TRIG_CFG_SW_EN, 0) # Software trigger disable
# Select external hardware trigger self.fmc_adc_csr.set_field('TRIG_CFG', 'SW_TRIG_EN', 0)
self.fmc_adc_csr.wr_bit(self.R_TRIG_CFG, self.TRIG_CFG_HW_SEL, 1) # Select external hardware trigger
# Trigger polarity self.fmc_adc_csr.set_field('TRIG_CFG', 'HW_TRIG_SEL', 1)
self.fmc_adc_csr.wr_bit(self.R_TRIG_CFG, self.TRIG_CFG_EXT_POL, polarity) # Trigger polarity
# Hardware trigger enable self.fmc_adc_csr.set_field('TRIG_CFG', 'HW_TRIG_POL', polarity)
self.fmc_adc_csr.wr_bit(self.R_TRIG_CFG, self.TRIG_CFG_HW_EN, 1) # Hardware trigger enable
self.fmc_adc_csr.set_field('TRIG_CFG', 'HW_TRIG_EN', 1)
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Software trigger # Software trigger
def set_soft_trig(self): def set_soft_trig(self):
# Hardware trigger disable try:
self.fmc_adc_csr.wr_bit(self.R_TRIG_CFG, self.TRIG_CFG_HW_EN, 0) # Hardware trigger disable
# Software trigger enable self.fmc_adc_csr.set_field('TRIG_CFG', 'HW_TRIG_EN', 0)
self.fmc_adc_csr.wr_bit(self.R_TRIG_CFG, self.TRIG_CFG_SW_EN, 1) # Software trigger enable
self.fmc_adc_csr.set_field('TRIG_CFG', 'SW_TRIG_EN', 1)
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Trigger delay # Trigger delay
def set_trig_delay(self, delay): def set_trig_delay(self, delay):
# Trigger delay (in sampling clock ticks) try:
self.fmc_adc_csr.wr_reg(self.R_TRIG_DLY, delay) # Trigger delay (in sampling clock ticks)
self.fmc_adc_csr.set_field('TRIG_DLY', 'TRIG_DLY', delay)
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Enable test data # Enable test data
def test_data_en(self): def test_data_en(self):
reg = self.fmc_adc_csr.rd_reg(self.R_CTL) try:
print("R_CTL:%.8X")%reg self.fmc_adc_csr.set_field('CTL', 'TEST_DATA_EN', 1)
reg |= ((1<<self.CTL_TEST_DATA_EN) & self.CTL_MASK) except CSRDeviceOperationError as e:
print("R_CTL:%.8X")%reg raise FmcAdc100mOperationError(e)
self.fmc_adc_csr.wr_reg(self.R_CTL, reg)
# Disable test data # Disable test data
def test_data_dis(self): def test_data_dis(self):
reg = self.fmc_adc_csr.rd_reg(self.R_CTL) try:
print("R_CTL:%.8X")%reg self.fmc_adc_csr.set_field('CTL', 'TEST_DATA_EN', 0)
reg &= (~(1<<self.CTL_TEST_DATA_EN) & self.CTL_MASK) except CSRDeviceOperationError as e:
print("R_CTL:%.8X")%reg raise FmcAdc100mOperationError(e)
self.fmc_adc_csr.wr_reg(self.R_CTL, reg)
# Start acquisition # Start acquisition
def start_acq(self): def start_acq(self):
# Wait for serdes to be synced try:
while(0 == self.get_serdes_sync_stat()): # Wait for serdes to be synced
print 'Wait for serdes to be synced' init_time=time.time()
time.sleep(.1) while(0 == self.get_serdes_sync_stat()):
reg = self.fmc_adc_csr.rd_reg(self.R_CTL) if (time.time()-init_time) > self.WAIT_TIME_OUT:
reg &= ~self.FSM_CMD_MASK raise FmcAdc100mOperationError("Wait serdes sync timeout.")
reg |= ((self.FSM_CMD_START<<self.CTL_FSM_CMD) & self.FSM_CMD_MASK) print '[FmcAdc100m] Wait for serdes to be synced'
reg &= (self.CTL_MASK | self.FSM_CMD_MASK) time.sleep(.1)
#print("R_CTL:%.8X")%reg self.fmc_adc_csr.set_field('CTL', 'FSM_CMD', self.FSM_CMD_START)
self.fmc_adc_csr.wr_reg(self.R_CTL, reg) except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Stop acquisition # Stop acquisition
def stop_acq(self): def stop_acq(self):
reg = self.fmc_adc_csr.rd_reg(self.R_CTL) try:
reg &= ~self.FSM_CMD_MASK self.fmc_adc_csr.set_field('CTL', 'FSM_CMD', self.FSM_CMD_STOP)
reg |= ((self.FSM_CMD_STOP<<self.CTL_FSM_CMD) & self.FSM_CMD_MASK) except CSRDeviceOperationError as e:
#print("R_CTL:%.8X")%reg raise FmcAdc100mOperationError(e)
self.fmc_adc_csr.wr_reg(self.R_CTL, reg)
# Software trigger # Software trigger
def sw_trig(self): def sw_trig(self):
while('WAIT_TRIG' != self.get_acq_fsm_state()): try:
#print self.get_acq_fsm_state() init_time=time.time()
#time.sleep(.001) while('WAIT_TRIG' != self.get_acq_fsm_state()):
pass if (time.time()-init_time) > self.WAIT_TIME_OUT:
self.fmc_adc_csr.wr_reg(self.R_SW_TRIG, 0xFFFFFFFF) raise FmcAdc100mOperationError("Wait trigger timeout.")
#print self.get_acq_fsm_state()
#time.sleep(.001)
self.fmc_adc_csr.set_reg('SW_TRIG', 0xFFFFFFFF)
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Software trigger without wait on WAIT_TRIG state # Software trigger without wait on WAIT_TRIG state
def sw_trig_no_wait(self): def sw_trig_no_wait(self):
self.fmc_adc_csr.wr_reg(self.R_SW_TRIG, 0xFFFFFFFF) try:
self.fmc_adc_csr.set_reg('SW_TRIG', 0xFFFFFFFF)
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Set pre-trigger samples # Set pre-trigger samples
def set_pre_trig_samples(self, samples): def set_pre_trig_samples(self, samples):
self.fmc_adc_csr.wr_reg(self.R_PRE_SAMPLES, samples) try:
self.fmc_adc_csr.set_reg('PRE_SAMPLES', samples)
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Set post-trigger samples # Set post-trigger samples
def set_post_trig_samples(self, samples): def set_post_trig_samples(self, samples):
self.fmc_adc_csr.wr_reg(self.R_POST_SAMPLES, samples) try:
self.fmc_adc_csr.set_reg('POST_SAMPLES', samples)
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Set number of shots # Set number of shots
def set_shots(self, shots): def set_shots(self, shots):
self.fmc_adc_csr.wr_reg(self.R_SHOTS, shots) try:
self.fmc_adc_csr.set_field('SHOTS', 'NB', shots)
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Get acquisition state machine status # Get acquisition state machine status
def get_acq_fsm_state(self): def get_acq_fsm_state(self):
state = (self.fmc_adc_csr.rd_reg(self.R_STA) & self.FSM_MASK) try:
#print("FSM state: %d")%state state = self.fmc_adc_csr.get_field('STA', 'FSM')
return self.FSM_STATES[state] #print "[FmcAdc100m] FSM state: %d" % state
return self.FSM_STATES[state]
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Get trigger position (DDR address) # Get trigger position (DDR address)
def get_trig_pos(self): def get_trig_pos(self):
return self.fmc_adc_csr.rd_reg(self.R_TRIG_POS) try:
return self.fmc_adc_csr.get_reg('TRIG_POS')
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Get number of acquired samples # Get number of acquired samples
def get_nb_samples(self): def get_nb_samples(self):
return self.fmc_adc_csr.rd_reg(self.R_SAMP_CNT) try:
return self.fmc_adc_csr.get_reg('SAMPLES_CNT')
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Get serdes sync status # Get serdes sync status
def get_serdes_sync_stat(self): def get_serdes_sync_stat(self):
return (self.fmc_adc_csr.rd_bit(self.R_STA, self.STA_SERDES_SYNCED)) try:
return self.fmc_adc_csr.get_field('STA', 'SERDES_SYNCED')
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Get ADC core status # Get ADC core status
def get_status(self): def get_status(self):
return self.fmc_adc_csr.rd_reg(self.R_STA) try:
return self.fmc_adc_csr.get_reg('STA')
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Get Channel current ADC value # Get Channel current ADC value
def get_current_adc_value(self, channel): def get_current_adc_value(self, channel):
addr = self.channel_addr(channel,self.R_CH1_VALUE) reg_name = 'CH'+str(self.channel_check(channel))+"_STA"
return self.fmc_adc_csr.rd_reg(addr) try:
return self.fmc_adc_csr.get_field(reg_name, 'VAL')
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Set channel gain and offset correction # Set channel gain and offset correction
def set_adc_gain_offset_corr(self, channel, gain, offset): def set_adc_gain_offset_corr(self, channel, gain, offset):
addr = self.channel_addr(channel,self.R_CH1_GAIN) try:
self.fmc_adc_csr.wr_reg(addr, gain) reg_name = 'CH'+str(self.channel_check(channel))+"_GAIN"
addr = self.channel_addr(channel,self.R_CH1_OFFSET) self.fmc_adc_csr.set_field(reg_name, 'VAL', gain)
self.fmc_adc_csr.wr_reg(addr, offset) reg_name = 'CH'+str(self.channel_check(channel))+"_OFFSET"
self.fmc_adc_csr.set_field(reg_name, 'VAL', offset)
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Get channel gain correction # Get channel gain correction
def get_adc_gain_corr(self, channel): def get_adc_gain_corr(self, channel):
addr = self.channel_addr(channel,self.R_CH1_GAIN) try:
return self.fmc_adc_csr.rd_reg(addr) reg_name = 'CH'+str(self.channel_check(channel))+"_GAIN"
self.fmc_adc_csr.set_field(reg_name, 'VAL', gain)
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Get channel offset correction # Get channel offset correction
def get_adc_offset_corr(self, channel): def get_adc_offset_corr(self, channel):
addr = self.channel_addr(channel,self.R_CH1_OFFSET) try:
return self.fmc_adc_csr.rd_reg(addr) reg_name = 'CH'+str(self.channel_check(channel))+"_OFFSET"
self.fmc_adc_csr.set_field(reg_name, 'VAL', offset)
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Print ADC core config/status # Print ADC core config/status registers
def print_adc_core_config(self): def print_adc_core_config(self):
print("\nADC core configuration/status") try:
self.fmc_adc_csr.rd_reg(0x04) # Workaround for first read at 0x00 bug self.fmc_adc_csr.print_reg_map()
for i in range(0,0x6C,4): except CSRDeviceOperationError as e:
print("%31s: 0x%.8X (%d)") % (self.FMC_CSR[i],self.fmc_adc_csr.rd_reg(i),self.fmc_adc_csr.rd_reg(i)) raise FmcAdc100mOperationError(e)
# Print Si570 config # Print Si570 config
def print_si570_config(self): def print_si570_config(self):
print("\nPrint Si570 configuration") try:
print("RFREQ : %3.28f") % self.si570.get_rfreq() print("\nPrint Si570 configuration")
print("N1 : %d") % self.si570.get_n1_div() print("RFREQ : %3.28f") % self.si570.get_rfreq()
print("HS_DIV : %d") % self.si570.get_hs_div() print("N1 : %d") % self.si570.get_n1_div()
print("HS_DIV : %d") % self.si570.get_hs_div()
except Si57xOperationError as e:
raise FmcAdc100mOperationError(e)
# Get Si570 config # Get Si570 config
def get_si570_config(self): def get_si570_config(self):
return self.si570.get_rfreq(), self.si570.get_n1_div(), self.si570.get_hs_div() try:
""" return self.si570.get_rfreq(), self.si570.get_n1_div(), self.si570.get_hs_div()
config = [] except Si57xOperationError as e:
config.append(self.si570.get_rfreq()) raise FmcAdc100mOperationError(e)
config.append(self.si570.get_n1_div())
config.append(self.si570.get_hs_div())
return config
"""
# Get Si570 raw config (hex value of the I2C registers in a table) # Get Si570 raw config (hex value of the I2C registers in a table)
def get_si570_raw_config(self): def get_si570_raw_config(self):
return self.si570.get_raw_config() try:
return self.si570.get_raw_config()
except Si57xOperationError as e:
raise FmcAdc100mOperationError(e)
test/fmcadc100m14b4cha/python/test01.py
View file @ c48ae8d9
...@@ -58,9 +58,6 @@ def main (default_directory='.'): ...@@ -58,9 +58,6 @@ def main (default_directory='.'):
except FmcAdc100mOperationError as e: except FmcAdc100mOperationError as e:
raise PtsCritical("Mezzanine init failed, test stopped: %s" % e) raise PtsCritical("Mezzanine init failed, test stopped: %s" % e)
# Read unique ID and print to log # Read unique ID and print to log
unique_id = fmc.get_unique_id() unique_id = fmc.get_unique_id()
if(unique_id == -1): if(unique_id == -1):
......
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