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FMC ADC 100M 14b 4cha - Testing
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FMC ADC 100M 14b 4cha - Testing
Commits
c48ae8d9
Commit
c48ae8d9
authored
May 11, 2012
by
Matthieu Cattin
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fmc_adc: Exception handling added, common modules interface updated.
Most of the function still needs to be tested.
parent
5aae3b2f
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2 changed files
with
296 additions
and
214 deletions
+296
-214
fmc_adc.py
test/fmcadc100m14b4cha/python/fmc_adc.py
+296
-211
test01.py
test/fmcadc100m14b4cha/python/test01.py
+0
-3
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test/fmcadc100m14b4cha/python/fmc_adc.py
View file @
c48ae8d9
...
...
@@ -157,8 +157,6 @@ class CFmcAdc100m:
CTL_MASK = 0xEC
FSM_CMD_MASK = 0x00000003
FSM_CMD_START = 0x1
FSM_CMD_STOP = 0x2
STA_FSM = 0
STA_SERDES_SYNCED = 4
...
...
@@ -166,6 +164,8 @@ class CFmcAdc100m:
FSM_MASK = 0x00000007
"""
FSM_CMD_START
=
0x1
FSM_CMD_STOP
=
0x2
FSM_STATES
=
[
'N/A'
,
'IDLE'
,
'PRE_TRIG'
,
'WAIT_TRIG'
,
'POST_TRIG'
,
'DECR_SHOT'
,
'N/A'
,
'others'
]
...
...
@@ -190,6 +190,8 @@ class CFmcAdc100m:
'100mV'
:{
'offset'
:[
0x0
,
0x0
,
0x0
,
0x0
],
'gain'
:[
0x8000
,
0x8000
,
0x8000
,
0x8000
]}}
WAIT_TIME_OUT
=
2
def
channel_addr
(
self
,
channel
,
reg
):
if
(
channel
<
1
or
channel
>
4
):
...
...
@@ -202,39 +204,42 @@ class CFmcAdc100m:
def
__init__
(
self
,
bus
):
self
.
bus
=
bus
# Objects declaration
try
:
# Objects declaration
self
.
fmc_sys_i2c
=
COpenCoresI2C
(
self
.
bus
,
self
.
FMC_SYS_I2C_ADDR
,
249
)
self
.
fmc_i2c
=
COpenCoresI2C
(
self
.
bus
,
self
.
FMC_I2C_ADDR
,
249
)
except
I2CDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
self
.
eeprom_24aa64
=
C24AA64
(
self
.
fmc_sys_i2c
,
self
.
EEPROM_ADDR
)
self
.
si570
=
CSi57x
(
self
.
fmc_i2c
,
self
.
SI570_ADDR
)
self
.
fmc_onewire
=
COpenCoresOneWire
(
self
.
bus
,
self
.
FMC_ONEWIRE_ADDR
,
624
,
124
)
self
.
ds18b20
=
CDS18B20
(
self
.
fmc_onewire
,
0
)
self
.
eeprom_24aa64
=
C24AA64
(
self
.
fmc_sys_i2c
,
self
.
EEPROM_ADDR
)
self
.
si570
=
CSi57x
(
self
.
fmc_i2c
,
self
.
SI570_ADDR
)
self
.
fmc_onewire
=
COpenCoresOneWire
(
self
.
bus
,
self
.
FMC_ONEWIRE_ADDR
,
624
,
124
)
self
.
ds18b20
=
CDS18B20
(
self
.
fmc_onewire
,
0
)
self
.
fmc_adc_csr
=
CCSR
(
self
.
bus
,
self
.
FMC_CSR_ADDR
,
FMCADC100M_CSR
)
self
.
fmc_spi
=
COpenCoresSPI
(
self
.
bus
,
self
.
FMC_SPI_ADDR
,
self
.
FMC_SPI_DIV
)
self
.
adc_cfg
=
CLTC217x
(
self
.
fmc_spi
,
self
.
FMC_SPI_SS
[
'ADC'
])
self
.
dac_ch
=
[]
self
.
dac_ch
.
append
(
CMAX5442
(
self
.
fmc_spi
,
self
.
FMC_SPI_SS
[
'DAC1'
]))
self
.
dac_ch
.
append
(
CMAX5442
(
self
.
fmc_spi
,
self
.
FMC_SPI_SS
[
'DAC2'
]))
self
.
dac_ch
.
append
(
CMAX5442
(
self
.
fmc_spi
,
self
.
FMC_SPI_SS
[
'DAC3'
]))
self
.
dac_ch
.
append
(
CMAX5442
(
self
.
fmc_spi
,
self
.
FMC_SPI_SS
[
'DAC4'
]))
self
.
fmc_spi
=
COpenCoresSPI
(
self
.
bus
,
self
.
FMC_SPI_ADDR
,
self
.
FMC_SPI_DIV
)
self
.
adc_cfg
=
CLTC217x
(
self
.
fmc_spi
,
self
.
FMC_SPI_SS
[
'ADC'
])
self
.
dac_ch
[
1
]
=
CMAX5442
(
self
.
fmc_spi
,
self
.
FMC_SPI_SS
[
'DAC1'
])
self
.
dac_ch
[
2
]
=
CMAX5442
(
self
.
fmc_spi
,
self
.
FMC_SPI_SS
[
'DAC2'
])
self
.
dac_ch
[
3
]
=
CMAX5442
(
self
.
fmc_spi
,
self
.
FMC_SPI_SS
[
'DAC3'
])
self
.
dac_ch
[
4
]
=
CMAX5442
(
self
.
fmc_spi
,
self
.
FMC_SPI_SS
[
'DAC4'
])
self
.
fmc_adc_csr
=
CCSR
(
self
.
bus
,
self
.
FMC_CSR_ADDR
,
FMCADC100M_CSR
)
# Set channels gain to 1
self
.
fmc_adc_csr
.
set_field
(
'CH1_GAIN'
,
'VAL'
,
0x8000
)
self
.
fmc_adc_csr
.
set_field
(
'CH2_GAIN'
,
'VAL'
,
0x8000
)
self
.
fmc_adc_csr
.
set_field
(
'CH3_GAIN'
,
'VAL'
,
0x8000
)
self
.
fmc_adc_csr
.
set_field
(
'CH4_GAIN'
,
'VAL'
,
0x8000
)
# Set channels gain to 1
self
.
fmc_adc_csr
.
set_field
(
'CH1_GAIN'
,
'VAL'
,
0x8000
)
self
.
fmc_adc_csr
.
set_field
(
'CH2_GAIN'
,
'VAL'
,
0x8000
)
self
.
fmc_adc_csr
.
set_field
(
'CH3_GAIN'
,
'VAL'
,
0x8000
)
self
.
fmc_adc_csr
.
set_field
(
'CH4_GAIN'
,
'VAL'
,
0x8000
)
# Enable mezzanine clock and offset DACs
self
.
fmc_adc_csr
.
set_field
(
'CTL'
,
'FMC_CLK_OE'
,
1
)
self
.
fmc_adc_csr
.
set_field
(
'CTL'
,
'OFFSET_DAC_CLR_N'
,
1
)
# Enable mezzanine clock and offset DACs
self
.
en_sampfreq
(
)
self
.
dc_offset_reset
(
)
# Disable ADC test pattern
self
.
adc_cfg
.
dis_testpat
()
# Disable ADC test pattern
self
.
adc_cfg
.
dis_testpat
()
except
(
I2CDeviceOperationError
,
CSRDeviceOperationError
,
LTC217xOperationError
)
as
e
:
raise
FmcAdc100mOperationError
(
e
)
def
channel_check
(
self
,
channel
):
...
...
@@ -367,18 +372,20 @@ class CFmcAdc100m:
raise
FmcAdc100mOperationError
(
e
)
# Set channel DC offset (MAX5442 DAC)
def
set_dc_offset
(
self
,
channel
,
offset
):
def
set_dc_offset
(
self
,
channel
,
value
):
ch
=
self
.
channel_check
(
channel
)
try
:
self
.
dac_ch
[
ch
]
.
set_value
(
offset
)
self
.
dac_ch
[
ch
-
1
]
.
set_value
(
value
)
except
MAX5442OperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Save a copy of the correction data locally
def
set_dac_corr
(
self
,
corr_data
):
self
.
dac_corr_data
=
corr_data
# Apply correction factors to DAC data
def
dac_apply_corr
(
self
,
value
,
gain_corr
,
offset_corr
):
#print "dac_apply_corr: value:%d offset:%d gain:%d"%(value, hex2signed(offset_corr), gain_corr)
#print "
[FmcAdc100m]
dac_apply_corr: value:%d offset:%d gain:%d"%(value, hex2signed(offset_corr), gain_corr)
value_corr
=
(((((
value
-
0x8000
)
+
hex2signed
(
offset_corr
))
<<
15
)
*
gain_corr
)
>>
30
)
+
0x8000
return
value_corr
...
...
@@ -386,103 +393,132 @@ class CFmcAdc100m:
# value = DAC unsigned integer value
def
set_dc_offset_corrected
(
self
,
channel
,
in_range
,
value
,
print_value
=
False
):
uncorr_value
=
value
value
=
self
.
dac_apply_corr
(
value
,
self
.
dac_corr_data
[
in_range
][
'gain'
][
channel
-
1
],
self
.
dac_corr_data
[
in_range
][
'offset'
][
channel
-
1
])
value
=
self
.
dac_apply_corr
(
value
,
self
.
dac_corr_data
[
in_range
][
'gain'
][
channel
-
1
],
self
.
dac_corr_data
[
in_range
][
'offset'
][
channel
-
1
])
if
(
print_value
):
print
(
'CH
%
d DAC uncorrected value: 0x
%.4
X'
)
%
(
channel
,
uncorr_value
)
print
(
'CH
%
d DAC corrected value : 0x
%.4
X'
)
%
(
channel
,
value
)
if
(
1
==
channel
):
self
.
dac_ch1
.
set_offset
(
value
)
elif
(
2
==
channel
):
self
.
dac_ch2
.
set_offset
(
value
)
elif
(
3
==
channel
):
self
.
dac_ch3
.
set_offset
(
value
)
elif
(
4
==
channel
):
self
.
dac_ch4
.
set_offset
(
value
)
else
:
raise
Exception
(
'Unsupported parameter, channel number from 1 to 4'
)
print
(
'[FmcAdc100m] CH
%
d DAC uncorrected value: 0x
%.4
X'
)
%
(
channel
,
uncorr_value
)
print
(
'[FmcAdc100m] CH
%
d DAC corrected value : 0x
%.4
X'
)
%
(
channel
,
value
)
ch
=
self
.
channel_check
(
channel
)
try
:
self
.
dac_ch
[
ch
-
1
]
.
set_value
(
value
)
except
MAX5442OperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Reset DC offset DACs
def
dc_offset_reset
(
self
):
reg
=
self
.
fmc_adc_csr
.
rd_reg
(
self
.
R_CTL
)
#print("R_CTL:%.8X")%reg
reg
&=
~
(
1
<<
self
.
CTL_OFFSET_DAC_CLR_N
)
#print("R_CTL:%.8X")%reg
self
.
fmc_adc_csr
.
wr_reg
(
self
.
R_CTL
,
reg
)
reg
|=
(
1
<<
self
.
CTL_OFFSET_DAC_CLR_N
)
#print("R_CTL:%.8X")%reg
self
.
fmc_adc_csr
.
wr_reg
(
self
.
R_CTL
,
reg
)
try
:
self
.
fmc_adc_csr
.
set_field
(
'CTL'
,
'OFFSET_DAC_CLR_N'
,
0
)
self
.
fmc_adc_csr
.
set_field
(
'CTL'
,
'OFFSET_DAC_CLR_N'
,
1
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Set 50ohms termination
# channel: integer (1 to 4)
# state: string ('ON' or 'OFF')
def
set_input_term
(
self
,
channel
,
state
):
addr
=
self
.
channel_addr
(
channel
,
self
.
R_CH1_SSR
)
reg
=
self
.
fmc_adc_csr
.
rd_reg
(
addr
)
#print("ssr reg ch%1d: %.8X") %(channel, reg)
if
(
'ON'
==
state
):
reg
|=
self
.
IN_TERM
elif
(
'OFF'
==
state
):
reg
&=
~
(
self
.
IN_TERM
)
else
:
raise
Exception
(
'Unsupported parameter, should be ON or OFF.'
)
#print("ssr reg ch%1d: %.8X") %(channel, reg)
self
.
fmc_adc_csr
.
wr_reg
(
addr
,
reg
)
#print("ssr reg ch%1d: %.8X") %(channel, self.fmc_adc_csr.rd_reg(addr))
reg_name
=
'CH'
+
str
(
self
.
channel_check
(
channel
))
+
"_CTL"
try
:
# Read channel control register
reg_val
=
self
.
fmc_adc_csr
.
get_reg
(
reg_name
)
#print "[FmcAdc100m] ssr reg ch%1d: %.8X" % (channel, reg_val)
if
(
'ON'
==
state
):
reg_val
|=
self
.
IN_TERM
elif
(
'OFF'
==
state
):
reg_val
&=
~
(
self
.
IN_TERM
)
else
:
raise
FmcAdc100mOperationError
(
"Unsupported state parameter (
%
s), should be ON or OFF."
%
state
)
#print "[FmcAdc100m] ssr reg ch%1d: %.8X" % (channel, reg_vale)
self
.
fmc_adc_csr
.
set_reg
(
reg_name
,
reg_val
)
#print "[FmcAdc100m] ssr reg ch%1d: %.8X" % (channel, self.fmc_adc_csr.get_reg(reg_name))
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Set decimation factor
def
set_decimation
(
self
,
factor
):
self
.
fmc_adc_csr
.
wr_reg
(
self
.
R_SRATE
,
factor
)
try
:
self
.
fmc_adc_csr
.
set_field
(
'SR'
,
'DECI'
,
factor
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Get decimation factor
def
get_decimation
(
self
):
return
self
.
fmc_adc_csr
.
rd_reg
(
self
.
R_SRATE
)
try
:
return
self
.
fmc_adc_csr
.
get_field
(
'SR'
,
'DECI'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Enable Sampling clock (Si570)
def
en_sampfreq
(
self
):
self
.
fmc_adc_csr
.
wr_bit
(
self
.
R_CTL
,
self
.
CTL_CLK_EN
,
1
)
try
:
self
.
fmc_adc_csr
.
set_field
(
'CTL'
,
'FMC_CLK_OE'
,
1
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Disable Sampling clock (Si570)
def
dis_sampfreq
(
self
):
self
.
fmc_adc_csr
.
wr_bit
(
self
.
R_CTL
,
self
.
CTL_CLK_EN
,
0
)
try
:
self
.
fmc_adc_csr
.
set_field
(
'CTL'
,
'FMC_CLK_OE'
,
0
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Serdes calibration
# Serdes
'manual'
calibration
def
serdes_sync
(
self
):
print
(
"
\n
Start serdes synchro"
)
pattern
=
0x3456
self
.
adc_cfg
.
set_testpat
(
pattern
)
self
.
adc_cfg
.
en_testpat
()
print
(
"Test pattern :
%.4
X"
)
%
self
.
adc_cfg
.
get_testpat
()
print
(
"Test pattern status :
%.1
X"
)
%
self
.
adc_cfg
.
get_testpat_stat
()
while
(
pattern
!=
self
.
fmc_adc_csr
.
rd_reg
(
self
.
R_CH1_VALUE
)):
print
(
"CH1 value :
%.4
X"
)
%
self
.
fmc_adc_csr
.
rd_reg
(
self
.
R_CH1_VALUE
)
print
(
"CH2 value :
%.4
X"
)
%
self
.
fmc_adc_csr
.
rd_reg
(
self
.
R_CH2_VALUE
)
print
(
"CH3 value :
%.4
X"
)
%
self
.
fmc_adc_csr
.
rd_reg
(
self
.
R_CH3_VALUE
)
print
(
"CH4 value :
%.4
X"
)
%
self
.
fmc_adc_csr
.
rd_reg
(
self
.
R_CH4_VALUE
)
self
.
fmc_adc_csr
.
wr_bit
(
self
.
R_CTL
,
self
.
CTL_BSLIP
,
1
)
time
.
sleep
(
.1
)
self
.
adc_cfg
.
dis_testpat
()
print
(
"Serdes synced!"
)
try
:
print
"
\n
[FmcAdc100m] Start serdes synchro"
pattern
=
0x3456
self
.
adc_cfg
.
set_testpat
(
pattern
)
self
.
adc_cfg
.
en_testpat
()
print
"[FmcAdc100m] Test pattern :
%.4
X"
%
self
.
adc_cfg
.
get_testpat
()
print
"[FmcAdc100m] Test pattern status :
%.1
X"
%
self
.
adc_cfg
.
get_testpat_stat
()
while
(
pattern
!=
self
.
fmc_adc_csr
.
get_field
(
'CH1_STA'
,
'VAL'
)):
for
ch
in
range
(
1
,
5
,
1
):
print
"[FmcAdc100m] CH
%
d value :
%.4
X"
%
(
ch
,
self
.
fmc_adc_csr
.
get_reg
(
'CH'
+
str
(
ch
)
+
'_STA'
,
'VAL'
))
self
.
fmc_adc_csr
.
set_field
(
'CTL'
,
'MAN_BITSLIP'
,
1
)
time
.
sleep
(
.1
)
self
.
adc_cfg
.
dis_testpat
()
print
(
"[FmcAdc100m] Serdes synced!"
)
except
(
LTC217xOperationError
,
CSRDeviceOperationError
)
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Set test pattern
def
set_testpat
(
self
,
pattern
):
self
.
adc_cfg
.
set_testpat
(
pattern
)
try
:
self
.
adc_cfg
.
set_testpat
(
pattern
)
except
LTC217xOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Get test pattern
def
get_testpat
(
self
):
return
self
.
adc_cfg
.
get_testpat
()
try
:
return
self
.
adc_cfg
.
get_testpat
()
except
LTC217xOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Enable test pattern
def
testpat_en
(
self
,
pattern
):
self
.
adc_cfg
.
set_testpat
(
pattern
)
self
.
adc_cfg
.
en_testpat
()
try
:
self
.
adc_cfg
.
set_testpat
(
pattern
)
self
.
adc_cfg
.
en_testpat
()
except
LTC217xOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Disable test pattern
def
testpat_dis
(
self
):
self
.
adc_cfg
.
dis_testpat
()
try
:
self
.
adc_cfg
.
dis_testpat
()
except
LTC217xOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Print adc config regs
def
print_adc_regs
(
self
):
self
.
adc_cfg
.
print_regs
()
try
:
self
.
adc_cfg
.
print_regs
()
except
LTC217xOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Set sampling frequency
# Set sampling frequency
(Si570)
#def set_sampfreq(self, freq):
# Get sampling frequency
...
...
@@ -491,205 +527,254 @@ class CFmcAdc100m:
#def get_channel_config(self, channel):
# Set trigger configuration
def
set_trig_config
(
self
,
hw_sel
,
ext_pol
,
hw_en
,
sw_en
,
int_sel
,
int_thres
,
delay
):
# Hardware trigger select (ext/int)
self
.
fmc_adc_csr
.
wr_bit
(
self
.
R_TRIG_CFG
,
self
.
TRIG_CFG_HW_SEL
,
hw_sel
)
# External trigger pulse polarity
self
.
fmc_adc_csr
.
wr_bit
(
self
.
R_TRIG_CFG
,
self
.
TRIG_CFG_EXT_POL
,
ext_pol
)
# Hardware trigger enable
self
.
fmc_adc_csr
.
wr_bit
(
self
.
R_TRIG_CFG
,
self
.
TRIG_CFG_HW_EN
,
hw_en
)
# Software trigger enable
self
.
fmc_adc_csr
.
wr_bit
(
self
.
R_TRIG_CFG
,
self
.
TRIG_CFG_SW_EN
,
sw_en
)
# Internal trigger channel select (1 to 4)
reg
=
self
.
fmc_adc_csr
.
rd_reg
(
self
.
R_TRIG_CFG
)
reg
&=
self
.
INT_SEL_MASK
reg
+=
(
int_sel
<<
self
.
TRIG_CFG_INT_SEL
)
self
.
fmc_adc_csr
.
wr_reg
(
self
.
R_TRIG_CFG
,
reg
)
# Internal trigger threshold
reg
=
self
.
fmc_adc_csr
.
rd_reg
(
self
.
R_TRIG_CFG
)
reg
&=
self
.
INT_THRES_MASK
reg
+=
(
int_thres
<<
self
.
TRIG_CFG_INT_THRES
)
self
.
fmc_adc_csr
.
wr_reg
(
self
.
R_TRIG_CFG
,
reg
)
# Trigger delay (in sampling clock ticks)
self
.
fmc_adc_csr
.
wr_reg
(
self
.
R_TRIG_DLY
,
delay
)
def
set_trig_config
(
self
,
hw_sel
,
hw_pol
,
hw_en
,
sw_en
,
channel
,
int_thres
,
delay
):
ch
=
self
.
channel_check
(
channel
)
try
:
# Hardware trigger select (ext/int)
self
.
fmc_adc_csr
.
set_field
(
'TRIG_CFG'
,
'HW_TRIG_SEL'
,
hw_sel
)
# Hardware trigger polarity
self
.
fmc_adc_csr
.
set_field
(
'TRIG_CFG'
,
'HW_TRIG_POL'
,
hw_pol
)
# Hardware trigger enable
self
.
fmc_adc_csr
.
set_field
(
'TRIG_CFG'
,
'HW_TRIG_EN'
,
hw_en
)
# Software trigger enable
self
.
fmc_adc_csr
.
set_field
(
'TRIG_CFG'
,
'SW_TRIG_EN'
,
sw_en
)
# Internal trigger channel select (1 to 4)
self
.
fmc_adc_csr
.
set_field
(
'TRIG_CFG'
,
'INT_TRIG_SEL'
,
ch
-
1
)
# Internal trigger threshold
self
.
fmc_adc_csr
.
set_field
(
'TRIG_CFG'
,
'INT_TRIG_THRES'
,
int_thres
)
# Trigger delay (in sampling clock ticks)
self
.
fmc_adc_csr
.
set_field
(
'TRIG_DLY'
,
'TRIG_DLY'
,
delay
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Get trigger configuration
# Internal trigger
def
set_int_trig
(
self
,
channel
,
polarity
,
threshold
):
# Software trigger disable
self
.
fmc_adc_csr
.
wr_bit
(
self
.
R_TRIG_CFG
,
self
.
TRIG_CFG_SW_EN
,
0
)
# Select internal hardware trigger
self
.
fmc_adc_csr
.
wr_bit
(
self
.
R_TRIG_CFG
,
self
.
TRIG_CFG_HW_SEL
,
0
)
# Trigger polarity
self
.
fmc_adc_csr
.
wr_bit
(
self
.
R_TRIG_CFG
,
self
.
TRIG_CFG_EXT_POL
,
polarity
)
# Internal trigger channel select (1 to 4)
reg
=
self
.
fmc_adc_csr
.
rd_reg
(
self
.
R_TRIG_CFG
)
reg
&=
self
.
INT_SEL_MASK
reg
+=
(
int_sel
<<
self
.
TRIG_CFG_INT_SEL
)
self
.
fmc_adc_csr
.
wr_reg
(
self
.
R_TRIG_CFG
,
reg
)
# Internal trigger threshold
reg
=
self
.
fmc_adc_csr
.
rd_reg
(
self
.
R_TRIG_CFG
)
reg
&=
self
.
INT_THRES_MASK
reg
+=
(
int_thres
<<
self
.
TRIG_CFG_INT_THRES
)
self
.
fmc_adc_csr
.
wr_reg
(
self
.
R_TRIG_CFG
,
reg
)
# Hardware trigger enable
self
.
fmc_adc_csr
.
wr_bit
(
self
.
R_TRIG_CFG
,
self
.
TRIG_CFG_HW_EN
,
1
)
ch
=
self
.
channel_check
(
channel
)
try
:
# Software trigger disable
self
.
fmc_adc_csr
.
set_field
(
'TRIG_CFG'
,
'SW_TRIG_EN'
,
0
)
# Select internal hardware trigger
self
.
fmc_adc_csr
.
set_field
(
'TRIG_CFG'
,
'HW_TRIG_SEL'
,
0
)
# Trigger polarity
self
.
fmc_adc_csr
.
set_field
(
'TRIG_CFG'
,
'HW_TRIG_POL'
,
polarity
)
# Internal trigger channel select (1 to 4)
self
.
fmc_adc_csr
.
set_field
(
'TRIG_CFG'
,
'INT_TRIG_SEL'
,
ch
-
1
)
# Internal trigger threshold
self
.
fmc_adc_csr
.
set_field
(
'TRIG_CFG'
,
'INT_TRIG_THRES'
,
threshold
)
# Hardware trigger enable
self
.
fmc_adc_csr
.
set_field
(
'TRIG_CFG'
,
'HW_TRIG_EN'
,
1
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# External trigger
def
set_ext_trig
(
self
,
polarity
):
# Software trigger disable
self
.
fmc_adc_csr
.
wr_bit
(
self
.
R_TRIG_CFG
,
self
.
TRIG_CFG_SW_EN
,
0
)
# Select external hardware trigger
self
.
fmc_adc_csr
.
wr_bit
(
self
.
R_TRIG_CFG
,
self
.
TRIG_CFG_HW_SEL
,
1
)
# Trigger polarity
self
.
fmc_adc_csr
.
wr_bit
(
self
.
R_TRIG_CFG
,
self
.
TRIG_CFG_EXT_POL
,
polarity
)
# Hardware trigger enable
self
.
fmc_adc_csr
.
wr_bit
(
self
.
R_TRIG_CFG
,
self
.
TRIG_CFG_HW_EN
,
1
)
try
:
# Software trigger disable
self
.
fmc_adc_csr
.
set_field
(
'TRIG_CFG'
,
'SW_TRIG_EN'
,
0
)
# Select external hardware trigger
self
.
fmc_adc_csr
.
set_field
(
'TRIG_CFG'
,
'HW_TRIG_SEL'
,
1
)
# Trigger polarity
self
.
fmc_adc_csr
.
set_field
(
'TRIG_CFG'
,
'HW_TRIG_POL'
,
polarity
)
# Hardware trigger enable
self
.
fmc_adc_csr
.
set_field
(
'TRIG_CFG'
,
'HW_TRIG_EN'
,
1
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Software trigger
def
set_soft_trig
(
self
):
# Hardware trigger disable
self
.
fmc_adc_csr
.
wr_bit
(
self
.
R_TRIG_CFG
,
self
.
TRIG_CFG_HW_EN
,
0
)
# Software trigger enable
self
.
fmc_adc_csr
.
wr_bit
(
self
.
R_TRIG_CFG
,
self
.
TRIG_CFG_SW_EN
,
1
)
try
:
# Hardware trigger disable
self
.
fmc_adc_csr
.
set_field
(
'TRIG_CFG'
,
'HW_TRIG_EN'
,
0
)
# Software trigger enable
self
.
fmc_adc_csr
.
set_field
(
'TRIG_CFG'
,
'SW_TRIG_EN'
,
1
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Trigger delay
def
set_trig_delay
(
self
,
delay
):
# Trigger delay (in sampling clock ticks)
self
.
fmc_adc_csr
.
wr_reg
(
self
.
R_TRIG_DLY
,
delay
)
try
:
# Trigger delay (in sampling clock ticks)
self
.
fmc_adc_csr
.
set_field
(
'TRIG_DLY'
,
'TRIG_DLY'
,
delay
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Enable test data
def
test_data_en
(
self
):
reg
=
self
.
fmc_adc_csr
.
rd_reg
(
self
.
R_CTL
)
print
(
"R_CTL:
%.8
X"
)
%
reg
reg
|=
((
1
<<
self
.
CTL_TEST_DATA_EN
)
&
self
.
CTL_MASK
)
print
(
"R_CTL:
%.8
X"
)
%
reg
self
.
fmc_adc_csr
.
wr_reg
(
self
.
R_CTL
,
reg
)
try
:
self
.
fmc_adc_csr
.
set_field
(
'CTL'
,
'TEST_DATA_EN'
,
1
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Disable test data
def
test_data_dis
(
self
):
reg
=
self
.
fmc_adc_csr
.
rd_reg
(
self
.
R_CTL
)
print
(
"R_CTL:
%.8
X"
)
%
reg
reg
&=
(
~
(
1
<<
self
.
CTL_TEST_DATA_EN
)
&
self
.
CTL_MASK
)
print
(
"R_CTL:
%.8
X"
)
%
reg
self
.
fmc_adc_csr
.
wr_reg
(
self
.
R_CTL
,
reg
)
try
:
self
.
fmc_adc_csr
.
set_field
(
'CTL'
,
'TEST_DATA_EN'
,
0
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Start acquisition
def
start_acq
(
self
):
# Wait for serdes to be synced
while
(
0
==
self
.
get_serdes_sync_stat
()):
print
'Wait for serdes to be synced'
time
.
sleep
(
.1
)
reg
=
self
.
fmc_adc_csr
.
rd_reg
(
self
.
R_CTL
)
reg
&=
~
self
.
FSM_CMD_MASK
reg
|=
((
self
.
FSM_CMD_START
<<
self
.
CTL_FSM_CMD
)
&
self
.
FSM_CMD_MASK
)
reg
&=
(
self
.
CTL_MASK
|
self
.
FSM_CMD_MASK
)
#print("R_CTL:%.8X")%reg
self
.
fmc_adc_csr
.
wr_reg
(
self
.
R_CTL
,
reg
)
try
:
# Wait for serdes to be synced
init_time
=
time
.
time
()
while
(
0
==
self
.
get_serdes_sync_stat
()):
if
(
time
.
time
()
-
init_time
)
>
self
.
WAIT_TIME_OUT
:
raise
FmcAdc100mOperationError
(
"Wait serdes sync timeout."
)
print
'[FmcAdc100m] Wait for serdes to be synced'
time
.
sleep
(
.1
)
self
.
fmc_adc_csr
.
set_field
(
'CTL'
,
'FSM_CMD'
,
self
.
FSM_CMD_START
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Stop acquisition
def
stop_acq
(
self
):
reg
=
self
.
fmc_adc_csr
.
rd_reg
(
self
.
R_CTL
)
reg
&=
~
self
.
FSM_CMD_MASK
reg
|=
((
self
.
FSM_CMD_STOP
<<
self
.
CTL_FSM_CMD
)
&
self
.
FSM_CMD_MASK
)
#print("R_CTL:%.8X")%reg
self
.
fmc_adc_csr
.
wr_reg
(
self
.
R_CTL
,
reg
)
try
:
self
.
fmc_adc_csr
.
set_field
(
'CTL'
,
'FSM_CMD'
,
self
.
FSM_CMD_STOP
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Software trigger
def
sw_trig
(
self
):
while
(
'WAIT_TRIG'
!=
self
.
get_acq_fsm_state
()):
#print self.get_acq_fsm_state()
#time.sleep(.001)
pass
self
.
fmc_adc_csr
.
wr_reg
(
self
.
R_SW_TRIG
,
0xFFFFFFFF
)
try
:
init_time
=
time
.
time
()
while
(
'WAIT_TRIG'
!=
self
.
get_acq_fsm_state
()):
if
(
time
.
time
()
-
init_time
)
>
self
.
WAIT_TIME_OUT
:
raise
FmcAdc100mOperationError
(
"Wait trigger timeout."
)
#print self.get_acq_fsm_state()
#time.sleep(.001)
self
.
fmc_adc_csr
.
set_reg
(
'SW_TRIG'
,
0xFFFFFFFF
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Software trigger without wait on WAIT_TRIG state
def
sw_trig_no_wait
(
self
):
self
.
fmc_adc_csr
.
wr_reg
(
self
.
R_SW_TRIG
,
0xFFFFFFFF
)
try
:
self
.
fmc_adc_csr
.
set_reg
(
'SW_TRIG'
,
0xFFFFFFFF
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Set pre-trigger samples
def
set_pre_trig_samples
(
self
,
samples
):
self
.
fmc_adc_csr
.
wr_reg
(
self
.
R_PRE_SAMPLES
,
samples
)
try
:
self
.
fmc_adc_csr
.
set_reg
(
'PRE_SAMPLES'
,
samples
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Set post-trigger samples
def
set_post_trig_samples
(
self
,
samples
):
self
.
fmc_adc_csr
.
wr_reg
(
self
.
R_POST_SAMPLES
,
samples
)
try
:
self
.
fmc_adc_csr
.
set_reg
(
'POST_SAMPLES'
,
samples
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Set number of shots
def
set_shots
(
self
,
shots
):
self
.
fmc_adc_csr
.
wr_reg
(
self
.
R_SHOTS
,
shots
)
try
:
self
.
fmc_adc_csr
.
set_field
(
'SHOTS'
,
'NB'
,
shots
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Get acquisition state machine status
def
get_acq_fsm_state
(
self
):
state
=
(
self
.
fmc_adc_csr
.
rd_reg
(
self
.
R_STA
)
&
self
.
FSM_MASK
)
#print("FSM state: %d")%state
return
self
.
FSM_STATES
[
state
]
try
:
state
=
self
.
fmc_adc_csr
.
get_field
(
'STA'
,
'FSM'
)
#print "[FmcAdc100m] FSM state: %d" % state
return
self
.
FSM_STATES
[
state
]
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Get trigger position (DDR address)
def
get_trig_pos
(
self
):
return
self
.
fmc_adc_csr
.
rd_reg
(
self
.
R_TRIG_POS
)
try
:
return
self
.
fmc_adc_csr
.
get_reg
(
'TRIG_POS'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Get number of acquired samples
def
get_nb_samples
(
self
):
return
self
.
fmc_adc_csr
.
rd_reg
(
self
.
R_SAMP_CNT
)
try
:
return
self
.
fmc_adc_csr
.
get_reg
(
'SAMPLES_CNT'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Get serdes sync status
def
get_serdes_sync_stat
(
self
):
return
(
self
.
fmc_adc_csr
.
rd_bit
(
self
.
R_STA
,
self
.
STA_SERDES_SYNCED
))
try
:
return
self
.
fmc_adc_csr
.
get_field
(
'STA'
,
'SERDES_SYNCED'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Get ADC core status
def
get_status
(
self
):
return
self
.
fmc_adc_csr
.
rd_reg
(
self
.
R_STA
)
try
:
return
self
.
fmc_adc_csr
.
get_reg
(
'STA'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Get Channel current ADC value
def
get_current_adc_value
(
self
,
channel
):
addr
=
self
.
channel_addr
(
channel
,
self
.
R_CH1_VALUE
)
return
self
.
fmc_adc_csr
.
rd_reg
(
addr
)
reg_name
=
'CH'
+
str
(
self
.
channel_check
(
channel
))
+
"_STA"
try
:
return
self
.
fmc_adc_csr
.
get_field
(
reg_name
,
'VAL'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Set channel gain and offset correction
def
set_adc_gain_offset_corr
(
self
,
channel
,
gain
,
offset
):
addr
=
self
.
channel_addr
(
channel
,
self
.
R_CH1_GAIN
)
self
.
fmc_adc_csr
.
wr_reg
(
addr
,
gain
)
addr
=
self
.
channel_addr
(
channel
,
self
.
R_CH1_OFFSET
)
self
.
fmc_adc_csr
.
wr_reg
(
addr
,
offset
)
try
:
reg_name
=
'CH'
+
str
(
self
.
channel_check
(
channel
))
+
"_GAIN"
self
.
fmc_adc_csr
.
set_field
(
reg_name
,
'VAL'
,
gain
)
reg_name
=
'CH'
+
str
(
self
.
channel_check
(
channel
))
+
"_OFFSET"
self
.
fmc_adc_csr
.
set_field
(
reg_name
,
'VAL'
,
offset
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Get channel gain correction
def
get_adc_gain_corr
(
self
,
channel
):
addr
=
self
.
channel_addr
(
channel
,
self
.
R_CH1_GAIN
)
return
self
.
fmc_adc_csr
.
rd_reg
(
addr
)
try
:
reg_name
=
'CH'
+
str
(
self
.
channel_check
(
channel
))
+
"_GAIN"
self
.
fmc_adc_csr
.
set_field
(
reg_name
,
'VAL'
,
gain
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Get channel offset correction
def
get_adc_offset_corr
(
self
,
channel
):
addr
=
self
.
channel_addr
(
channel
,
self
.
R_CH1_OFFSET
)
return
self
.
fmc_adc_csr
.
rd_reg
(
addr
)
try
:
reg_name
=
'CH'
+
str
(
self
.
channel_check
(
channel
))
+
"_OFFSET"
self
.
fmc_adc_csr
.
set_field
(
reg_name
,
'VAL'
,
offset
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Print ADC core config/status
# Print ADC core config/status
registers
def
print_adc_core_config
(
self
):
print
(
"
\n
ADC core configuration/status"
)
self
.
fmc_adc_csr
.
rd_reg
(
0x04
)
# Workaround for first read at 0x00 bug
for
i
in
range
(
0
,
0x6C
,
4
)
:
print
(
"
%31
s: 0x
%.8
X (
%
d)"
)
%
(
self
.
FMC_CSR
[
i
],
self
.
fmc_adc_csr
.
rd_reg
(
i
),
self
.
fmc_adc_csr
.
rd_reg
(
i
)
)
try
:
self
.
fmc_adc_csr
.
print_reg_map
()
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Print Si570 config
def
print_si570_config
(
self
):
print
(
"
\n
Print Si570 configuration"
)
print
(
"RFREQ :
%3.28
f"
)
%
self
.
si570
.
get_rfreq
()
print
(
"N1 :
%
d"
)
%
self
.
si570
.
get_n1_div
()
print
(
"HS_DIV :
%
d"
)
%
self
.
si570
.
get_hs_div
()
try
:
print
(
"
\n
Print Si570 configuration"
)
print
(
"RFREQ :
%3.28
f"
)
%
self
.
si570
.
get_rfreq
()
print
(
"N1 :
%
d"
)
%
self
.
si570
.
get_n1_div
()
print
(
"HS_DIV :
%
d"
)
%
self
.
si570
.
get_hs_div
()
except
Si57xOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Get Si570 config
def
get_si570_config
(
self
):
return
self
.
si570
.
get_rfreq
(),
self
.
si570
.
get_n1_div
(),
self
.
si570
.
get_hs_div
()
"""
config = []
config.append(self.si570.get_rfreq())
config.append(self.si570.get_n1_div())
config.append(self.si570.get_hs_div())
return config
"""
try
:
return
self
.
si570
.
get_rfreq
(),
self
.
si570
.
get_n1_div
(),
self
.
si570
.
get_hs_div
()
except
Si57xOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
# Get Si570 raw config (hex value of the I2C registers in a table)
def
get_si570_raw_config
(
self
):
return
self
.
si570
.
get_raw_config
()
try
:
return
self
.
si570
.
get_raw_config
()
except
Si57xOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
test/fmcadc100m14b4cha/python/test01.py
View file @
c48ae8d9
...
...
@@ -58,9 +58,6 @@ def main (default_directory='.'):
except
FmcAdc100mOperationError
as
e
:
raise
PtsCritical
(
"Mezzanine init failed, test stopped:
%
s"
%
e
)
# Read unique ID and print to log
unique_id
=
fmc
.
get_unique_id
()
if
(
unique_id
==
-
1
):
...
...
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