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FMC ADC 100M 14b 4cha - Testing
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FMC ADC 100M 14b 4cha - Testing
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4e3a3b20
Commit
4e3a3b20
authored
Aug 25, 2014
by
Matthieu Cattin
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test44: comment out change of sampling clock.
For now, the clock is fixed at 100MHz, due to fpga pll constraints.
parent
85e7e58d
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test44.py
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tests/test44.py
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4e3a3b20
...
@@ -266,7 +266,6 @@ def main (default_directory='.'):
...
@@ -266,7 +266,6 @@ def main (default_directory='.'):
time.sleep(3)
time.sleep(3)
fs_clk = fmc.get_samp_freq()
fs_clk = fmc.get_samp_freq()
print("Sampling frequency:
%
d Hz"
%
fs_clk)
print("Sampling frequency:
%
d Hz"
%
fs_clk)
"""
print("
\
Reduce sampling frequency")
print("
\
Reduce sampling frequency")
fmc.si570.wr_reg(0x89,(1<<4)) # freeze DCO
fmc.si570.wr_reg(0x89,(1<<4)) # freeze DCO
...
@@ -286,6 +285,8 @@ def main (default_directory='.'):
...
@@ -286,6 +285,8 @@ def main (default_directory='.'):
fmc.si570.recall_nvm()
fmc.si570.recall_nvm()
fmc.print_si570_config()
fmc.print_si570_config()
"""
time
.
sleep
(
3
)
time
.
sleep
(
3
)
fs_clk
=
fmc
.
get_samp_freq
()
fs_clk
=
fmc
.
get_samp_freq
()
print
(
"Sampling frequency:
%
d Hz"
%
fs_clk
)
print
(
"Sampling frequency:
%
d Hz"
%
fs_clk
)
...
...
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