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FMC ADC 100M 14b 4cha - Gateware
Commit b4cf7521 authored by Matthieu Cattin's avatar Matthieu Cattin
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hdl: Update wbgen wishbone interfaces (port name change).

parent dbd5e841
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Showing with 237 additions and 291 deletions
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ b4cf7521
......@@ -143,15 +143,16 @@ architecture rtl of fmc_adc_100Ms_core is
component fmc_adc_100Ms_csr
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
fs_clk_i : in std_logic;
fmc_adc_core_ctl_fsm_cmd_o : out std_logic_vector(1 downto 0);
fmc_adc_core_ctl_fsm_cmd_wr_o : out std_logic;
......@@ -637,15 +638,16 @@ begin
cmp_fmc_adc_100Ms_csr : fmc_adc_100Ms_csr
port map(
rst_n_i => sys_rst_n_i,
wb_clk_i => sys_clk_i,
wb_addr_i => wb_csr_adr_i,
wb_data_i => wb_csr_dat_i,
wb_data_o => wb_csr_dat_o,
clk_sys_i => sys_clk_i,
wb_adr_i => wb_csr_adr_i,
wb_dat_i => wb_csr_dat_i,
wb_dat_o => wb_csr_dat_o,
wb_cyc_i => wb_csr_cyc_i,
wb_sel_i => wb_csr_sel_i,
wb_stb_i => wb_csr_stb_i,
wb_we_i => wb_csr_we_i,
wb_ack_o => wb_csr_ack_o,
wb_stall_o => open,
fs_clk_i => fs_clk,
fmc_adc_core_ctl_fsm_cmd_o => fsm_cmd,
fmc_adc_core_ctl_fsm_cmd_wr_o => fsm_cmd_wr,
......
hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
View file @ b4cf7521
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Thu Aug 30 09:41:11 2012
-- Created : Fri May 3 10:49:18 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -17,24 +17,25 @@ use ieee.numeric_std.all;
entity fmc_adc_100Ms_csr is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
fs_clk_i : in std_logic;
-- Ports for PASS_THROUGH field: 'State machine commands' in reg: 'Control register'
-- Ports for PASS_THROUGH field: 'State machine commands (ignore on read)' in reg: 'Control register'
fmc_adc_core_ctl_fsm_cmd_o : out std_logic_vector(1 downto 0);
fmc_adc_core_ctl_fsm_cmd_wr_o : out std_logic;
-- Port for BIT field: 'FMC Si750 output enable' in reg: 'Control register'
fmc_adc_core_ctl_fmc_clk_oe_o : out std_logic;
-- Port for BIT field: 'Offset DACs clear (active low)' in reg: 'Control register'
fmc_adc_core_ctl_offset_dac_clr_n_o : out std_logic;
-- Port for asynchronous (clock: fs_clk_i) MONOSTABLE field: 'Manual serdes bitslip' in reg: 'Control register'
-- Port for asynchronous (clock: fs_clk_i) MONOSTABLE field: 'Manual serdes bitslip (ignore on read)' in reg: 'Control register'
fmc_adc_core_ctl_man_bitslip_o : out std_logic;
-- Port for BIT field: 'Enable test data' in reg: 'Control register'
fmc_adc_core_ctl_test_data_en_o : out std_logic;
......@@ -68,7 +69,7 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_trig_cfg_int_trig_thres_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Trigger delay value' in reg: 'Trigger delay'
fmc_adc_core_trig_dly_o : out std_logic_vector(31 downto 0);
-- Ports for asynchronous (clock: fs_clk_i) PASS_THROUGH field: 'Software trigger' in reg: 'Software trigger'
-- Ports for asynchronous (clock: fs_clk_i) PASS_THROUGH field: 'Software trigger (ignore on read)' in reg: 'Software trigger'
fmc_adc_core_sw_trig_o : out std_logic_vector(31 downto 0);
fmc_adc_core_sw_trig_wr_o : out std_logic;
-- Port for std_logic_vector field: 'Number of shots' in reg: 'Number of shots'
......@@ -269,22 +270,20 @@ signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (bus_clock_int, rst_n_i)
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
......@@ -357,7 +356,7 @@ begin
fmc_adc_core_ch4_gain_reserved_int <= "0000000000000000";
fmc_adc_core_ch4_offset_val_int <= "0000000000000000";
fmc_adc_core_ch4_offset_reserved_int <= "0000000000000000";
elsif rising_edge(bus_clock_int) then
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
......@@ -408,55 +407,41 @@ begin
when "00000" =>
if (wb_we_i = '1') then
fmc_adc_core_ctl_fsm_cmd_wr_o <= '1';
rddata_reg(2) <= 'X';
fmc_adc_core_ctl_fmc_clk_oe_int <= wrdata_reg(2);
rddata_reg(3) <= 'X';
fmc_adc_core_ctl_offset_dac_clr_n_int <= wrdata_reg(3);
rddata_reg(4) <= 'X';
fmc_adc_core_ctl_man_bitslip_int <= wrdata_reg(4);
fmc_adc_core_ctl_man_bitslip_int_delay <= wrdata_reg(4);
rddata_reg(5) <= 'X';
fmc_adc_core_ctl_test_data_en_int <= wrdata_reg(5);
rddata_reg(6) <= 'X';
fmc_adc_core_ctl_trig_led_int <= wrdata_reg(6);
rddata_reg(7) <= 'X';
fmc_adc_core_ctl_acq_led_int <= wrdata_reg(7);
fmc_adc_core_ctl_reserved_int <= wrdata_reg(31 downto 8);
else
end if;
rddata_reg(2) <= fmc_adc_core_ctl_fmc_clk_oe_int;
rddata_reg(3) <= fmc_adc_core_ctl_offset_dac_clr_n_int;
rddata_reg(4) <= 'X';
rddata_reg(4) <= '0';
rddata_reg(5) <= fmc_adc_core_ctl_test_data_en_int;
rddata_reg(6) <= fmc_adc_core_ctl_trig_led_int;
rddata_reg(7) <= fmc_adc_core_ctl_acq_led_int;
rddata_reg(31 downto 8) <= fmc_adc_core_ctl_reserved_int;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
end if;
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "00001" =>
if (wb_we_i = '1') then
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
else
end if;
rddata_reg(2 downto 0) <= fmc_adc_core_sta_fsm_i;
rddata_reg(3) <= fmc_adc_core_sta_serdes_pll_i;
rddata_reg(4) <= fmc_adc_core_sta_serdes_synced_i;
rddata_reg(31 downto 5) <= fmc_adc_core_sta_reserved_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010" =>
if (wb_we_i = '1') then
fmc_adc_core_trig_cfg_hw_trig_sel_int <= wrdata_reg(0);
rddata_reg(0) <= 'X';
fmc_adc_core_trig_cfg_hw_trig_pol_int <= wrdata_reg(1);
rddata_reg(1) <= 'X';
fmc_adc_core_trig_cfg_hw_trig_en_int <= wrdata_reg(2);
rddata_reg(2) <= 'X';
fmc_adc_core_trig_cfg_sw_trig_en_int <= wrdata_reg(3);
rddata_reg(3) <= 'X';
fmc_adc_core_trig_cfg_int_trig_sel_int <= wrdata_reg(5 downto 4);
fmc_adc_core_trig_cfg_int_trig_sel_swb <= '1';
fmc_adc_core_trig_cfg_int_trig_sel_swb_delay <= '1';
......@@ -464,7 +449,7 @@ begin
fmc_adc_core_trig_cfg_int_trig_thres_int <= wrdata_reg(31 downto 16);
fmc_adc_core_trig_cfg_int_trig_thres_swb <= '1';
fmc_adc_core_trig_cfg_int_trig_thres_swb_delay <= '1';
else
end if;
rddata_reg(0) <= fmc_adc_core_trig_cfg_hw_trig_sel_int;
rddata_reg(1) <= fmc_adc_core_trig_cfg_hw_trig_pol_int;
rddata_reg(2) <= fmc_adc_core_trig_cfg_hw_trig_en_int;
......@@ -472,22 +457,20 @@ begin
rddata_reg(5 downto 4) <= fmc_adc_core_trig_cfg_int_trig_sel_int;
rddata_reg(15 downto 6) <= fmc_adc_core_trig_cfg_reserved_int;
rddata_reg(31 downto 16) <= fmc_adc_core_trig_cfg_int_trig_thres_int;
end if;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "00011" =>
if (wb_we_i = '1') then
fmc_adc_core_trig_dly_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= fmc_adc_core_trig_dly_int;
end if;
rddata_reg(31 downto 0) <= fmc_adc_core_trig_dly_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100" =>
if (wb_we_i = '1') then
fmc_adc_core_sw_trig_wr_int <= '1';
fmc_adc_core_sw_trig_wr_int_delay <= '1';
else
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
......@@ -520,24 +503,21 @@ begin
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "00101" =>
if (wb_we_i = '1') then
fmc_adc_core_shots_nb_int <= wrdata_reg(15 downto 0);
fmc_adc_core_shots_reserved_int <= wrdata_reg(31 downto 16);
else
end if;
rddata_reg(15 downto 0) <= fmc_adc_core_shots_nb_int;
rddata_reg(31 downto 16) <= fmc_adc_core_shots_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= fmc_adc_core_trig_pos_i;
end if;
rddata_reg(31 downto 0) <= fmc_adc_core_trig_pos_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111" =>
......@@ -546,193 +526,181 @@ begin
fmc_adc_core_sr_deci_swb <= '1';
fmc_adc_core_sr_deci_swb_delay <= '1';
fmc_adc_core_sr_reserved_int <= wrdata_reg(31 downto 16);
else
end if;
rddata_reg(15 downto 0) <= fmc_adc_core_sr_deci_int;
rddata_reg(31 downto 16) <= fmc_adc_core_sr_reserved_int;
end if;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "01000" =>
if (wb_we_i = '1') then
fmc_adc_core_pre_samples_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= fmc_adc_core_pre_samples_int;
end if;
rddata_reg(31 downto 0) <= fmc_adc_core_pre_samples_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001" =>
if (wb_we_i = '1') then
fmc_adc_core_post_samples_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= fmc_adc_core_post_samples_int;
end if;
rddata_reg(31 downto 0) <= fmc_adc_core_post_samples_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= fmc_adc_core_samples_cnt_i;
end if;
rddata_reg(31 downto 0) <= fmc_adc_core_samples_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011" =>
if (wb_we_i = '1') then
fmc_adc_core_ch1_ctl_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch1_ctl_reserved_int <= wrdata_reg(31 downto 7);
else
end if;
rddata_reg(6 downto 0) <= fmc_adc_core_ch1_ctl_ssr_int;
rddata_reg(31 downto 7) <= fmc_adc_core_ch1_ctl_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100" =>
if (wb_we_i = '1') then
else
end if;
if (wb_we_i = '0') then
fmc_adc_core_ch1_sta_val_lwb <= '1';
fmc_adc_core_ch1_sta_val_lwb_delay <= '1';
fmc_adc_core_ch1_sta_val_lwb_in_progress <= '1';
rddata_reg(31 downto 16) <= fmc_adc_core_ch1_sta_reserved_i;
end if;
rddata_reg(31 downto 16) <= fmc_adc_core_ch1_sta_reserved_i;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "01101" =>
if (wb_we_i = '1') then
fmc_adc_core_ch1_gain_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch1_gain_reserved_int <= wrdata_reg(31 downto 16);
else
end if;
rddata_reg(15 downto 0) <= fmc_adc_core_ch1_gain_val_int;
rddata_reg(31 downto 16) <= fmc_adc_core_ch1_gain_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110" =>
if (wb_we_i = '1') then
fmc_adc_core_ch1_offset_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch1_offset_reserved_int <= wrdata_reg(31 downto 16);
else
end if;
rddata_reg(15 downto 0) <= fmc_adc_core_ch1_offset_val_int;
rddata_reg(31 downto 16) <= fmc_adc_core_ch1_offset_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111" =>
if (wb_we_i = '1') then
fmc_adc_core_ch2_ctl_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch2_ctl_reserved_int <= wrdata_reg(31 downto 7);
else
end if;
rddata_reg(6 downto 0) <= fmc_adc_core_ch2_ctl_ssr_int;
rddata_reg(31 downto 7) <= fmc_adc_core_ch2_ctl_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000" =>
if (wb_we_i = '1') then
else
end if;
if (wb_we_i = '0') then
fmc_adc_core_ch2_sta_val_lwb <= '1';
fmc_adc_core_ch2_sta_val_lwb_delay <= '1';
fmc_adc_core_ch2_sta_val_lwb_in_progress <= '1';
rddata_reg(31 downto 16) <= fmc_adc_core_ch2_sta_reserved_i;
end if;
rddata_reg(31 downto 16) <= fmc_adc_core_ch2_sta_reserved_i;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "10001" =>
if (wb_we_i = '1') then
fmc_adc_core_ch2_gain_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch2_gain_reserved_int <= wrdata_reg(31 downto 16);
else
end if;
rddata_reg(15 downto 0) <= fmc_adc_core_ch2_gain_val_int;
rddata_reg(31 downto 16) <= fmc_adc_core_ch2_gain_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010" =>
if (wb_we_i = '1') then
fmc_adc_core_ch2_offset_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch2_offset_reserved_int <= wrdata_reg(31 downto 16);
else
end if;
rddata_reg(15 downto 0) <= fmc_adc_core_ch2_offset_val_int;
rddata_reg(31 downto 16) <= fmc_adc_core_ch2_offset_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011" =>
if (wb_we_i = '1') then
fmc_adc_core_ch3_ctl_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch3_ctl_reserved_int <= wrdata_reg(31 downto 7);
else
end if;
rddata_reg(6 downto 0) <= fmc_adc_core_ch3_ctl_ssr_int;
rddata_reg(31 downto 7) <= fmc_adc_core_ch3_ctl_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10100" =>
if (wb_we_i = '1') then
else
end if;
if (wb_we_i = '0') then
fmc_adc_core_ch3_sta_val_lwb <= '1';
fmc_adc_core_ch3_sta_val_lwb_delay <= '1';
fmc_adc_core_ch3_sta_val_lwb_in_progress <= '1';
rddata_reg(31 downto 16) <= fmc_adc_core_ch3_sta_reserved_i;
end if;
rddata_reg(31 downto 16) <= fmc_adc_core_ch3_sta_reserved_i;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "10101" =>
if (wb_we_i = '1') then
fmc_adc_core_ch3_gain_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch3_gain_reserved_int <= wrdata_reg(31 downto 16);
else
end if;
rddata_reg(15 downto 0) <= fmc_adc_core_ch3_gain_val_int;
rddata_reg(31 downto 16) <= fmc_adc_core_ch3_gain_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10110" =>
if (wb_we_i = '1') then
fmc_adc_core_ch3_offset_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch3_offset_reserved_int <= wrdata_reg(31 downto 16);
else
end if;
rddata_reg(15 downto 0) <= fmc_adc_core_ch3_offset_val_int;
rddata_reg(31 downto 16) <= fmc_adc_core_ch3_offset_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10111" =>
if (wb_we_i = '1') then
fmc_adc_core_ch4_ctl_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch4_ctl_reserved_int <= wrdata_reg(31 downto 7);
else
end if;
rddata_reg(6 downto 0) <= fmc_adc_core_ch4_ctl_ssr_int;
rddata_reg(31 downto 7) <= fmc_adc_core_ch4_ctl_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11000" =>
if (wb_we_i = '1') then
else
end if;
if (wb_we_i = '0') then
fmc_adc_core_ch4_sta_val_lwb <= '1';
fmc_adc_core_ch4_sta_val_lwb_delay <= '1';
fmc_adc_core_ch4_sta_val_lwb_in_progress <= '1';
rddata_reg(31 downto 16) <= fmc_adc_core_ch4_sta_reserved_i;
end if;
rddata_reg(31 downto 16) <= fmc_adc_core_ch4_sta_reserved_i;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "11001" =>
if (wb_we_i = '1') then
fmc_adc_core_ch4_gain_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch4_gain_reserved_int <= wrdata_reg(31 downto 16);
else
end if;
rddata_reg(15 downto 0) <= fmc_adc_core_ch4_gain_val_int;
rddata_reg(31 downto 16) <= fmc_adc_core_ch4_gain_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11010" =>
if (wb_we_i = '1') then
fmc_adc_core_ch4_offset_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch4_offset_reserved_int <= wrdata_reg(31 downto 16);
else
end if;
rddata_reg(15 downto 0) <= fmc_adc_core_ch4_offset_val_int;
rddata_reg(31 downto 16) <= fmc_adc_core_ch4_offset_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
......@@ -747,15 +715,15 @@ begin
-- Drive the data output bus
wb_data_o <= rddata_reg;
-- State machine commands
-- pass-through field: State machine commands in register: Control register
wb_dat_o <= rddata_reg;
-- State machine commands (ignore on read)
-- pass-through field: State machine commands (ignore on read) in register: Control register
fmc_adc_core_ctl_fsm_cmd_o <= wrdata_reg(1 downto 0);
-- FMC Si750 output enable
fmc_adc_core_ctl_fmc_clk_oe_o <= fmc_adc_core_ctl_fmc_clk_oe_int;
-- Offset DACs clear (active low)
fmc_adc_core_ctl_offset_dac_clr_n_o <= fmc_adc_core_ctl_offset_dac_clr_n_int;
-- Manual serdes bitslip
-- Manual serdes bitslip (ignore on read)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -785,7 +753,7 @@ begin
-- SerDes synchronization status
-- Reserved
-- Hardware trigger selection
-- synchronizer chain for field : Hardware trigger selection (type RW/RO, bus_clock_int <-> fs_clk_i)
-- synchronizer chain for field : Hardware trigger selection (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -801,7 +769,7 @@ begin
-- Hardware trigger polarity
-- synchronizer chain for field : Hardware trigger polarity (type RW/RO, bus_clock_int <-> fs_clk_i)
-- synchronizer chain for field : Hardware trigger polarity (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -817,7 +785,7 @@ begin
-- Hardware trigger enable
-- synchronizer chain for field : Hardware trigger enable (type RW/RO, bus_clock_int <-> fs_clk_i)
-- synchronizer chain for field : Hardware trigger enable (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -833,7 +801,7 @@ begin
-- Software trigger enable
-- synchronizer chain for field : Software trigger enable (type RW/RO, bus_clock_int <-> fs_clk_i)
-- synchronizer chain for field : Software trigger enable (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -849,7 +817,7 @@ begin
-- Channel selection for internal trigger
-- asynchronous std_logic_vector register : Channel selection for internal trigger (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -871,7 +839,7 @@ begin
-- Reserved
fmc_adc_core_trig_cfg_reserved_o <= fmc_adc_core_trig_cfg_reserved_int;
-- Threshold for internal trigger
-- asynchronous std_logic_vector register : Threshold for internal trigger (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -892,8 +860,8 @@ begin
-- Trigger delay value
fmc_adc_core_trig_dly_o <= fmc_adc_core_trig_dly_int;
-- Software trigger
-- pass-through field: Software trigger in register: Software trigger
-- Software trigger (ignore on read)
-- pass-through field: Software trigger (ignore on read) in register: Software trigger
fmc_adc_core_sw_trig_o <= wrdata_reg(31 downto 0);
process (fs_clk_i, rst_n_i)
begin
......@@ -916,7 +884,7 @@ begin
fmc_adc_core_shots_reserved_o <= fmc_adc_core_shots_reserved_int;
-- Trigger address
-- Sample rate decimation
-- asynchronous std_logic_vector register : Sample rate decimation (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -947,7 +915,7 @@ begin
-- Reserved
fmc_adc_core_ch1_ctl_reserved_o <= fmc_adc_core_ch1_ctl_reserved_int;
-- Channel 1 current ADC value
-- asynchronous std_logic_vector register : Channel 1 current ADC value (type RO/WO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -980,7 +948,7 @@ begin
-- Reserved
fmc_adc_core_ch2_ctl_reserved_o <= fmc_adc_core_ch2_ctl_reserved_int;
-- Channel 2 current ACD value
-- asynchronous std_logic_vector register : Channel 2 current ACD value (type RO/WO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1013,7 +981,7 @@ begin
-- Reserved
fmc_adc_core_ch3_ctl_reserved_o <= fmc_adc_core_ch3_ctl_reserved_int;
-- Channel 3 current ADC value
-- asynchronous std_logic_vector register : Channel 3 current ADC value (type RO/WO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1046,7 +1014,7 @@ begin
-- Reserved
fmc_adc_core_ch4_ctl_reserved_o <= fmc_adc_core_ch4_ctl_reserved_int;
-- Channel 4 current ADC value
-- asynchronous std_logic_vector register : Channel 4 current ADC value (type RO/WO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1074,7 +1042,8 @@ begin
fmc_adc_core_ch4_offset_val_o <= fmc_adc_core_ch4_offset_val_int;
-- Reserved
fmc_adc_core_ch4_offset_reserved_o <= fmc_adc_core_ch4_offset_reserved_int;
rwaddr_reg <= wb_addr_i;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/spec/rtl/carrier_csr.vhd
View file @ b4cf7521
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Mon Mar 11 17:11:09 2013
-- Created : Tue Apr 9 18:41:24 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -17,15 +17,16 @@ use ieee.numeric_std.all;
entity carrier_csr is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'PCB revision' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_pcb_rev_i : in std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Reserved register' in reg: 'Carrier type and PCB version'
......@@ -67,22 +68,20 @@ signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (bus_clock_int, rst_n_i)
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
......@@ -92,7 +91,7 @@ begin
carrier_csr_ctrl_led_red_int <= '0';
carrier_csr_ctrl_dac_clr_n_int <= '0';
carrier_csr_ctrl_reserved_int <= "00000000000000000000000000000";
elsif rising_edge(bus_clock_int) then
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
......@@ -106,43 +105,33 @@ begin
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
else
end if;
rddata_reg(3 downto 0) <= carrier_csr_carrier_pcb_rev_i;
rddata_reg(15 downto 4) <= carrier_csr_carrier_reserved_i;
rddata_reg(31 downto 16) <= carrier_csr_carrier_type_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
else
end if;
rddata_reg(0) <= carrier_csr_stat_fmc_pres_i;
rddata_reg(1) <= carrier_csr_stat_p2l_pll_lck_i;
rddata_reg(2) <= carrier_csr_stat_sys_pll_lck_i;
rddata_reg(3) <= carrier_csr_stat_ddr3_cal_done_i;
rddata_reg(31 downto 4) <= carrier_csr_stat_reserved_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
carrier_csr_ctrl_led_green_int <= wrdata_reg(0);
rddata_reg(1) <= 'X';
carrier_csr_ctrl_led_red_int <= wrdata_reg(1);
rddata_reg(2) <= 'X';
carrier_csr_ctrl_dac_clr_n_int <= wrdata_reg(2);
carrier_csr_ctrl_reserved_int <= wrdata_reg(31 downto 3);
else
end if;
rddata_reg(0) <= carrier_csr_ctrl_led_green_int;
rddata_reg(1) <= carrier_csr_ctrl_led_red_int;
rddata_reg(2) <= carrier_csr_ctrl_dac_clr_n_int;
rddata_reg(31 downto 3) <= carrier_csr_ctrl_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
......@@ -157,7 +146,7 @@ begin
-- Drive the data output bus
wb_data_o <= rddata_reg;
wb_dat_o <= rddata_reg;
-- PCB revision
-- Reserved register
-- Carrier type
......@@ -174,7 +163,8 @@ begin
carrier_csr_ctrl_dac_clr_n_o <= carrier_csr_ctrl_dac_clr_n_int;
-- Reserved
carrier_csr_ctrl_reserved_o <= carrier_csr_ctrl_reserved_int;
rwaddr_reg <= wb_addr_i;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/spec/rtl/irq_controller.vhd
View file @ b4cf7521
......@@ -77,15 +77,16 @@ architecture rtl of irq_controller is
component irq_controller_regs
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
irq_ctrl_multi_irq_o : out std_logic_vector(31 downto 0);
irq_ctrl_multi_irq_i : in std_logic_vector(31 downto 0);
irq_ctrl_multi_irq_load_o : out std_logic;
......@@ -119,15 +120,16 @@ begin
cmp_irq_controller_regs : irq_controller_regs
port map(
rst_n_i => rst_n_i,
wb_clk_i => clk_i,
wb_addr_i => wb_adr_i,
wb_data_i => wb_dat_i,
wb_data_o => wb_dat_o,
clk_sys_i => clk_i,
wb_adr_i => wb_adr_i,
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
wb_stall_o => open,
irq_ctrl_multi_irq_o => multi_irq_rst,
irq_ctrl_multi_irq_load_o => multi_irq_rst_en,
irq_ctrl_multi_irq_i => multi_irq,
......
hdl/spec/rtl/irq_controller_regs.vhd
View file @ b4cf7521
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/irq_controller_regs.vhd
-- Author : auto-generated by wbgen2 from irq_controller_regs.wb
-- Created : Wed Jan 18 09:43:55 2012
-- Created : Tue Apr 9 18:41:31 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller_regs.wb
......@@ -17,15 +17,16 @@ use ieee.numeric_std.all;
entity irq_controller_regs is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'Multiple interrupt' in reg: 'Multiple interrupt register'
irq_ctrl_multi_irq_o : out std_logic_vector(31 downto 0);
irq_ctrl_multi_irq_i : in std_logic_vector(31 downto 0);
......@@ -50,22 +51,20 @@ signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (bus_clock_int, rst_n_i)
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
......@@ -74,7 +73,7 @@ begin
irq_ctrl_multi_irq_load_o <= '0';
irq_ctrl_src_load_o <= '0';
irq_ctrl_en_mask_int <= "00000000000000000000000000000000";
elsif rising_edge(bus_clock_int) then
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
......@@ -93,25 +92,22 @@ begin
when "00" =>
if (wb_we_i = '1') then
irq_ctrl_multi_irq_load_o <= '1';
else
rddata_reg(31 downto 0) <= irq_ctrl_multi_irq_i;
end if;
rddata_reg(31 downto 0) <= irq_ctrl_multi_irq_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
irq_ctrl_src_load_o <= '1';
else
rddata_reg(31 downto 0) <= irq_ctrl_src_i;
end if;
rddata_reg(31 downto 0) <= irq_ctrl_src_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
irq_ctrl_en_mask_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= irq_ctrl_en_mask_int;
end if;
rddata_reg(31 downto 0) <= irq_ctrl_en_mask_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
......@@ -126,14 +122,15 @@ begin
-- Drive the data output bus
wb_data_o <= rddata_reg;
wb_dat_o <= rddata_reg;
-- Multiple interrupt
irq_ctrl_multi_irq_o <= wrdata_reg(31 downto 0);
-- Interrupt sources
irq_ctrl_src_o <= wrdata_reg(31 downto 0);
-- Interrupt enable mask
irq_ctrl_en_mask_o <= irq_ctrl_en_mask_int;
rwaddr_reg <= wb_addr_i;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ b4cf7521
......@@ -172,15 +172,16 @@ architecture rtl of spec_top_fmc_adc_100Ms is
component carrier_csr
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
carrier_csr_carrier_pcb_rev_i : in std_logic_vector(3 downto 0);
carrier_csr_carrier_reserved_i : in std_logic_vector(11 downto 0);
carrier_csr_carrier_type_i : in std_logic_vector(15 downto 0);
......@@ -782,15 +783,16 @@ begin
cmp_carrier_csr : carrier_csr
port map(
rst_n_i => sys_rst_n,
wb_clk_i => sys_clk_125,
wb_addr_i => cnx_master_out(c_SLAVE_SPEC_CSR).adr(3 downto 2), -- cnx_master_out.adr is byte address
wb_data_i => cnx_master_out(c_SLAVE_SPEC_CSR).dat,
wb_data_o => cnx_master_in(c_SLAVE_SPEC_CSR).dat,
clk_sys_i => sys_clk_125,
wb_adr_i => cnx_master_out(c_SLAVE_SPEC_CSR).adr(3 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_SLAVE_SPEC_CSR).dat,
wb_dat_o => cnx_master_in(c_SLAVE_SPEC_CSR).dat,
wb_cyc_i => cnx_master_out(c_SLAVE_SPEC_CSR).cyc,
wb_sel_i => cnx_master_out(c_SLAVE_SPEC_CSR).sel,
wb_stb_i => cnx_master_out(c_SLAVE_SPEC_CSR).stb,
wb_we_i => cnx_master_out(c_SLAVE_SPEC_CSR).we,
wb_ack_o => cnx_master_in(c_SLAVE_SPEC_CSR).ack,
wb_stall_o => open,
carrier_csr_carrier_pcb_rev_i => pcb_ver_i,
carrier_csr_carrier_reserved_i => X"000",
carrier_csr_carrier_type_i => c_CARRIER_TYPE,
......
hdl/spec/rtl/utc_core.vhd
View file @ b4cf7521
......@@ -78,15 +78,16 @@ architecture rtl of utc_core is
component utc_core_regs
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
utc_core_seconds_o : out std_logic_vector(31 downto 0);
utc_core_seconds_i : in std_logic_vector(31 downto 0);
utc_core_seconds_load_o : out std_logic;
......@@ -152,15 +153,16 @@ begin
cmp_utc_core_regs : utc_core_regs
port map(
rst_n_i => rst_n_i,
wb_clk_i => clk_i,
wb_addr_i => wb_adr_i,
wb_data_i => wb_dat_i,
wb_data_o => wb_dat_o,
clk_sys_i => clk_i,
wb_adr_i => wb_adr_i,
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
wb_stall_o => open,
utc_core_seconds_o => utc_seconds_load_value,
utc_core_seconds_i => utc_seconds,
utc_core_seconds_load_o => utc_seconds_load_en,
......
hdl/spec/rtl/utc_core_regs.vhd
View file @ b4cf7521
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/utc_core_regs.vhd
-- Author : auto-generated by wbgen2 from utc_core_regs.wb
-- Created : Tue Nov 22 10:20:36 2011
-- Created : Tue Apr 9 18:41:27 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE utc_core_regs.wb
......@@ -17,15 +17,16 @@ use ieee.numeric_std.all;
entity utc_core_regs is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'UTC seconds' in reg: 'UTC seconds register'
utc_core_seconds_o : out std_logic_vector(31 downto 0);
utc_core_seconds_i : in std_logic_vector(31 downto 0);
......@@ -79,22 +80,20 @@ signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (bus_clock_int, rst_n_i)
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
......@@ -102,7 +101,7 @@ begin
rddata_reg <= "00000000000000000000000000000000";
utc_core_seconds_load_o <= '0';
utc_core_coarse_load_o <= '0';
elsif rising_edge(bus_clock_int) then
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
......@@ -121,129 +120,111 @@ begin
when "00000" =>
if (wb_we_i = '1') then
utc_core_seconds_load_o <= '1';
else
rddata_reg(31 downto 0) <= utc_core_seconds_i;
end if;
rddata_reg(31 downto 0) <= utc_core_seconds_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001" =>
if (wb_we_i = '1') then
utc_core_coarse_load_o <= '1';
else
rddata_reg(31 downto 0) <= utc_core_coarse_i;
end if;
rddata_reg(31 downto 0) <= utc_core_coarse_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_trig_tag_meta_i;
end if;
rddata_reg(31 downto 0) <= utc_core_trig_tag_meta_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_trig_tag_seconds_i;
end if;
rddata_reg(31 downto 0) <= utc_core_trig_tag_seconds_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_trig_tag_coarse_i;
end if;
rddata_reg(31 downto 0) <= utc_core_trig_tag_coarse_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_trig_tag_fine_i;
end if;
rddata_reg(31 downto 0) <= utc_core_trig_tag_fine_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_meta_i;
end if;
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_meta_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_seconds_i;
end if;
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_seconds_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_coarse_i;
end if;
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_coarse_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_fine_i;
end if;
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_fine_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_meta_i;
end if;
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_meta_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_seconds_i;
end if;
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_seconds_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_coarse_i;
end if;
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_coarse_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_fine_i;
end if;
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_fine_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_meta_i;
end if;
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_meta_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_seconds_i;
end if;
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_seconds_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_coarse_i;
end if;
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_coarse_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_fine_i;
end if;
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_fine_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
......@@ -258,7 +239,7 @@ begin
-- Drive the data output bus
wb_data_o <= rddata_reg;
wb_dat_o <= rddata_reg;
-- UTC seconds
utc_core_seconds_o <= wrdata_reg(31 downto 0);
-- UTC coarse time
......@@ -279,7 +260,8 @@ begin
-- Acquisition end time-tag UTC seconds
-- Acquisition end time-tag coarse time
-- Acquisition end time-tag fine time
rwaddr_reg <= wb_addr_i;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
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