Skip to content

F
FMC ADC 100M 14b 4cha - Gateware
Commit b48832a9 authored by Matthieu Cattin's avatar Matthieu Cattin
Browse files
Options

hdl: Insert trigger time-tag in data, after post-trigger samples.

parent 94774b66
Show whitespace changes
Inline Side-by-side
Showing with 385 additions and 311 deletions
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ b48832a9
...@@ -39,6 +39,7 @@ ...@@ -39,6 +39,7 @@
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all; use IEEE.NUMERIC_STD.all;
use work.timetag_core_pkg.all;
library UNISIM; library UNISIM;
...@@ -85,6 +86,9 @@ entity fmc_adc_100Ms_core is ...@@ -85,6 +86,9 @@ entity fmc_adc_100Ms_core is
acq_stop_p_o : out std_logic; acq_stop_p_o : out std_logic;
acq_end_p_o : out std_logic; acq_end_p_o : out std_logic;
-- Trigger time-tag input
trigger_tag_i : t_timetag;
-- FMC interface -- FMC interface
ext_trigger_p_i : in std_logic; -- External trigger ext_trigger_p_i : in std_logic; -- External trigger
ext_trigger_n_i : in std_logic; ext_trigger_n_i : in std_logic;
...@@ -276,7 +280,7 @@ architecture rtl of fmc_adc_100Ms_core is ...@@ -276,7 +280,7 @@ architecture rtl of fmc_adc_100Ms_core is
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Types declaration -- Types declaration
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
type t_acq_fsm_state is (IDLE, PRE_TRIG, WAIT_TRIG, POST_TRIG, DECR_SHOT); type t_acq_fsm_state is (IDLE, PRE_TRIG, WAIT_TRIG, POST_TRIG, TRIG_TAG, DECR_SHOT);
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Signals declaration -- Signals declaration
...@@ -346,7 +350,6 @@ architecture rtl of fmc_adc_100Ms_core is ...@@ -346,7 +350,6 @@ architecture rtl of fmc_adc_100Ms_core is
signal sync_fifo_wr : std_logic; signal sync_fifo_wr : std_logic;
signal sync_fifo_rd : std_logic; signal sync_fifo_rd : std_logic;
signal sync_fifo_valid : std_logic; signal sync_fifo_valid : std_logic;
signal sync_fifo_dreq : std_logic;
-- Gain/offset calibration -- Gain/offset calibration
signal gain_calibr : std_logic_vector(63 downto 0); signal gain_calibr : std_logic_vector(63 downto 0);
...@@ -355,7 +358,6 @@ architecture rtl of fmc_adc_100Ms_core is ...@@ -355,7 +358,6 @@ architecture rtl of fmc_adc_100Ms_core is
signal data_calibr_out : std_logic_vector(63 downto 0); signal data_calibr_out : std_logic_vector(63 downto 0);
signal data_calibr_out_d : std_logic_vector(63 downto 0); signal data_calibr_out_d : std_logic_vector(63 downto 0);
-- Acquisition FSM -- Acquisition FSM
signal acq_fsm_current_state : t_acq_fsm_state; signal acq_fsm_current_state : t_acq_fsm_state;
signal acq_fsm_state : std_logic_vector(2 downto 0); signal acq_fsm_state : std_logic_vector(2 downto 0);
...@@ -369,8 +371,14 @@ architecture rtl of fmc_adc_100Ms_core is ...@@ -369,8 +371,14 @@ architecture rtl of fmc_adc_100Ms_core is
signal acq_in_pre_trig : std_logic; signal acq_in_pre_trig : std_logic;
signal acq_in_wait_trig : std_logic; signal acq_in_wait_trig : std_logic;
signal acq_in_post_trig : std_logic; signal acq_in_post_trig : std_logic;
signal acq_in_trig_tag : std_logic;
signal samples_wr_en : std_logic; signal samples_wr_en : std_logic;
-- Trigger tag insertion in data
signal trig_tag_done : std_logic;
signal trig_tag_data : std_logic_vector(63 downto 0);
signal trig_tag_progress : std_logic_vector(1 downto 0);
-- pre/post trigger and shots counters -- pre/post trigger and shots counters
signal pre_trig_value : std_logic_vector(31 downto 0); signal pre_trig_value : std_logic_vector(31 downto 0);
signal pre_trig_cnt : unsigned(31 downto 0); signal pre_trig_cnt : unsigned(31 downto 0);
...@@ -970,7 +978,7 @@ begin ...@@ -970,7 +978,7 @@ begin
-- "00000000" & serdes_out_fr; -- "00000000" & serdes_out_fr;
sync_fifo_wr <= decim_en and serdes_synced and not(sync_fifo_full); sync_fifo_wr <= decim_en and serdes_synced and not(sync_fifo_full);
sync_fifo_rd <= sync_fifo_dreq and not(sync_fifo_empty); sync_fifo_rd <= not(sync_fifo_empty); -- read sync fifo as soon as data are available
--============================================================================ --============================================================================
...@@ -1162,6 +1170,13 @@ begin ...@@ -1162,6 +1170,13 @@ begin
if acq_stop = '1' then if acq_stop = '1' then
acq_fsm_current_state <= IDLE; acq_fsm_current_state <= IDLE;
elsif post_trig_done = '1' then elsif post_trig_done = '1' then
acq_fsm_current_state <= TRIG_TAG;
end if;
when TRIG_TAG =>
if acq_stop = '1' then
acq_fsm_current_state <= IDLE;
elsif trig_tag_done = '1' then
if single_shot = '1' then if single_shot = '1' then
acq_fsm_current_state <= IDLE; acq_fsm_current_state <= IDLE;
else else
...@@ -1195,64 +1210,93 @@ begin ...@@ -1195,64 +1210,93 @@ begin
when IDLE => when IDLE =>
shots_decr <= '0'; shots_decr <= '0';
sync_fifo_dreq <= '1';
acq_in_pre_trig <= '0'; acq_in_pre_trig <= '0';
acq_in_wait_trig <= '0'; acq_in_wait_trig <= '0';
acq_in_post_trig <= '0'; acq_in_post_trig <= '0';
acq_in_trig_tag <= '0';
samples_wr_en <= '0'; samples_wr_en <= '0';
acq_fsm_state <= "001"; acq_fsm_state <= "001";
when PRE_TRIG => when PRE_TRIG =>
shots_decr <= '0'; shots_decr <= '0';
sync_fifo_dreq <= '1';
acq_in_pre_trig <= '1'; acq_in_pre_trig <= '1';
acq_in_wait_trig <= '0'; acq_in_wait_trig <= '0';
acq_in_post_trig <= '0'; acq_in_post_trig <= '0';
acq_in_trig_tag <= '0';
samples_wr_en <= '1'; samples_wr_en <= '1';
acq_fsm_state <= "010"; acq_fsm_state <= "010";
when WAIT_TRIG => when WAIT_TRIG =>
shots_decr <= '0'; shots_decr <= '0';
sync_fifo_dreq <= '1';
acq_in_pre_trig <= '0'; acq_in_pre_trig <= '0';
acq_in_wait_trig <= '1'; acq_in_wait_trig <= '1';
acq_in_post_trig <= '0'; acq_in_post_trig <= '0';
acq_in_trig_tag <= '0';
samples_wr_en <= '1'; samples_wr_en <= '1';
acq_fsm_state <= "011"; acq_fsm_state <= "011";
when POST_TRIG => when POST_TRIG =>
shots_decr <= '0'; shots_decr <= '0';
sync_fifo_dreq <= '1';
acq_in_pre_trig <= '0'; acq_in_pre_trig <= '0';
acq_in_wait_trig <= '0'; acq_in_wait_trig <= '0';
acq_in_post_trig <= '1'; acq_in_post_trig <= '1';
acq_in_trig_tag <= '0';
samples_wr_en <= '1'; samples_wr_en <= '1';
acq_fsm_state <= "100"; acq_fsm_state <= "100";
when TRIG_TAG =>
shots_decr <= '0';
acq_in_pre_trig <= '0';
acq_in_wait_trig <= '0';
acq_in_post_trig <= '0';
acq_in_trig_tag <= '1';
samples_wr_en <= '0';
acq_fsm_state <= "101";
when DECR_SHOT => when DECR_SHOT =>
shots_decr <= '1'; shots_decr <= '1';
sync_fifo_dreq <= '1';
acq_in_pre_trig <= '0'; acq_in_pre_trig <= '0';
acq_in_wait_trig <= '0'; acq_in_wait_trig <= '0';
acq_in_post_trig <= '0'; acq_in_post_trig <= '0';
acq_in_trig_tag <= '0';
samples_wr_en <= '0'; samples_wr_en <= '0';
acq_fsm_state <= "101"; acq_fsm_state <= "110";
when others => when others =>
shots_decr <= '0'; shots_decr <= '0';
sync_fifo_dreq <= '1';
acq_in_pre_trig <= '0'; acq_in_pre_trig <= '0';
acq_in_wait_trig <= '0'; acq_in_wait_trig <= '0';
acq_in_post_trig <= '0'; acq_in_post_trig <= '0';
acq_in_trig_tag <= '0';
samples_wr_en <= '0'; samples_wr_en <= '0';
acq_fsm_state <= "111"; acq_fsm_state <= "111";
end case; end case;
end process p_acq_fsm_outputs; end process p_acq_fsm_outputs;
------------------------------------------------------------------------------
-- Inserting trigger time-tag after post_trigger samples
------------------------------------------------------------------------------
-- ###
p_insert_trig_tag : process (sys_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
trig_tag_data <= (others => '0');
trig_tag_progress <= (others => '0');
elsif rising_edge(sys_clk_i) then
trig_tag_done <= acq_in_trig_tag;
if trig_tag_done = '0' then
trig_tag_data <= trigger_tag_i.seconds & trigger_tag_i.meta;
elsif trig_tag_done = '1' then
trig_tag_data <= trigger_tag_i.fine & trigger_tag_i.coarse;
end if;
end if;
end process p_insert_trig_tag;
-- ###
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Dual DPRAM buffers for multi-shots acquisition -- Dual DPRAM buffers for multi-shots acquisition
----------------------------------------------------------------------------- ------------------------------------------------------------------------------
-- DPRAM input address counter -- DPRAM input address counter
p_dpram_addra_cnt : process (sys_clk_i, sys_rst_n_i) p_dpram_addra_cnt : process (sys_clk_i, sys_rst_n_i)
...@@ -1283,10 +1327,10 @@ begin ...@@ -1283,10 +1327,10 @@ begin
-- DPRAM inputs -- DPRAM inputs
dpram0_addra <= std_logic_vector(dpram_addra_cnt); dpram0_addra <= std_logic_vector(dpram_addra_cnt);
dpram1_addra <= std_logic_vector(dpram_addra_cnt); dpram1_addra <= std_logic_vector(dpram_addra_cnt);
dpram0_dina <= sync_fifo_dout(63 downto 0); dpram0_dina <= sync_fifo_dout(63 downto 0) when acq_in_trig_tag = '0' else trig_tag_data; -- ###
dpram1_dina <= sync_fifo_dout(63 downto 0); dpram1_dina <= sync_fifo_dout(63 downto 0) when acq_in_trig_tag = '0' else trig_tag_data; -- ###;
dpram0_wea <= (samples_wr_en and sync_fifo_valid) when multishot_buffer_sel = '0' else '0'; dpram0_wea <= (samples_wr_en and sync_fifo_valid) or acq_in_trig_tag when multishot_buffer_sel = '0' else '0'; -- ###
dpram1_wea <= (samples_wr_en and sync_fifo_valid) when multishot_buffer_sel = '1' else '0'; dpram1_wea <= (samples_wr_en and sync_fifo_valid) or acq_in_trig_tag when multishot_buffer_sel = '1' else '0'; -- ###
-- DPRAMs -- DPRAMs
cmp_multishot_dpram0 : generic_dpram cmp_multishot_dpram0 : generic_dpram
...@@ -1416,8 +1460,13 @@ begin ...@@ -1416,8 +1460,13 @@ begin
wb_ddr_fifo_wr_en <= '0'; wb_ddr_fifo_wr_en <= '0';
elsif rising_edge(sys_clk_i) then elsif rising_edge(sys_clk_i) then
if single_shot = '1' then if single_shot = '1' then
if acq_in_trig_tag = '1' then
wb_ddr_fifo_din <= trig_tag_data; -- ###
wb_ddr_fifo_wr_en <= acq_in_trig_tag; -- ###
else
wb_ddr_fifo_din <= acq_trig & sync_fifo_dout(63 downto 0); -- trigger + data wb_ddr_fifo_din <= acq_trig & sync_fifo_dout(63 downto 0); -- trigger + data
wb_ddr_fifo_wr_en <= samples_wr_en and sync_fifo_valid; wb_ddr_fifo_wr_en <= samples_wr_en and sync_fifo_valid;
end if;
else else
wb_ddr_fifo_din <= '0' & dpram_dout; wb_ddr_fifo_din <= '0' & dpram_dout;
wb_ddr_fifo_wr_en <= dpram_valid; wb_ddr_fifo_wr_en <= dpram_valid;
...@@ -1503,4 +1552,4 @@ begin ...@@ -1503,4 +1552,4 @@ begin
wb_ddr_sel_o <= X"FF"; wb_ddr_sel_o <= X"FF";
end rtl; end rtl;
hdl/adc/rtl/fmc_adc_100Ms_core_pkg.vhd
View file @ b48832a9
...@@ -37,6 +37,8 @@ ...@@ -37,6 +37,8 @@
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all; use IEEE.NUMERIC_STD.all;
use work.timetag_core_pkg.all;
package fmc_adc_100Ms_core_pkg is package fmc_adc_100Ms_core_pkg is
...@@ -85,6 +87,9 @@ package fmc_adc_100Ms_core_pkg is ...@@ -85,6 +87,9 @@ package fmc_adc_100Ms_core_pkg is
acq_stop_p_o : out std_logic; acq_stop_p_o : out std_logic;
acq_end_p_o : out std_logic; acq_end_p_o : out std_logic;
-- Trigger time-tag input
trigger_tag_i : t_timetag;
-- FMC interface -- FMC interface
ext_trigger_p_i : in std_logic; -- External trigger ext_trigger_p_i : in std_logic; -- External trigger
ext_trigger_n_i : in std_logic; ext_trigger_n_i : in std_logic;
......
hdl/adc/rtl/fmc_adc_mezzanine.vhd
View file @ b48832a9
...@@ -43,6 +43,7 @@ use IEEE.NUMERIC_STD.all; ...@@ -43,6 +43,7 @@ use IEEE.NUMERIC_STD.all;
library work; library work;
use work.fmc_adc_100Ms_core_pkg.all; use work.fmc_adc_100Ms_core_pkg.all;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
use work.timetag_core_pkg.all;
entity fmc_adc_mezzanine is entity fmc_adc_mezzanine is
...@@ -83,6 +84,9 @@ entity fmc_adc_mezzanine is ...@@ -83,6 +84,9 @@ entity fmc_adc_mezzanine is
acq_stop_p_o : out std_logic; acq_stop_p_o : out std_logic;
acq_end_p_o : out std_logic; acq_end_p_o : out std_logic;
-- Trigger time-tag input
trigger_tag_i : t_timetag;
-- FMC interface -- FMC interface
ext_trigger_p_i : in std_logic; -- External trigger ext_trigger_p_i : in std_logic; -- External trigger
ext_trigger_n_i : in std_logic; ext_trigger_n_i : in std_logic;
...@@ -399,6 +403,8 @@ begin ...@@ -399,6 +403,8 @@ begin
acq_stop_p_o => acq_stop_p_o, acq_stop_p_o => acq_stop_p_o,
acq_end_p_o => acq_end_p_o, acq_end_p_o => acq_end_p_o,
trigger_tag_i => trigger_tag_i,
ext_trigger_p_i => ext_trigger_p_i, ext_trigger_p_i => ext_trigger_p_i,
ext_trigger_n_i => ext_trigger_n_i, ext_trigger_n_i => ext_trigger_n_i,
......
hdl/adc/rtl/fmc_adc_mezzanine_pkg.vhd
View file @ b48832a9
...@@ -37,6 +37,8 @@ ...@@ -37,6 +37,8 @@
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all; use IEEE.NUMERIC_STD.all;
use work.timetag_core_pkg.all;
package fmc_adc_mezzanine_pkg is package fmc_adc_mezzanine_pkg is
...@@ -86,6 +88,9 @@ package fmc_adc_mezzanine_pkg is ...@@ -86,6 +88,9 @@ package fmc_adc_mezzanine_pkg is
acq_stop_p_o : out std_logic; acq_stop_p_o : out std_logic;
acq_end_p_o : out std_logic; acq_end_p_o : out std_logic;
-- Trigger time-tag input
trigger_tag_i : t_timetag;
-- FMC interface -- FMC interface
ext_trigger_p_i : in std_logic; -- External trigger ext_trigger_p_i : in std_logic; -- External trigger
ext_trigger_n_i : in std_logic; ext_trigger_n_i : in std_logic;
......
hdl/ip_cores/timetag_core/rtl/timetag_core.vhd
View file @ b48832a9
...@@ -38,7 +38,7 @@ ...@@ -38,7 +38,7 @@
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all; use IEEE.NUMERIC_STD.all;
use work.timetag_core_pkg.all;
--library UNISIM; --library UNISIM;
--use UNISIM.vcomponents.all; --use UNISIM.vcomponents.all;
...@@ -56,6 +56,9 @@ entity timetag_core is ...@@ -56,6 +56,9 @@ entity timetag_core is
acq_stop_p_i : in std_logic; acq_stop_p_i : in std_logic;
acq_end_p_i : in std_logic; acq_end_p_i : in std_logic;
-- Trigger time-tag output
trig_tag_o : out t_timetag;
-- Wishbone interface -- Wishbone interface
wb_adr_i : in std_logic_vector(4 downto 0); wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0);
...@@ -124,22 +127,10 @@ architecture rtl of timetag_core is ...@@ -124,22 +127,10 @@ architecture rtl of timetag_core is
signal timetag_coarse_cnt : unsigned(31 downto 0); signal timetag_coarse_cnt : unsigned(31 downto 0);
signal timetag_coarse_load_value : std_logic_vector(31 downto 0); signal timetag_coarse_load_value : std_logic_vector(31 downto 0);
signal timetag_coarse_load_en : std_logic; signal timetag_coarse_load_en : std_logic;
signal timetag_trig_tag_meta : std_logic_vector(31 downto 0); signal trig_tag : t_timetag;
signal timetag_trig_tag_seconds : std_logic_vector(31 downto 0); signal acq_start_tag : t_timetag;
signal timetag_trig_tag_coarse : std_logic_vector(31 downto 0); signal acq_stop_tag : t_timetag;
signal timetag_trig_tag_fine : std_logic_vector(31 downto 0); signal acq_end_tag : t_timetag;
signal timetag_acq_start_tag_meta : std_logic_vector(31 downto 0);
signal timetag_acq_start_tag_seconds : std_logic_vector(31 downto 0);
signal timetag_acq_start_tag_coarse : std_logic_vector(31 downto 0);
signal timetag_acq_start_tag_fine : std_logic_vector(31 downto 0);
signal timetag_acq_stop_tag_meta : std_logic_vector(31 downto 0);
signal timetag_acq_stop_tag_seconds : std_logic_vector(31 downto 0);
signal timetag_acq_stop_tag_coarse : std_logic_vector(31 downto 0);
signal timetag_acq_stop_tag_fine : std_logic_vector(31 downto 0);
signal timetag_acq_end_tag_meta : std_logic_vector(31 downto 0);
signal timetag_acq_end_tag_seconds : std_logic_vector(31 downto 0);
signal timetag_acq_end_tag_coarse : std_logic_vector(31 downto 0);
signal timetag_acq_end_tag_fine : std_logic_vector(31 downto 0);
signal local_pps : std_logic; signal local_pps : std_logic;
...@@ -169,22 +160,22 @@ begin ...@@ -169,22 +160,22 @@ begin
timetag_core_coarse_o => timetag_coarse_load_value, timetag_core_coarse_o => timetag_coarse_load_value,
timetag_core_coarse_i => timetag_coarse, timetag_core_coarse_i => timetag_coarse,
timetag_core_coarse_load_o => timetag_coarse_load_en, timetag_core_coarse_load_o => timetag_coarse_load_en,
timetag_core_trig_tag_meta_i => timetag_trig_tag_meta, timetag_core_trig_tag_meta_i => trig_tag.meta,
timetag_core_trig_tag_seconds_i => timetag_trig_tag_seconds, timetag_core_trig_tag_seconds_i => trig_tag.seconds,
timetag_core_trig_tag_coarse_i => timetag_trig_tag_coarse, timetag_core_trig_tag_coarse_i => trig_tag.coarse,
timetag_core_trig_tag_fine_i => timetag_trig_tag_fine, timetag_core_trig_tag_fine_i => trig_tag.fine,
timetag_core_acq_start_tag_meta_i => timetag_acq_start_tag_meta, timetag_core_acq_start_tag_meta_i => acq_start_tag.meta,
timetag_core_acq_start_tag_seconds_i => timetag_acq_start_tag_seconds, timetag_core_acq_start_tag_seconds_i => acq_start_tag.seconds,
timetag_core_acq_start_tag_coarse_i => timetag_acq_start_tag_coarse, timetag_core_acq_start_tag_coarse_i => acq_start_tag.coarse,
timetag_core_acq_start_tag_fine_i => timetag_acq_start_tag_fine, timetag_core_acq_start_tag_fine_i => acq_start_tag.fine,
timetag_core_acq_stop_tag_meta_i => timetag_acq_stop_tag_meta, timetag_core_acq_stop_tag_meta_i => acq_stop_tag.meta,
timetag_core_acq_stop_tag_seconds_i => timetag_acq_stop_tag_seconds, timetag_core_acq_stop_tag_seconds_i => acq_stop_tag.seconds,
timetag_core_acq_stop_tag_coarse_i => timetag_acq_stop_tag_coarse, timetag_core_acq_stop_tag_coarse_i => acq_stop_tag.coarse,
timetag_core_acq_stop_tag_fine_i => timetag_acq_stop_tag_fine, timetag_core_acq_stop_tag_fine_i => acq_stop_tag.fine,
timetag_core_acq_end_tag_meta_i => timetag_acq_end_tag_meta, timetag_core_acq_end_tag_meta_i => acq_end_tag.meta,
timetag_core_acq_end_tag_seconds_i => timetag_acq_end_tag_seconds, timetag_core_acq_end_tag_seconds_i => acq_end_tag.seconds,
timetag_core_acq_end_tag_coarse_i => timetag_acq_end_tag_coarse, timetag_core_acq_end_tag_coarse_i => acq_end_tag.coarse,
timetag_core_acq_end_tag_fine_i => timetag_acq_end_tag_fine timetag_core_acq_end_tag_fine_i => acq_end_tag.fine
); );
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
...@@ -236,17 +227,18 @@ begin ...@@ -236,17 +227,18 @@ begin
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if rst_n_i = '0' then if rst_n_i = '0' then
timetag_trig_tag_seconds <= (others => '0'); trig_tag.seconds <= (others => '0');
timetag_trig_tag_coarse <= (others => '0'); trig_tag.coarse <= (others => '0');
timetag_trig_tag_fine <= (others => '0'); trig_tag.fine <= (others => '0');
elsif trigger_p_i = '1' then elsif trigger_p_i = '1' then
timetag_trig_tag_seconds <= timetag_seconds; trig_tag.seconds <= timetag_seconds;
timetag_trig_tag_coarse <= timetag_coarse; trig_tag.coarse <= timetag_coarse;
end if; end if;
end if; end if;
end process p_trig_tag; end process p_trig_tag;
timetag_trig_tag_meta <= X"00000000"; trig_tag.meta <= X"00000000";
trig_tag_o <= trig_tag;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Last acquisition start event time-tag -- Last acquisition start event time-tag
...@@ -255,17 +247,17 @@ begin ...@@ -255,17 +247,17 @@ begin
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if rst_n_i = '0' then if rst_n_i = '0' then
timetag_acq_start_tag_seconds <= (others => '0'); acq_start_tag.seconds <= (others => '0');
timetag_acq_start_tag_coarse <= (others => '0'); acq_start_tag.coarse <= (others => '0');
timetag_acq_start_tag_fine <= (others => '0'); acq_start_tag.fine <= (others => '0');
elsif acq_start_p_i = '1' then elsif acq_start_p_i = '1' then
timetag_acq_start_tag_seconds <= timetag_seconds; acq_start_tag.seconds <= timetag_seconds;
timetag_acq_start_tag_coarse <= timetag_coarse; acq_start_tag.coarse <= timetag_coarse;
end if; end if;
end if; end if;
end process p_acq_start_tag; end process p_acq_start_tag;
timetag_acq_start_tag_meta <= X"00000000"; acq_start_tag.meta <= X"00000000";
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Last acquisition stop event time-tag -- Last acquisition stop event time-tag
...@@ -274,17 +266,17 @@ begin ...@@ -274,17 +266,17 @@ begin
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if rst_n_i = '0' then if rst_n_i = '0' then
timetag_acq_stop_tag_seconds <= (others => '0'); acq_stop_tag.seconds <= (others => '0');
timetag_acq_stop_tag_coarse <= (others => '0'); acq_stop_tag.coarse <= (others => '0');
timetag_acq_stop_tag_fine <= (others => '0'); acq_stop_tag.fine <= (others => '0');
elsif acq_stop_p_i = '1' then elsif acq_stop_p_i = '1' then
timetag_acq_stop_tag_seconds <= timetag_seconds; acq_stop_tag.seconds <= timetag_seconds;
timetag_acq_stop_tag_coarse <= timetag_coarse; acq_stop_tag.coarse <= timetag_coarse;
end if; end if;
end if; end if;
end process p_acq_stop_tag; end process p_acq_stop_tag;
timetag_acq_stop_tag_meta <= X"00000000"; acq_stop_tag.meta <= X"00000000";
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Last acquisition end event time-tag -- Last acquisition end event time-tag
...@@ -293,17 +285,17 @@ begin ...@@ -293,17 +285,17 @@ begin
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if rst_n_i = '0' then if rst_n_i = '0' then
timetag_acq_end_tag_seconds <= (others => '0'); acq_end_tag.seconds <= (others => '0');
timetag_acq_end_tag_coarse <= (others => '0'); acq_end_tag.coarse <= (others => '0');
timetag_acq_end_tag_fine <= (others => '0'); acq_end_tag.fine <= (others => '0');
elsif acq_end_p_i = '1' then elsif acq_end_p_i = '1' then
timetag_acq_end_tag_seconds <= timetag_seconds; acq_end_tag.seconds <= timetag_seconds;
timetag_acq_end_tag_coarse <= timetag_coarse; acq_end_tag.coarse <= timetag_coarse;
end if; end if;
end if; end if;
end process p_acq_end_tag; end process p_acq_end_tag;
timetag_acq_end_tag_meta <= X"00000000"; acq_end_tag.meta <= X"00000000";
end rtl; end rtl;
hdl/ip_cores/timetag_core/rtl/timetag_core_pkg.vhd
View file @ b48832a9
...@@ -44,6 +44,15 @@ package timetag_core_pkg is ...@@ -44,6 +44,15 @@ package timetag_core_pkg is
-- Constants declaration -- Constants declaration
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Types declaration
------------------------------------------------------------------------------
type t_timetag is record
meta : std_logic_vector(31 downto 0);
seconds : std_logic_vector(31 downto 0);
coarse : std_logic_vector(31 downto 0);
fine : std_logic_vector(31 downto 0);
end record t_timetag;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Components declaration -- Components declaration
...@@ -60,6 +69,9 @@ package timetag_core_pkg is ...@@ -60,6 +69,9 @@ package timetag_core_pkg is
acq_stop_p_i : in std_logic; acq_stop_p_i : in std_logic;
acq_end_p_i : in std_logic; acq_end_p_i : in std_logic;
-- Trigger time-tag output
trig_tag_o : out t_timetag;
-- Wishbone interface -- Wishbone interface
wb_adr_i : in std_logic_vector(4 downto 0); wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0);
......
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ b48832a9
...@@ -489,6 +489,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is ...@@ -489,6 +489,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal acq_start_p : std_logic; signal acq_start_p : std_logic;
signal acq_stop_p : std_logic; signal acq_stop_p : std_logic;
signal acq_end_p : std_logic; signal acq_end_p : std_logic;
signal trigger_tag : t_timetag;
-- led pwm -- led pwm
signal led_pwm_update_cnt : unsigned(9 downto 0); signal led_pwm_update_cnt : unsigned(9 downto 0);
...@@ -795,6 +796,8 @@ begin ...@@ -795,6 +796,8 @@ begin
acq_stop_p_i => acq_stop_p, acq_stop_p_i => acq_stop_p,
acq_end_p_i => acq_end_p, acq_end_p_i => acq_end_p,
trig_tag_o => trigger_tag,
wb_adr_i => cnx_master_out(c_WB_SLAVE_TIMETAG).adr(6 downto 2), -- cnx_master_out.adr is byte address wb_adr_i => cnx_master_out(c_WB_SLAVE_TIMETAG).adr(6 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_TIMETAG).dat, wb_dat_i => cnx_master_out(c_WB_SLAVE_TIMETAG).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_TIMETAG).dat, wb_dat_o => cnx_master_in(c_WB_SLAVE_TIMETAG).dat,
...@@ -949,6 +952,8 @@ begin ...@@ -949,6 +952,8 @@ begin
acq_stop_p_o => acq_stop_p, acq_stop_p_o => acq_stop_p,
acq_end_p_o => acq_end_p, acq_end_p_o => acq_end_p,
trigger_tag_i => trigger_tag,
ext_trigger_p_i => adc0_ext_trigger_p_i, ext_trigger_p_i => adc0_ext_trigger_p_i,
ext_trigger_n_i => adc0_ext_trigger_n_i, ext_trigger_n_i => adc0_ext_trigger_n_i,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment