This will generate a basic ISE project file with default settings.
If non-default setting is needed (e.g. binary bitstream output file .bin), the project file must be opened using ISE project navigator GUI and the setting changed manually.
@item Generate a synthesis Makefile.@*
@code{hdlmake --make-ise}
@item Check that all dependencies are fetched.@*
@code{hdlmake --list}
@item Synthesis, place and route.@*
@code{make}
@end enumerate
@c TODO specify the hdlmake release (once they have stable version release).
@@ -162,10 +212,13 @@ The @ref{tab:memory_map} shows the Wishbone slaves mapping.
@caption{Wishbone bus memory mapping (BAR 0).}
@end float
@sp 1
The Wishbone crossbar also implements SDB@footnote{@uref{http://www.ohwr.org/projects/fpga-config-space}} records. Those records describe the Wishbone slaves and their mapping on the bus.
The SDB records ROM must be located at offset @code{0x0}.
In order to identify the firmware, SDB meta-information records are used.
The following three meta-information records are used in the design:
The 'Integration', 'Top module repository url' and 'Synthesis tool information' meta-information records are used in the design. Below is a description of the fields and their content in the fmc-adc design.
@table @b
@item Integration
vendor_id = 0x0000CE42 (CERN vendor ID)@*
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@@ -188,13 +241,15 @@ The following three meta-information records are used in the design:
Note that some of the cores from the general-cores library are based on cores from
OpenCores@footnote{@uref{http://opencores.org/}}. Therefore, the documentation for those cores is hosted on the OpenCores website.
The register description for the cores for the carrier control and status, the time-tagging core, the interrupt controller and the ADC core can be found in annexe (@xref{ADC core registers}, @ref{Interrupt controller registers}, @ref{Time-tagging core registers} and @ref{Carrier registers}).
The register description for the cores for the carrier control and status, the time-tagging core, the interrupt controller and the ADC core can be found in annexe (@xref{ADC Core Registers}, @ref{Interrupt Controller Registers}, @ref{Time-tagging Core Registers} and @ref{Carrier Registers}). The registers for those cores have been generated using @command{wbgen2}@footnote{@uref{http://www.ohwr.org/projects/wishbone-gen}}.
The memory controller block is the interface between the 256MB DDR memory located on the SPEC board and the other blocks in the FPGA.
It is basically a MCB core (Memory Controller Block) generated with Xilinx CoreGen and an additional wrapper implementing two Wishbone slave interfaces.
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@@ -326,7 +378,7 @@ Therefore, the samples stored in the DDR memory cannot be read during an acquisi
The interrupt controller purpose is to concentrate several interrupt source into one interrupt request line. It has four interrupt inputs and one interrupt request output.
It also have one interrupt enable mask register and one interrupt source register.
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@@ -350,13 +402,8 @@ To clear a bit in the interrupt source register, a '1' must be written to it.
This interrupt signals the end of an acquisition. In case of multi-shot acquisition, it occurs at the end of the last shot.
On the mezzanine interface side, it takes a data flow from the LTC2174 ADC chip, an external trigger and controls the analogue switches to select the input range or calibration mode.
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@@ -389,7 +436,7 @@ In addition, it outputs the following event as pulses:
The internal detailed functionning of this block is described further in the document(@xref{Configuration}, @ref{Acquisition} and @ref{Calibration}).
This I2C master access the 24AA64 64Kb EEPROM memory chip located on the mezzanine board.
This memory is mandatory as specified in the FMC standard (VITA 57.1). It is connected to the system management I2C bus, also specified in the FMC standard.
The @ref{fig:adc_core_fs_clk} is a block diagram of the ADC core part in the sampling clock domain. It contains a ADC data stream de-serialiser, an offset and gain correction block (for ADC data), an under-sampling block and a trigger unit.
The four channels data and the trigger signal are synchronised to the system clock domain using a FIFO.
The configuration signals coming from registers in the system clock domain are synchronised to the sampling clock within the Wishbone slave (wbgen2@footnote{@uref{http://www.ohwr.org/projects/wishbone-gen}} feature).
The configuration signals coming from registers in the system clock domain are synchronised to the sampling clock within the Wishbone slave (@command{wbgen2} feature).
@@ -655,9 +703,10 @@ Those two counters can be set via the cores's Wishbone interface.
For example, the host computer can use the OS time to set the seconds counter and simply reset the coarse counter.
It is planned, in a later release, to set the time-tagging core counters using the White Rabbit core, for more details @pxref{Missing features & Improvements}.
It is planned, in a later release, to set the time-tagging core counters using the White Rabbit core, for more details @pxref{Missing Features and Improvements}.
@@ -695,9 +744,9 @@ In addition to the calibration values, the EEPROM also contains mandatory IPMI@f
Note that the vendor value 0xCE42 corresponds to CERN. While the device value 0xC5BE045E corresponds to the first 32-bit of the md5 sum of "fmc-adc-100m14b4cha".
@@ -754,7 +804,7 @@ It also explains how the software is expected to control the fmc-adc acquisition
The @ref{fig:adc_core_sys_clk} shows the ADC core acquisition logic.
The heart of the acquisition logic is a state machine driven by user commands (start, stop), the trigger signal and counters events (e.g. pre-trig done, etc...).
The ADC samples are routed along a datapath (bold arrows), which depends on the acquisition mode.
It is explained in detail in the @ref{Single-shot mode} and @ref{Multi-shot mode}.
It is explained in detail in the @ref{Single-shot Mode} and @ref{Multi-shot Mode}.
The four channels data and the trigger are concatenated together and fed to a FIFO to be synchronised between the sampling clock domain and the system clock domain.
Even if the LTC2174 ADC is 14-bit, the data of each channel is stored in a 16-bit word.
Along the datapath, we call @i{sample} a 64-bit vector containing a sample for each channel.
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@@ -778,7 +828,7 @@ The DDR memory size is 2Gb or 256MB.
The acquisition process is driven by a state machine.
The @ref{fig:acq_fsm} represents its states and transitions.
At start-up, the state machine is @code{IDLE}, waiting for an acquisistion start command (@code{ACQ_START}).
Commands are sent to the state machine by writing in the @code{FSM_CMD} field of the control register (@pxref{ADC core registers}).
Commands are sent to the state machine by writing in the @code{FSM_CMD} field of the control register (@pxref{ADC Core Registers}).
When a start command is received, the state machine goes to @code{PRE_TRIG} and stays in this state until the programmed number of pre-trigger samples are recorded.
After that, it goes in @code{WAIT_TRIG} state and continue recording sample to memory.
When a valid trigger is detected, the state machine moves to @code{POST_TRIG}.
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@@ -817,8 +867,8 @@ In addition to the requested pre/post-trigger samples, an addition sample, corre
The multi-shot acquisition process is almost identical to the single-shot one, except that once the acquisition is started it will go around the state machine as many time as the number of configured shots.
It means that if the board is configured for N shots, it will generate N trigger interrupts and then another interrupt at the end of the acquisition.
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@@ -901,15 +951,17 @@ The number of samples per shot stored in memory is equal to: number of pre-trigg
