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FMC ADC 100M 14b 4cha - Gateware
Commit a7445ce9 authored by Matthieu Cattin's avatar Matthieu Cattin
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hdl: Fix software reset field name (add _n for active low signal).

parent 063fb87d
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documentation/manuals/firmware/spec/carrier_csr.tex
View file @ a7445ce9
...@@ -117,7 +117,7 @@ Controls software reset of the mezzanine including the ddr interface and the tim ...@@ -117,7 +117,7 @@ Controls software reset of the mezzanine including the ddr interface and the tim
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name @headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0} @item @code{0}
@tab R/W @tab @tab R/W @tab
@code{FMC0} @code{FMC0_N}
@tab @code{0} @tab @tab @code{0} @tab
State of the reset line State of the reset line
@item @code{20...1} @item @code{20...1}
...@@ -128,6 +128,6 @@ Reserved ...@@ -128,6 +128,6 @@ Reserved
@end multitable @end multitable
@multitable @columnfractions 0.15 0.85 @multitable @columnfractions 0.15 0.85
@headitem Field @tab Description @headitem Field @tab Description
@item @code{fmc0} @tab write 0: FMC is held in reset@* write 1: Normal FMC operation @item @code{fmc0_n} @tab write 0: FMC is held in reset@* write 1: Normal FMC operation
@item @code{reserved} @tab Ignore on read, write with 0's @item @code{reserved} @tab Ignore on read, write with 0's
@end multitable @end multitable
hdl/spec/rtl/carrier_csr.vhd
View file @ a7445ce9
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd -- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb -- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Thu Jul 25 15:15:09 2013 -- Created : Fri Jul 26 16:52:08 2013
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
...@@ -52,7 +52,7 @@ entity carrier_csr is ...@@ -52,7 +52,7 @@ entity carrier_csr is
-- Port for std_logic_vector field: 'Reserved' in reg: 'Control' -- Port for std_logic_vector field: 'Reserved' in reg: 'Control'
carrier_csr_ctrl_reserved_o : out std_logic_vector(28 downto 0); carrier_csr_ctrl_reserved_o : out std_logic_vector(28 downto 0);
-- Port for BIT field: 'State of the reset line' in reg: 'Reset Register' -- Port for BIT field: 'State of the reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc0_o : out std_logic; carrier_csr_rst_fmc0_n_o : out std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Reset Register' -- Port for std_logic_vector field: 'Reserved' in reg: 'Reset Register'
carrier_csr_rst_reserved_o : out std_logic_vector(19 downto 0) carrier_csr_rst_reserved_o : out std_logic_vector(19 downto 0)
); );
...@@ -64,7 +64,7 @@ signal carrier_csr_ctrl_led_green_int : std_logic ; ...@@ -64,7 +64,7 @@ signal carrier_csr_ctrl_led_green_int : std_logic ;
signal carrier_csr_ctrl_led_red_int : std_logic ; signal carrier_csr_ctrl_led_red_int : std_logic ;
signal carrier_csr_ctrl_dac_clr_n_int : std_logic ; signal carrier_csr_ctrl_dac_clr_n_int : std_logic ;
signal carrier_csr_ctrl_reserved_int : std_logic_vector(28 downto 0); signal carrier_csr_ctrl_reserved_int : std_logic_vector(28 downto 0);
signal carrier_csr_rst_fmc0_int : std_logic ; signal carrier_csr_rst_fmc0_n_int : std_logic ;
signal carrier_csr_rst_reserved_int : std_logic_vector(19 downto 0); signal carrier_csr_rst_reserved_int : std_logic_vector(19 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0); signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0); signal rddata_reg : std_logic_vector(31 downto 0);
...@@ -97,7 +97,7 @@ begin ...@@ -97,7 +97,7 @@ begin
carrier_csr_ctrl_led_red_int <= '0'; carrier_csr_ctrl_led_red_int <= '0';
carrier_csr_ctrl_dac_clr_n_int <= '0'; carrier_csr_ctrl_dac_clr_n_int <= '0';
carrier_csr_ctrl_reserved_int <= "00000000000000000000000000000"; carrier_csr_ctrl_reserved_int <= "00000000000000000000000000000";
carrier_csr_rst_fmc0_int <= '0'; carrier_csr_rst_fmc0_n_int <= '0';
carrier_csr_rst_reserved_int <= "00000000000000000000"; carrier_csr_rst_reserved_int <= "00000000000000000000";
elsif rising_edge(clk_sys_i) then elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register -- advance the ACK generator shift register
...@@ -144,10 +144,10 @@ begin ...@@ -144,10 +144,10 @@ begin
ack_in_progress <= '1'; ack_in_progress <= '1';
when "11" => when "11" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
carrier_csr_rst_fmc0_int <= wrdata_reg(0); carrier_csr_rst_fmc0_n_int <= wrdata_reg(0);
carrier_csr_rst_reserved_int <= wrdata_reg(20 downto 1); carrier_csr_rst_reserved_int <= wrdata_reg(20 downto 1);
end if; end if;
rddata_reg(0) <= carrier_csr_rst_fmc0_int; rddata_reg(0) <= carrier_csr_rst_fmc0_n_int;
rddata_reg(20 downto 1) <= carrier_csr_rst_reserved_int; rddata_reg(20 downto 1) <= carrier_csr_rst_reserved_int;
rddata_reg(21) <= 'X'; rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X'; rddata_reg(22) <= 'X';
...@@ -192,7 +192,7 @@ begin ...@@ -192,7 +192,7 @@ begin
-- Reserved -- Reserved
carrier_csr_ctrl_reserved_o <= carrier_csr_ctrl_reserved_int; carrier_csr_ctrl_reserved_o <= carrier_csr_ctrl_reserved_int;
-- State of the reset line -- State of the reset line
carrier_csr_rst_fmc0_o <= carrier_csr_rst_fmc0_int; carrier_csr_rst_fmc0_n_o <= carrier_csr_rst_fmc0_n_int;
-- Reserved -- Reserved
carrier_csr_rst_reserved_o <= carrier_csr_rst_reserved_int; carrier_csr_rst_reserved_o <= carrier_csr_rst_reserved_int;
rwaddr_reg <= wb_adr_i; rwaddr_reg <= wb_adr_i;
......
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ a7445ce9
...@@ -196,7 +196,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is ...@@ -196,7 +196,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
carrier_csr_ctrl_led_red_o : out std_logic; carrier_csr_ctrl_led_red_o : out std_logic;
carrier_csr_ctrl_dac_clr_n_o : out std_logic; carrier_csr_ctrl_dac_clr_n_o : out std_logic;
carrier_csr_ctrl_reserved_o : out std_logic_vector(28 downto 0); carrier_csr_ctrl_reserved_o : out std_logic_vector(28 downto 0);
carrier_csr_rst_fmc0_o : out std_logic; carrier_csr_rst_fmc0_n_o : out std_logic;
carrier_csr_rst_reserved_o : out std_logic_vector(19 downto 0) carrier_csr_rst_reserved_o : out std_logic_vector(19 downto 0)
); );
end component carrier_csr; end component carrier_csr;
...@@ -373,7 +373,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is ...@@ -373,7 +373,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
-- Reset -- Reset
signal powerup_reset_cnt : unsigned(7 downto 0) := "00000000"; signal powerup_reset_cnt : unsigned(7 downto 0) := "00000000";
signal powerup_rst_n : std_logic := '0'; signal powerup_rst_n : std_logic := '0';
signal sw_rst_fmc0 : std_logic; signal sw_rst_fmc0_n : std_logic;
signal sys_rst_n : std_logic; signal sys_rst_n : std_logic;
signal fmc0_rst_n : std_logic; signal fmc0_rst_n : std_logic;
...@@ -564,7 +564,7 @@ begin ...@@ -564,7 +564,7 @@ begin
end process; end process;
sys_rst_n <= powerup_rst_n; sys_rst_n <= powerup_rst_n;
fmc0_rst_n <= powerup_rst_n and sw_rst_fmc0; fmc0_rst_n <= powerup_rst_n and sw_rst_fmc0_n;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- GN4124 interface -- GN4124 interface
...@@ -735,7 +735,7 @@ begin ...@@ -735,7 +735,7 @@ begin
carrier_csr_ctrl_led_red_o => led_red, carrier_csr_ctrl_led_red_o => led_red,
carrier_csr_ctrl_dac_clr_n_o => open, carrier_csr_ctrl_dac_clr_n_o => open,
carrier_csr_ctrl_reserved_o => open, carrier_csr_ctrl_reserved_o => open,
carrier_csr_rst_fmc0_o => sw_rst_fmc0, carrier_csr_rst_fmc0_n_o => sw_rst_fmc0_n,
carrier_csr_rst_reserved_o => open carrier_csr_rst_reserved_o => open
); );
......
hdl/spec/spec_top_fmc_adc_100Ms.ucf
View file @ a7445ce9
...@@ -656,5 +656,5 @@ NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/mem ...@@ -656,5 +656,5 @@ NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/mem
# Reset # Reset
NET "powerup_rst_n" TIG; NET "powerup_rst_n" TIG;
NET "cmp_carrier_csr/carrier_csr_rst_fmc0_int" TIG; NET "cmp_carrier_csr/carrier_csr_rst_fmc0_n_int" TIG;
hdl/spec/wb_gen/carrier_csr.h
View file @ a7445ce9
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* File : carrier_csr.h * File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb * Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Thu Jul 25 15:15:09 2013 * Created : Fri Jul 26 16:52:08 2013
* Standard : ANSI C * Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
...@@ -91,7 +91,7 @@ ...@@ -91,7 +91,7 @@
/* definitions for register: Reset Register */ /* definitions for register: Reset Register */
/* definitions for field: State of the reset line in reg: Reset Register */ /* definitions for field: State of the reset line in reg: Reset Register */
#define CARRIER_CSR_RST_FMC0 WBGEN2_GEN_MASK(0, 1) #define CARRIER_CSR_RST_FMC0_N WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Reserved in reg: Reset Register */ /* definitions for field: Reserved in reg: Reset Register */
#define CARRIER_CSR_RST_RESERVED_MASK WBGEN2_GEN_MASK(1, 20) #define CARRIER_CSR_RST_RESERVED_MASK WBGEN2_GEN_MASK(1, 20)
......
hdl/spec/wb_gen/carrier_csr.htm
View file @ a7445ce9
...@@ -463,7 +463,7 @@ carrier_csr_ctrl_reserved_o[28:0] ...@@ -463,7 +463,7 @@ carrier_csr_ctrl_reserved_o[28:0]
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
carrier_csr_rst_fmc0_o carrier_csr_rst_fmc0_n_o
</td> </td>
<td class="td_arrow_right"> <td class="td_arrow_right">
&rarr; &rarr;
...@@ -1532,7 +1532,7 @@ RESERVED[14:7] ...@@ -1532,7 +1532,7 @@ RESERVED[14:7]
RESERVED[6:0] RESERVED[6:0]
</td> </td>
<td style="border: solid 1px black;" colspan=1 class="td_field"> <td style="border: solid 1px black;" colspan=1 class="td_field">
FMC0 FMC0_N
</td> </td>
<td > <td >
...@@ -1556,7 +1556,7 @@ FMC0 ...@@ -1556,7 +1556,7 @@ FMC0
</table> </table>
<ul> <ul>
<li><b> <li><b>
FMC0 FMC0_N
</b>[<i>read/write</i>]: State of the reset line </b>[<i>read/write</i>]: State of the reset line
<br>write 0: FMC is held in reset<br> write 1: Normal FMC operation <br>write 0: FMC is held in reset<br> write 1: Normal FMC operation
<li><b> <li><b>
......
hdl/spec/wb_gen/carrier_csr.wb
View file @ a7445ce9
...@@ -144,7 +144,7 @@ peripheral { ...@@ -144,7 +144,7 @@ peripheral {
write 1: Normal FMC operation"; write 1: Normal FMC operation";
type = BIT; type = BIT;
size = 1; size = 1;
prefix = "fmc0"; prefix = "fmc0_n";
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
......
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