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FMC ADC 100M 14b 4cha - Gateware
Commit a1755df7 authored by Matthieu Cattin's avatar Matthieu Cattin
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hdl: Change interrupt controller for the wbgen2 one (level output).

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hdl/svec/rtl/Manifest.py
View file @ a1755df7
......@@ -2,7 +2,6 @@ files = [
"svec_top_fmc_adc_100Ms.vhd",
"carrier_csr.vhd",
"irq_controller.vhd",
"irq_controller_regs.vhd",
"bicolor_led_ctrl.vhd",
"bicolor_led_ctrl_pkg.vhd",
"sdb_meta_pkg.vhd"]
hdl/svec/rtl/irq_controller.vhd
View file @ a1755df7
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- IRQ controller
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: irq_controller (irq_controller.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 18-11-2011
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--library UNISIM;
--use UNISIM.vcomponents.all;
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Interrupt controller
---------------------------------------------------------------------------------------
-- File : ../rtl/irq_controller.vhd
-- Author : auto-generated by wbgen2 from irq_controller.wb
-- Created : Mon Jul 22 11:13:45 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
entity irq_controller is
port (
-- Clock, reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Interrupt sources input, must be 1 clk_i tick long
irq_src_p_i : in std_logic_vector(31 downto 0);
-- IRQ pulse output
irq_p_o : out std_logic;
-- Wishbone interface
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic
);
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
irq_fmc0_trig_i : in std_logic;
irq_fmc0_acq_end_i : in std_logic;
irq_fmc1_trig_i : in std_logic;
irq_fmc1_acq_end_i : in std_logic
);
end irq_controller;
architecture syn of irq_controller is
architecture rtl of irq_controller is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component irq_controller_regs
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
irq_ctrl_multi_irq_o : out std_logic_vector(31 downto 0);
irq_ctrl_multi_irq_i : in std_logic_vector(31 downto 0);
irq_ctrl_multi_irq_load_o : out std_logic;
irq_ctrl_src_o : out std_logic_vector(31 downto 0);
irq_ctrl_src_i : in std_logic_vector(31 downto 0);
irq_ctrl_src_load_o : out std_logic;
irq_ctrl_en_mask_o : out std_logic_vector(31 downto 0)
);
end component irq_controller_regs;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal irq_en_mask : std_logic_vector(31 downto 0);
signal irq_pending : std_logic_vector(31 downto 0);
signal irq_pending_d : std_logic_vector(31 downto 0);
signal irq_pending_re : std_logic_vector(31 downto 0);
signal irq_src_rst : std_logic_vector(31 downto 0);
signal irq_src_rst_en : std_logic;
signal multi_irq : std_logic_vector(31 downto 0);
signal multi_irq_rst : std_logic_vector(31 downto 0);
signal multi_irq_rst_en : std_logic;
signal irq_p_or : std_logic_vector(32 downto 0);
signal eic_idr_int : std_logic_vector(3 downto 0);
signal eic_idr_write_int : std_logic ;
signal eic_ier_int : std_logic_vector(3 downto 0);
signal eic_ier_write_int : std_logic ;
signal eic_imr_int : std_logic_vector(3 downto 0);
signal eic_isr_clear_int : std_logic_vector(3 downto 0);
signal eic_isr_status_int : std_logic_vector(3 downto 0);
signal eic_irq_ack_int : std_logic_vector(3 downto 0);
signal eic_isr_write_int : std_logic ;
signal irq_inputs_vector_int : std_logic_vector(3 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
------------------------------------------------------------------------------
-- Wishbone interface to IRQ controller registers
------------------------------------------------------------------------------
cmp_irq_controller_regs : irq_controller_regs
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
wb_adr_i => wb_adr_i,
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
wb_stall_o => open,
irq_ctrl_multi_irq_o => multi_irq_rst,
irq_ctrl_multi_irq_load_o => multi_irq_rst_en,
irq_ctrl_multi_irq_i => multi_irq,
irq_ctrl_src_o => irq_src_rst,
irq_ctrl_src_i => irq_pending,
irq_ctrl_src_load_o => irq_src_rst_en,
irq_ctrl_en_mask_o => irq_en_mask
);
------------------------------------------------------------------------------
-- Register interrupt sources
-- IRQ is pending until a '1' is written to the corresponding bit
------------------------------------------------------------------------------
p_irq_src : process (clk_i)
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if rising_edge(clk_i) then
for I in 0 to irq_pending'length-1 loop
if rst_n_i = '0' then
irq_pending(I) <= '0';
elsif irq_src_p_i(I) = '1' and irq_en_mask(I) = '1' then
irq_pending(I) <= '1';
elsif irq_src_rst_en = '1' and irq_src_rst(I) = '1' then
irq_pending(I) <= '0';
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
ack_in_progress <= '0';
else
end if;
end loop; -- I
end if;
end process p_irq_src;
------------------------------------------------------------------------------
-- Multiple interrupt detection
-- Rise a flag if an interrupt occurs while an irq is still pending
-- Write '1' to the flag to clear it
------------------------------------------------------------------------------
p_multi_irq_detect : process (clk_i)
begin
if rising_edge(clk_i) then
for I in 0 to multi_irq'length-1 loop
if rst_n_i = '0' then
multi_irq(I) <= '0';
elsif irq_src_p_i(I) = '1' and irq_pending(I) = '1' then
multi_irq(I) <= '1';
elsif multi_irq_rst_en = '1' and multi_irq_rst(I) = '1' then
multi_irq(I) <= '0';
end if;
end loop; -- I
end if;
end process p_multi_irq_detect;
------------------------------------------------------------------------------
-- Generate IRQ output pulse
------------------------------------------------------------------------------
irq_p_or(0) <= '0';
l_irq_out_pulse : for I in 0 to irq_src_p_i'length-1 generate
irq_p_or(I+1) <= irq_p_or(I) or (irq_src_p_i(I) and irq_en_mask(I));
end generate l_irq_out_pulse;
p_irq_out_pulse : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
irq_p_o <= '0';
else
irq_p_o <= irq_p_or(32);
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
eic_ier_write_int <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
end if;
rddata_reg(3 downto 0) <= eic_imr_int(3 downto 0);
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
end if;
rddata_reg(3 downto 0) <= eic_isr_status_int(3 downto 0);
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process p_irq_out_pulse;
end rtl;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(3 downto 0) <= wrdata_reg(3 downto 0);
-- extra code for reg/fifo/mem: Interrupt enable register
eic_ier_int(3 downto 0) <= wrdata_reg(3 downto 0);
-- extra code for reg/fifo/mem: Interrupt status register
eic_isr_clear_int(3 downto 0) <= wrdata_reg(3 downto 0);
-- extra code for reg/fifo/mem: IRQ_CONTROLLER
eic_irq_controller_inst : wbgen2_eic
generic map (
g_num_interrupts => 4,
g_irq00_mode => 0,
g_irq01_mode => 0,
g_irq02_mode => 0,
g_irq03_mode => 0,
g_irq04_mode => 0,
g_irq05_mode => 0,
g_irq06_mode => 0,
g_irq07_mode => 0,
g_irq08_mode => 0,
g_irq09_mode => 0,
g_irq0a_mode => 0,
g_irq0b_mode => 0,
g_irq0c_mode => 0,
g_irq0d_mode => 0,
g_irq0e_mode => 0,
g_irq0f_mode => 0,
g_irq10_mode => 0,
g_irq11_mode => 0,
g_irq12_mode => 0,
g_irq13_mode => 0,
g_irq14_mode => 0,
g_irq15_mode => 0,
g_irq16_mode => 0,
g_irq17_mode => 0,
g_irq18_mode => 0,
g_irq19_mode => 0,
g_irq1a_mode => 0,
g_irq1b_mode => 0,
g_irq1c_mode => 0,
g_irq1d_mode => 0,
g_irq1e_mode => 0,
g_irq1f_mode => 0
)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
irq_i => irq_inputs_vector_int,
irq_ack_o => eic_irq_ack_int,
reg_imr_o => eic_imr_int,
reg_ier_i => eic_ier_int,
reg_ier_wr_stb_i => eic_ier_write_int,
reg_idr_i => eic_idr_int,
reg_idr_wr_stb_i => eic_idr_write_int,
reg_isr_o => eic_isr_status_int,
reg_isr_i => eic_isr_clear_int,
reg_isr_wr_stb_i => eic_isr_write_int,
wb_irq_o => wb_int_o
);
irq_inputs_vector_int(0) <= irq_fmc0_trig_i;
irq_inputs_vector_int(1) <= irq_fmc0_acq_end_i;
irq_inputs_vector_int(2) <= irq_fmc1_trig_i;
irq_inputs_vector_int(3) <= irq_fmc1_acq_end_i;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
View file @ a1755df7
......@@ -278,21 +278,26 @@ architecture rtl of svec_top_fmc_adc_100Ms is
component irq_controller
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
irq_src_p_i : in std_logic_vector(31 downto 0);
irq_p_o : out std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
irq_fmc0_trig_i : in std_logic;
irq_fmc0_acq_end_i : in std_logic;
irq_fmc1_trig_i : in std_logic;
irq_fmc1_acq_end_i : in std_logic
);
end component irq_controller;
------------------------------------------------------------------------------
-- SDB crossbar constants declaration
--
......@@ -557,15 +562,17 @@ architecture rtl of svec_top_fmc_adc_100Ms is
signal wb_ddr1_adc_stall : std_logic;
-- Interrupts stuff
signal irq_sources : std_logic_vector(31 downto 0);
signal irq_to_vme : std_logic;
signal irq_sources_2_led : std_logic_vector(31 downto 0);
signal ddr_wr_fifo_empty : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal ddr_wr_fifo_empty_d : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal ddr_wr_fifo_empty_d1 : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal ddr_wr_fifo_empty_p : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal acq_end_irq_p : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal acq_end_extend : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal fmc0_trig_irq_led : std_logic;
signal fmc0_acq_end_irq_led : std_logic;
signal irq_to_vme : std_logic;
signal irq_to_vme_t : std_logic;
signal irq_to_vme_sync : std_logic;
-- Front panel LED control
signal led_state : std_logic_vector(15 downto 0);
......@@ -716,7 +723,7 @@ begin
------------------------------------------------------------------------------
-- VME interface
------------------------------------------------------------------------------
cmp_vme_Core : xvme64x_core
cmp_vme_core : xvme64x_core
port map (
clk_i => sys_clk_62_5,
rst_n_i => powerup_rst_n,
......@@ -747,7 +754,7 @@ begin
VME_ADDR_OE_N_o => vme_addr_oe_n_o,
master_o => vme_master_out,
master_i => vme_master_in,
irq_i => irq_to_vme
irq_i => irq_to_vme_sync
);
-- VME tri-state buffers
......@@ -778,6 +785,18 @@ begin
cnx_slave_in(c_WB_MASTER_VME) <= vme_sync_master_out;
vme_sync_master_in <= cnx_slave_out(c_WB_MASTER_VME);
-- Interrupt line synchronisation to vme 62.5MHz
p_irq_to_vme_sync : process (sys_clk_62_5)
begin
if powerup_rst_n = '0' then
irq_to_vme_t <= '0';
irq_to_vme_sync <= '0';
elsif rising_edge(sys_clk_62_5) then
irq_to_vme_t <= irq_to_vme;
irq_to_vme_sync <= irq_to_vme_t;
end if;
end process p_irq_to_vme_sync;
------------------------------------------------------------------------------
-- CSR wishbone crossbar
......@@ -901,37 +920,27 @@ begin
------------------------------------------------------------------------------
cmp_irq_controller : irq_controller
port map(
clk_i => sys_clk_125,
rst_n_i => sys_rst_n,
irq_src_p_i => irq_sources,
irq_p_o => irq_to_vme,
wb_adr_i => cnx_master_out(c_WB_SLAVE_INT).adr(3 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_INT).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_INT).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_INT).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_INT).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_INT).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_INT).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_INT).ack
rst_n_i => sys_rst_n,
clk_sys_i => sys_clk_125,
wb_adr_i => cnx_master_out(c_WB_SLAVE_INT).adr(3 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_INT).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_INT).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_INT).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_INT).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_INT).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_INT).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_INT).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_INT).stall,
wb_int_o => irq_to_vme,
irq_fmc0_trig_i => trig_p(0),
irq_fmc0_acq_end_i => acq_end_irq_p(0),
irq_fmc1_trig_i => trig_p(1),
irq_fmc1_acq_end_i => acq_end_irq_p(1)
);
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_INT).err <= '0';
cnx_master_in(c_WB_SLAVE_INT).rty <= '0';
cnx_master_in(c_WB_SLAVE_INT).stall <= '0';
cnx_master_in(c_WB_SLAVE_INT).int <= '0';
-- IRQ sources
-- 0 -> FMC slot 1 trigger
-- 1 -> FMC slot 1 end of acquisition (data written to DDR)
-- 2 -> FMC slot 2 trigger
-- 3 -> FMC slot 2 end of acquisition (data written to DDR)
-- 4-31 -> Unused
irq_sources(0) <= trig_p(0);
irq_sources(1) <= acq_end_irq_p(0);
irq_sources(2) <= trig_p(1);
irq_sources(3) <= acq_end_irq_p(1);
irq_sources(31 downto 4) <= (others => '0');
cnx_master_in(c_WB_SLAVE_INT).err <= '0';
cnx_master_in(c_WB_SLAVE_INT).rty <= '0';
-- Detects end of adc core writing to ddr
l_ddr_wr_fifo_empty : for I in 0 to c_NB_FMC_SLOTS-1 generate
......@@ -1527,7 +1536,7 @@ begin
line_oen_o => fp_led_line_oen_o
);
cmp_vme_access_Led : gc_extend_pulse
cmp_vme_access_led : gc_extend_pulse
generic map (
g_width => 5000000)
port map (
......@@ -1537,6 +1546,26 @@ begin
extended_o => vme_access
);
cmp_fmc0_trig_irq_led : gc_extend_pulse
generic map (
g_width => 5000000)
port map (
clk_i => sys_clk_125,
rst_n_i => sys_rst_n,
pulse_i => trig_p(0),
extended_o => fmc0_trig_irq_led
);
cmp_fmc0_acq_end_irq_led : gc_extend_pulse
generic map (
g_width => 5000000)
port map (
clk_i => sys_clk_125,
rst_n_i => sys_rst_n,
pulse_i => acq_end_irq_p(0),
extended_o => fmc0_acq_end_irq_led
);
-- LED 1 : VME access
led_state(1 downto 0) <= c_LED_GREEN when vme_access = '1' else c_LED_OFF;
......@@ -1549,19 +1578,19 @@ begin
-- LED 4 :
led_state(7 downto 6) <= '0' & led_pwm;
led_state(15 downto 8) <= led_state_man(15 downto 8);
-- LED 5 :
--led_state(9 downto 8) <= c_LED_OFF;
led_state(9 downto 8) <= fmc0_trig_irq_led & '0';
-- LED 6 :
--led_state(11 downto 10) <= c_LED_OFF;
led_state(11 downto 10) <= fmc0_acq_end_irq_led & '0';
-- LED 7 :
--led_state(13 downto 12) <= c_LED_OFF;
led_state(13 downto 12) <= '0' & cnx_master_in(c_WB_SLAVE_INT).int;
-- LED 8 :
--led_state(15 downto 14) <= c_LED_OFF;
led_state(15 downto 14) <= '0' & irq_to_vme_sync;
--led_state(15 downto 12) <= led_state_man(15 downto 12);
------------------------------------------------------------------------------
-- FPGA loaded led (heart beat)
......
hdl/svec/wb_gen/Makefile
View file @ a1755df7
......@@ -9,3 +9,7 @@ carrier_csr:
irq_controller_regs:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
irq_controller:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
\ No newline at end of file
hdl/svec/wb_gen/irq_controller.h 0 → 100644
View file @ a1755df7
/*
Register definitions for slave core: Interrupt controller
* File : irq_controller.h
* Author : auto-generated by wbgen2 from irq_controller.wb
* Created : Mon Jul 22 11:13:45 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_IRQ_CONTROLLER_WB
#define __WBGEN2_REGDEFS_IRQ_CONTROLLER_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Interrupt disable register */
/* definitions for field: FMC slot 1 trigger interrupt in reg: Interrupt disable register */
#define IRQ_CTRL_EIC_IDR_FMC0_TRIG WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC slot 1 end of acquisition interrupt in reg: Interrupt disable register */
#define IRQ_CTRL_EIC_IDR_FMC0_ACQ_END WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC slot 2 trigger interrupt in reg: Interrupt disable register */
#define IRQ_CTRL_EIC_IDR_FMC1_TRIG WBGEN2_GEN_MASK(2, 1)
/* definitions for field: FMC slot 2 end of acquisition interrupt in reg: Interrupt disable register */
#define IRQ_CTRL_EIC_IDR_FMC1_ACQ_END WBGEN2_GEN_MASK(3, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: FMC slot 1 trigger interrupt in reg: Interrupt enable register */
#define IRQ_CTRL_EIC_IER_FMC0_TRIG WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC slot 1 end of acquisition interrupt in reg: Interrupt enable register */
#define IRQ_CTRL_EIC_IER_FMC0_ACQ_END WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC slot 2 trigger interrupt in reg: Interrupt enable register */
#define IRQ_CTRL_EIC_IER_FMC1_TRIG WBGEN2_GEN_MASK(2, 1)
/* definitions for field: FMC slot 2 end of acquisition interrupt in reg: Interrupt enable register */
#define IRQ_CTRL_EIC_IER_FMC1_ACQ_END WBGEN2_GEN_MASK(3, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: FMC slot 1 trigger interrupt in reg: Interrupt mask register */
#define IRQ_CTRL_EIC_IMR_FMC0_TRIG WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC slot 1 end of acquisition interrupt in reg: Interrupt mask register */
#define IRQ_CTRL_EIC_IMR_FMC0_ACQ_END WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC slot 2 trigger interrupt in reg: Interrupt mask register */
#define IRQ_CTRL_EIC_IMR_FMC1_TRIG WBGEN2_GEN_MASK(2, 1)
/* definitions for field: FMC slot 2 end of acquisition interrupt in reg: Interrupt mask register */
#define IRQ_CTRL_EIC_IMR_FMC1_ACQ_END WBGEN2_GEN_MASK(3, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: FMC slot 1 trigger interrupt in reg: Interrupt status register */
#define IRQ_CTRL_EIC_ISR_FMC0_TRIG WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC slot 1 end of acquisition interrupt in reg: Interrupt status register */
#define IRQ_CTRL_EIC_ISR_FMC0_ACQ_END WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC slot 2 trigger interrupt in reg: Interrupt status register */
#define IRQ_CTRL_EIC_ISR_FMC1_TRIG WBGEN2_GEN_MASK(2, 1)
/* definitions for field: FMC slot 2 end of acquisition interrupt in reg: Interrupt status register */
#define IRQ_CTRL_EIC_ISR_FMC1_ACQ_END WBGEN2_GEN_MASK(3, 1)
PACKED struct IRQ_CTRL_WB {
/* [0x0]: REG Interrupt disable register */
uint32_t EIC_IDR;
/* [0x4]: REG Interrupt enable register */
uint32_t EIC_IER;
/* [0x8]: REG Interrupt mask register */
uint32_t EIC_IMR;
/* [0xc]: REG Interrupt status register */
uint32_t EIC_ISR;
};
#endif
hdl/svec/wb_gen/irq_controller.htm 0 → 100644
View file @ a1755df7
<HTML>
<HEAD>
<TITLE>irq_controller</TITLE>
<STYLE TYPE="text/css" MEDIA="all">
<!--
BODY { background: white; color: black;
font-family: Arial,Helvetica; font-size:12; }
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h2 { font-family: Trebuchet MS,Arial,Helvetica; font-size:22; color:#404040; }
h3 { font-family: Trebuchet MS,Arial,Helvetica; font-size:16; color:#404040; }
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</STYLE>
</HEAD>
<BODY>
<h1 class="heading">irq_controller</h1>
<h3>Interrupt controller</h3>
<p>Fmc-adc interrrupt controller for SVEC.</p>
<h3>Contents:</h3>
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">Interrupt disable register</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Interrupt enable register</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">Interrupt mask register</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">Interrupt status register</a></span><br/>
<span style="margin-left: 0px; ">5. <A href="#sect_5_0">Interrupts</a></span><br/>
<span style="margin-left: 20px; ">5.1. <A href="#sect_5_1">FMC slot 1 trigger interrupt</a></span><br/>
<span style="margin-left: 20px; ">5.2. <A href="#sect_5_2">FMC slot 1 end of acquisition interrupt</a></span><br/>
<span style="margin-left: 20px; ">5.3. <A href="#sect_5_3">FMC slot 2 trigger interrupt</a></span><br/>
<span style="margin-left: 20px; ">5.4. <A href="#sect_5_4">FMC slot 2 end of acquisition interrupt</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<th >
H/W Address
</th>
<th >
Type
</th>
<th >
Name
</th>
<th >
VHDL/Verilog prefix
</th>
<th >
C prefix
</th>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x0
</td>
<td >
REG
</td>
<td >
<A href="#EIC_IDR">Interrupt disable register</a>
</td>
<td class="td_code">
irq_ctrl_eic_idr
</td>
<td class="td_code">
EIC_IDR
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x1
</td>
<td >
REG
</td>
<td >
<A href="#EIC_IER">Interrupt enable register</a>
</td>
<td class="td_code">
irq_ctrl_eic_ier
</td>
<td class="td_code">
EIC_IER
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x2
</td>
<td >
REG
</td>
<td >
<A href="#EIC_IMR">Interrupt mask register</a>
</td>
<td class="td_code">
irq_ctrl_eic_imr
</td>
<td class="td_code">
EIC_IMR
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x3
</td>
<td >
REG
</td>
<td >
<A href="#EIC_ISR">Interrupt status register</a>
</td>
<td class="td_code">
irq_ctrl_eic_isr
</td>
<td class="td_code">
EIC_ISR
</td>
</tr>
</table>
<h3><a name="sect_2_0">2. HDL symbol</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
rst_n_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>FMC slot 1 trigger interrupt:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
clk_sys_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
irq_fmc0_trig_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_adr_i[1:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_dat_i[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>FMC slot 1 end of acquisition interrupt:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&lArr;
</td>
<td class="td_pblock_left">
wb_dat_o[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
irq_fmc0_acq_end_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_cyc_i
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_sel_i[3:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>FMC slot 2 trigger interrupt:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_stb_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
irq_fmc1_trig_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_we_i
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_ack_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>FMC slot 2 end of acquisition interrupt:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_stall_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
irq_fmc1_acq_end_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_int_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="EIC_IDR"></a>
<h3><a name="sect_3_1">3.1. Interrupt disable register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
irq_ctrl_eic_idr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
EIC_IDR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
</table>
<p>
Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC1_ACQ_END
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC1_TRIG
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC0_ACQ_END
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC0_TRIG
</td>
</tr>
</table>
<ul>
<li><b>
FMC0_TRIG
</b>[<i>write-only</i>]: FMC slot 1 trigger interrupt
<br>write 1: disable interrupt 'FMC slot 1 trigger interrupt'<br>write 0: no effect
<li><b>
FMC0_ACQ_END
</b>[<i>write-only</i>]: FMC slot 1 end of acquisition interrupt
<br>write 1: disable interrupt 'FMC slot 1 end of acquisition interrupt'<br>write 0: no effect
<li><b>
FMC1_TRIG
</b>[<i>write-only</i>]: FMC slot 2 trigger interrupt
<br>write 1: disable interrupt 'FMC slot 2 trigger interrupt'<br>write 0: no effect
<li><b>
FMC1_ACQ_END
</b>[<i>write-only</i>]: FMC slot 2 end of acquisition interrupt
<br>write 1: disable interrupt 'FMC slot 2 end of acquisition interrupt'<br>write 0: no effect
</ul>
<a name="EIC_IER"></a>
<h3><a name="sect_3_2">3.2. Interrupt enable register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
irq_ctrl_eic_ier
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x1
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
EIC_IER
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
</table>
<p>
Writing 1 enables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC1_ACQ_END
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC1_TRIG
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC0_ACQ_END
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC0_TRIG
</td>
</tr>
</table>
<ul>
<li><b>
FMC0_TRIG
</b>[<i>write-only</i>]: FMC slot 1 trigger interrupt
<br>write 1: enable interrupt 'FMC slot 1 trigger interrupt'<br>write 0: no effect
<li><b>
FMC0_ACQ_END
</b>[<i>write-only</i>]: FMC slot 1 end of acquisition interrupt
<br>write 1: enable interrupt 'FMC slot 1 end of acquisition interrupt'<br>write 0: no effect
<li><b>
FMC1_TRIG
</b>[<i>write-only</i>]: FMC slot 2 trigger interrupt
<br>write 1: enable interrupt 'FMC slot 2 trigger interrupt'<br>write 0: no effect
<li><b>
FMC1_ACQ_END
</b>[<i>write-only</i>]: FMC slot 2 end of acquisition interrupt
<br>write 1: enable interrupt 'FMC slot 2 end of acquisition interrupt'<br>write 0: no effect
</ul>
<a name="EIC_IMR"></a>
<h3><a name="sect_3_3">3.3. Interrupt mask register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
irq_ctrl_eic_imr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x2
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
EIC_IMR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x8
</td>
</tr>
</table>
<p>
Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC1_ACQ_END
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC1_TRIG
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC0_ACQ_END
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC0_TRIG
</td>
</tr>
</table>
<ul>
<li><b>
FMC0_TRIG
</b>[<i>read-only</i>]: FMC slot 1 trigger interrupt
<br>read 1: interrupt 'FMC slot 1 trigger interrupt' is enabled<br>read 0: interrupt 'FMC slot 1 trigger interrupt' is disabled
<li><b>
FMC0_ACQ_END
</b>[<i>read-only</i>]: FMC slot 1 end of acquisition interrupt
<br>read 1: interrupt 'FMC slot 1 end of acquisition interrupt' is enabled<br>read 0: interrupt 'FMC slot 1 end of acquisition interrupt' is disabled
<li><b>
FMC1_TRIG
</b>[<i>read-only</i>]: FMC slot 2 trigger interrupt
<br>read 1: interrupt 'FMC slot 2 trigger interrupt' is enabled<br>read 0: interrupt 'FMC slot 2 trigger interrupt' is disabled
<li><b>
FMC1_ACQ_END
</b>[<i>read-only</i>]: FMC slot 2 end of acquisition interrupt
<br>read 1: interrupt 'FMC slot 2 end of acquisition interrupt' is enabled<br>read 0: interrupt 'FMC slot 2 end of acquisition interrupt' is disabled
</ul>
<a name="EIC_ISR"></a>
<h3><a name="sect_3_4">3.4. Interrupt status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
irq_ctrl_eic_isr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x3
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
EIC_ISR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0xc
</td>
</tr>
</table>
<p>
Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC1_ACQ_END
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC1_TRIG
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC0_ACQ_END
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC0_TRIG
</td>
</tr>
</table>
<ul>
<li><b>
FMC0_TRIG
</b>[<i>read/write</i>]: FMC slot 1 trigger interrupt
<br>read 1: interrupt 'FMC slot 1 trigger interrupt' is pending<br>read 0: interrupt not pending<br>write 1: clear interrupt 'FMC slot 1 trigger interrupt'<br>write 0: no effect
<li><b>
FMC0_ACQ_END
</b>[<i>read/write</i>]: FMC slot 1 end of acquisition interrupt
<br>read 1: interrupt 'FMC slot 1 end of acquisition interrupt' is pending<br>read 0: interrupt not pending<br>write 1: clear interrupt 'FMC slot 1 end of acquisition interrupt'<br>write 0: no effect
<li><b>
FMC1_TRIG
</b>[<i>read/write</i>]: FMC slot 2 trigger interrupt
<br>read 1: interrupt 'FMC slot 2 trigger interrupt' is pending<br>read 0: interrupt not pending<br>write 1: clear interrupt 'FMC slot 2 trigger interrupt'<br>write 0: no effect
<li><b>
FMC1_ACQ_END
</b>[<i>read/write</i>]: FMC slot 2 end of acquisition interrupt
<br>read 1: interrupt 'FMC slot 2 end of acquisition interrupt' is pending<br>read 0: interrupt not pending<br>write 1: clear interrupt 'FMC slot 2 end of acquisition interrupt'<br>write 0: no effect
</ul>
<h3><a name="sect_5_0">5. Interrupts</a></h3>
<a name="FMC0_TRIG"></a>
<h3><a name="sect_5_1">5.1. FMC slot 1 trigger interrupt</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td >
irq_ctrl_fmc0_trig
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td >
FMC0_TRIG
</td>
</tr>
<tr>
<td >
<b>Trigger: </b>
</td>
<td >
rising edge
</td>
</tr>
</table>
<p>FMC slot 1 trigger interrupt line (rising edge sensitive).</p>
<a name="FMC0_ACQ_END"></a>
<h3><a name="sect_5_2">5.2. FMC slot 1 end of acquisition interrupt</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td >
irq_ctrl_fmc0_acq_end
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td >
FMC0_ACQ_END
</td>
</tr>
<tr>
<td >
<b>Trigger: </b>
</td>
<td >
rising edge
</td>
</tr>
</table>
<p>FMC slot 1 end of acquisition interrupt line (rising edge sensitive).</p>
<a name="FMC1_TRIG"></a>
<h3><a name="sect_5_3">5.3. FMC slot 2 trigger interrupt</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td >
irq_ctrl_fmc1_trig
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td >
FMC1_TRIG
</td>
</tr>
<tr>
<td >
<b>Trigger: </b>
</td>
<td >
rising edge
</td>
</tr>
</table>
<p>FMC slot 2 trigger interrupt line (rising edge sensitive).</p>
<a name="FMC1_ACQ_END"></a>
<h3><a name="sect_5_4">5.4. FMC slot 2 end of acquisition interrupt</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td >
irq_ctrl_fmc1_acq_end
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td >
FMC1_ACQ_END
</td>
</tr>
<tr>
<td >
<b>Trigger: </b>
</td>
<td >
rising edge
</td>
</tr>
</table>
<p>FMC slot 2 end of acquisition interrupt line (rising edge sensitive).</p>
</BODY>
</HTML>
hdl/svec/wb_gen/irq_controller.wb 0 → 100644
View file @ a1755df7
peripheral {
name = "Interrupt controller";
description = "Fmc-adc interrrupt controller for SVEC.";
hdl_entity = "irq_controller";
prefix = "irq_ctrl";
irq {
name = "FMC slot 1 trigger interrupt";
description = "FMC slot 1 trigger interrupt line (rising edge sensitive).";
prefix = "fmc0_trig";
trigger = EDGE_RISING;
};
irq {
name = "FMC slot 1 end of acquisition interrupt";
description = "FMC slot 1 end of acquisition interrupt line (rising edge sensitive).";
prefix = "fmc0_acq_end";
trigger = EDGE_RISING;
};
irq {
name = "FMC slot 2 trigger interrupt";
description = "FMC slot 2 trigger interrupt line (rising edge sensitive).";
prefix = "fmc1_trig";
trigger = EDGE_RISING;
};
irq {
name = "FMC slot 2 end of acquisition interrupt";
description = "FMC slot 2 end of acquisition interrupt line (rising edge sensitive).";
prefix = "fmc1_acq_end";
trigger = EDGE_RISING;
};
};
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