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FMC ADC 100M 14b 4cha - Gateware
Commits
9a65c3a9
Commit
9a65c3a9
authored
Mar 11, 2013
by
Matthieu Cattin
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hdl: Remove bitstream_type and bitstream_date from carrier csr registers.
This information is now in sdb header (meta info).
parent
661b71ba
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Showing
5 changed files
with
72 additions
and
781 deletions
+72
-781
carrier_csr.vhd
hdl/spec/rtl/carrier_csr.vhd
+14
-27
spec_top_fmc_adc_100Ms.vhd
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
+2
-8
carrier_csr.h
hdl/spec/wb_gen/carrier_csr.h
+3
-11
carrier_csr.htm
hdl/spec/wb_gen/carrier_csr.htm
+52
-706
carrier_csr.wb
hdl/spec/wb_gen/carrier_csr.wb
+1
-29
No files found.
hdl/spec/rtl/carrier_csr.vhd
View file @
9a65c3a9
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created :
Wed Nov 23 09:30:44 2011
-- Created :
Mon Mar 11 17:11:09 2013
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
...
@@ -18,7 +18,7 @@ entity carrier_csr is
...
@@ -18,7 +18,7 @@ entity carrier_csr is
port
(
port
(
rst_n_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
wb_clk_i
:
in
std_logic
;
wb_clk_i
:
in
std_logic
;
wb_addr_i
:
in
std_logic_vector
(
2
downto
0
);
wb_addr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_data_i
:
in
std_logic_vector
(
31
downto
0
);
wb_data_i
:
in
std_logic_vector
(
31
downto
0
);
wb_data_o
:
out
std_logic_vector
(
31
downto
0
);
wb_data_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_cyc_i
:
in
std_logic
;
...
@@ -32,10 +32,6 @@ entity carrier_csr is
...
@@ -32,10 +32,6 @@ entity carrier_csr is
carrier_csr_carrier_reserved_i
:
in
std_logic_vector
(
11
downto
0
);
carrier_csr_carrier_reserved_i
:
in
std_logic_vector
(
11
downto
0
);
-- Port for std_logic_vector field: 'Carrier type' in reg: 'Carrier type and PCB version'
-- Port for std_logic_vector field: 'Carrier type' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_type_i
:
in
std_logic_vector
(
15
downto
0
);
carrier_csr_carrier_type_i
:
in
std_logic_vector
(
15
downto
0
);
-- Port for std_logic_vector field: 'Bitstream type' in reg: 'Bitstream type'
carrier_csr_bitstream_type_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Bitstream date' in reg: 'Bitstream date'
carrier_csr_bitstream_date_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for BIT field: 'FMC presence' in reg: 'Status'
-- Port for BIT field: 'FMC presence' in reg: 'Status'
carrier_csr_stat_fmc_pres_i
:
in
std_logic
;
carrier_csr_stat_fmc_pres_i
:
in
std_logic
;
-- Port for BIT field: 'GN4142 core P2L PLL status' in reg: 'Status'
-- Port for BIT field: 'GN4142 core P2L PLL status' in reg: 'Status'
...
@@ -67,7 +63,7 @@ signal ack_sreg : std_logic_vector(9 downto 0);
...
@@ -67,7 +63,7 @@ signal ack_sreg : std_logic_vector(9 downto 0);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
bwsel_reg
:
std_logic_vector
(
3
downto
0
);
signal
bwsel_reg
:
std_logic_vector
(
3
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
2
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
1
downto
0
);
signal
ack_in_progress
:
std_logic
;
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
signal
rd_int
:
std_logic
;
...
@@ -107,8 +103,8 @@ begin
...
@@ -107,8 +103,8 @@ begin
end
if
;
end
if
;
else
else
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
case
rwaddr_reg
(
2
downto
0
)
is
case
rwaddr_reg
(
1
downto
0
)
is
when
"00
0
"
=>
when
"00"
=>
if
(
wb_we_i
=
'1'
)
then
if
(
wb_we_i
=
'1'
)
then
else
else
rddata_reg
(
3
downto
0
)
<=
carrier_csr_carrier_pcb_rev_i
;
rddata_reg
(
3
downto
0
)
<=
carrier_csr_carrier_pcb_rev_i
;
...
@@ -117,22 +113,12 @@ begin
...
@@ -117,22 +113,12 @@ begin
end
if
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"001"
=>
when
"01"
=>
if
(
wb_we_i
=
'1'
)
then
else
rddata_reg
(
31
downto
0
)
<=
carrier_csr_bitstream_type_i
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"010"
=>
if
(
wb_we_i
=
'1'
)
then
else
rddata_reg
(
31
downto
0
)
<=
carrier_csr_bitstream_date_i
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"011"
=>
if
(
wb_we_i
=
'1'
)
then
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
else
else
rddata_reg
(
0
)
<=
carrier_csr_stat_fmc_pres_i
;
rddata_reg
(
0
)
<=
carrier_csr_stat_fmc_pres_i
;
rddata_reg
(
1
)
<=
carrier_csr_stat_p2l_pll_lck_i
;
rddata_reg
(
1
)
<=
carrier_csr_stat_p2l_pll_lck_i
;
...
@@ -142,10 +128,13 @@ begin
...
@@ -142,10 +128,13 @@ begin
end
if
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"10
0
"
=>
when
"10"
=>
if
(
wb_we_i
=
'1'
)
then
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
0
)
<=
'X'
;
carrier_csr_ctrl_led_green_int
<=
wrdata_reg
(
0
);
carrier_csr_ctrl_led_green_int
<=
wrdata_reg
(
0
);
rddata_reg
(
1
)
<=
'X'
;
carrier_csr_ctrl_led_red_int
<=
wrdata_reg
(
1
);
carrier_csr_ctrl_led_red_int
<=
wrdata_reg
(
1
);
rddata_reg
(
2
)
<=
'X'
;
carrier_csr_ctrl_dac_clr_n_int
<=
wrdata_reg
(
2
);
carrier_csr_ctrl_dac_clr_n_int
<=
wrdata_reg
(
2
);
carrier_csr_ctrl_reserved_int
<=
wrdata_reg
(
31
downto
3
);
carrier_csr_ctrl_reserved_int
<=
wrdata_reg
(
31
downto
3
);
else
else
...
@@ -172,8 +161,6 @@ begin
...
@@ -172,8 +161,6 @@ begin
-- PCB revision
-- PCB revision
-- Reserved register
-- Reserved register
-- Carrier type
-- Carrier type
-- Bitstream type
-- Bitstream date
-- FMC presence
-- FMC presence
-- GN4142 core P2L PLL status
-- GN4142 core P2L PLL status
-- System clock PLL status
-- System clock PLL status
...
...
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @
9a65c3a9
...
@@ -173,7 +173,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
...
@@ -173,7 +173,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
port
(
port
(
rst_n_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
wb_clk_i
:
in
std_logic
;
wb_clk_i
:
in
std_logic
;
wb_addr_i
:
in
std_logic_vector
(
2
downto
0
);
wb_addr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_data_i
:
in
std_logic_vector
(
31
downto
0
);
wb_data_i
:
in
std_logic_vector
(
31
downto
0
);
wb_data_o
:
out
std_logic_vector
(
31
downto
0
);
wb_data_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_cyc_i
:
in
std_logic
;
...
@@ -184,8 +184,6 @@ architecture rtl of spec_top_fmc_adc_100Ms is
...
@@ -184,8 +184,6 @@ architecture rtl of spec_top_fmc_adc_100Ms is
carrier_csr_carrier_pcb_rev_i
:
in
std_logic_vector
(
3
downto
0
);
carrier_csr_carrier_pcb_rev_i
:
in
std_logic_vector
(
3
downto
0
);
carrier_csr_carrier_reserved_i
:
in
std_logic_vector
(
11
downto
0
);
carrier_csr_carrier_reserved_i
:
in
std_logic_vector
(
11
downto
0
);
carrier_csr_carrier_type_i
:
in
std_logic_vector
(
15
downto
0
);
carrier_csr_carrier_type_i
:
in
std_logic_vector
(
15
downto
0
);
carrier_csr_bitstream_type_i
:
in
std_logic_vector
(
31
downto
0
);
carrier_csr_bitstream_date_i
:
in
std_logic_vector
(
31
downto
0
);
carrier_csr_stat_fmc_pres_i
:
in
std_logic
;
carrier_csr_stat_fmc_pres_i
:
in
std_logic
;
carrier_csr_stat_p2l_pll_lck_i
:
in
std_logic
;
carrier_csr_stat_p2l_pll_lck_i
:
in
std_logic
;
carrier_csr_stat_sys_pll_lck_i
:
in
std_logic
;
carrier_csr_stat_sys_pll_lck_i
:
in
std_logic
;
...
@@ -422,8 +420,6 @@ architecture rtl of spec_top_fmc_adc_100Ms is
...
@@ -422,8 +420,6 @@ architecture rtl of spec_top_fmc_adc_100Ms is
-- SPEC carrier CSR constants
-- SPEC carrier CSR constants
constant
c_CARRIER_TYPE
:
std_logic_vector
(
15
downto
0
)
:
=
X"0001"
;
constant
c_CARRIER_TYPE
:
std_logic_vector
(
15
downto
0
)
:
=
X"0001"
;
constant
c_BITSTREAM_TYPE
:
std_logic_vector
(
31
downto
0
)
:
=
X"00000001"
;
constant
c_BITSTREAM_DATE
:
std_logic_vector
(
31
downto
0
)
:
=
X"50AA5124"
;
-- UTC time
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Signals declaration
-- Signals declaration
...
@@ -792,7 +788,7 @@ begin
...
@@ -792,7 +788,7 @@ begin
port
map
(
port
map
(
rst_n_i
=>
sys_rst_n
,
rst_n_i
=>
sys_rst_n
,
wb_clk_i
=>
sys_clk_125
,
wb_clk_i
=>
sys_clk_125
,
wb_addr_i
=>
cnx_master_out
(
c_SLAVE_SPEC_CSR
)
.
adr
(
4
downto
2
),
-- cnx_master_out.adr is byte address
wb_addr_i
=>
cnx_master_out
(
c_SLAVE_SPEC_CSR
)
.
adr
(
3
downto
2
),
-- cnx_master_out.adr is byte address
wb_data_i
=>
cnx_master_out
(
c_SLAVE_SPEC_CSR
)
.
dat
,
wb_data_i
=>
cnx_master_out
(
c_SLAVE_SPEC_CSR
)
.
dat
,
wb_data_o
=>
cnx_master_in
(
c_SLAVE_SPEC_CSR
)
.
dat
,
wb_data_o
=>
cnx_master_in
(
c_SLAVE_SPEC_CSR
)
.
dat
,
wb_cyc_i
=>
cnx_master_out
(
c_SLAVE_SPEC_CSR
)
.
cyc
,
wb_cyc_i
=>
cnx_master_out
(
c_SLAVE_SPEC_CSR
)
.
cyc
,
...
@@ -803,8 +799,6 @@ begin
...
@@ -803,8 +799,6 @@ begin
carrier_csr_carrier_pcb_rev_i
=>
pcb_ver_i
,
carrier_csr_carrier_pcb_rev_i
=>
pcb_ver_i
,
carrier_csr_carrier_reserved_i
=>
X"000"
,
carrier_csr_carrier_reserved_i
=>
X"000"
,
carrier_csr_carrier_type_i
=>
c_CARRIER_TYPE
,
carrier_csr_carrier_type_i
=>
c_CARRIER_TYPE
,
carrier_csr_bitstream_type_i
=>
c_BITSTREAM_TYPE
,
carrier_csr_bitstream_date_i
=>
c_BITSTREAM_DATE
,
carrier_csr_stat_fmc_pres_i
=>
prsnt_m2c_n_i
,
carrier_csr_stat_fmc_pres_i
=>
prsnt_m2c_n_i
,
carrier_csr_stat_p2l_pll_lck_i
=>
p2l_pll_locked
,
carrier_csr_stat_p2l_pll_lck_i
=>
p2l_pll_locked
,
carrier_csr_stat_sys_pll_lck_i
=>
sys_clk_pll_locked
,
carrier_csr_stat_sys_pll_lck_i
=>
sys_clk_pll_locked
,
...
...
hdl/spec/wb_gen/carrier_csr.h
View file @
9a65c3a9
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
* File : carrier_csr.h
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created :
Wed Nov 23 09:30:44 2011
* Created :
Mon Mar 11 17:11:09 2013
* Standard : ANSI C
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
...
@@ -51,10 +51,6 @@
...
@@ -51,10 +51,6 @@
#define CARRIER_CSR_CARRIER_TYPE_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define CARRIER_CSR_CARRIER_TYPE_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define CARRIER_CSR_CARRIER_TYPE_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
#define CARRIER_CSR_CARRIER_TYPE_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Bitstream type */
/* definitions for register: Bitstream date */
/* definitions for register: Status */
/* definitions for register: Status */
/* definitions for field: FMC presence in reg: Status */
/* definitions for field: FMC presence in reg: Status */
...
@@ -95,13 +91,9 @@
...
@@ -95,13 +91,9 @@
PACKED
struct
CARRIER_CSR_WB
{
PACKED
struct
CARRIER_CSR_WB
{
/* [0x0]: REG Carrier type and PCB version */
/* [0x0]: REG Carrier type and PCB version */
uint32_t
CARRIER
;
uint32_t
CARRIER
;
/* [0x4]: REG Bitstream type */
/* [0x4]: REG Status */
uint32_t
BITSTREAM_TYPE
;
/* [0x8]: REG Bitstream date */
uint32_t
BITSTREAM_DATE
;
/* [0xc]: REG Status */
uint32_t
STAT
;
uint32_t
STAT
;
/* [0x
10
]: REG Control */
/* [0x
8
]: REG Control */
uint32_t
CTRL
;
uint32_t
CTRL
;
};
};
...
...
hdl/spec/wb_gen/carrier_csr.htm
View file @
9a65c3a9
...
@@ -35,10 +35,8 @@
...
@@ -35,10 +35,8 @@
<span
style=
"margin-left: 0px; "
>
2.
<A
href=
"#sect_2_0"
>
HDL symbol
</a></span><br/>
<span
style=
"margin-left: 0px; "
>
2.
<A
href=
"#sect_2_0"
>
HDL symbol
</a></span><br/>
<span
style=
"margin-left: 0px; "
>
3.
<A
href=
"#sect_3_0"
>
Register description
</a></span><br/>
<span
style=
"margin-left: 0px; "
>
3.
<A
href=
"#sect_3_0"
>
Register description
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.1.
<A
href=
"#sect_3_1"
>
Carrier type and PCB version
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.1.
<A
href=
"#sect_3_1"
>
Carrier type and PCB version
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.2.
<A
href=
"#sect_3_2"
>
Bitstream type
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.2.
<A
href=
"#sect_3_2"
>
Status
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.3.
<A
href=
"#sect_3_3"
>
Bitstream date
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.3.
<A
href=
"#sect_3_3"
>
Control
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.4.
<A
href=
"#sect_3_4"
>
Status
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.5.
<A
href=
"#sect_3_5"
>
Control
</a></span><br/>
<h3><a
name=
"sect_1_0"
>
1. Memory map summary
</a></h3>
<h3><a
name=
"sect_1_0"
>
1. Memory map summary
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<tr>
...
@@ -83,40 +81,6 @@ CARRIER
...
@@ -83,40 +81,6 @@ CARRIER
REG
REG
</td>
</td>
<td
>
<td
>
<A
href=
"#BITSTREAM_TYPE"
>
Bitstream type
</a>
</td>
<td
class=
"td_code"
>
carrier_csr_bitstream_type
</td>
<td
class=
"td_code"
>
BITSTREAM_TYPE
</td>
</tr>
<tr
class=
"tr_odd"
>
<td
class=
"td_code"
>
0x2
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#BITSTREAM_DATE"
>
Bitstream date
</a>
</td>
<td
class=
"td_code"
>
carrier_csr_bitstream_date
</td>
<td
class=
"td_code"
>
BITSTREAM_DATE
</td>
</tr>
<tr
class=
"tr_even"
>
<td
class=
"td_code"
>
0x3
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#STAT"
>
Status
</a>
<A
href=
"#STAT"
>
Status
</a>
</td>
</td>
<td
class=
"td_code"
>
<td
class=
"td_code"
>
...
@@ -128,7 +92,7 @@ STAT
...
@@ -128,7 +92,7 @@ STAT
</tr>
</tr>
<tr
class=
"tr_odd"
>
<tr
class=
"tr_odd"
>
<td
class=
"td_code"
>
<td
class=
"td_code"
>
0x
4
0x
2
</td>
</td>
<td
>
<td
>
REG
REG
...
@@ -186,7 +150,7 @@ carrier_csr_carrier_pcb_rev_i[3:0]
...
@@ -186,7 +150,7 @@ carrier_csr_carrier_pcb_rev_i[3:0]
⇒
⇒
</td>
</td>
<td
class=
"td_pblock_left"
>
<td
class=
"td_pblock_left"
>
wb_addr_i[
2
:0]
wb_addr_i[
1
:0]
</td>
</td>
<td
class=
"td_sym_center"
>
<td
class=
"td_sym_center"
>
...
@@ -243,7 +207,7 @@ wb_cyc_i
...
@@ -243,7 +207,7 @@ wb_cyc_i
</td>
</td>
<td
class=
"td_pblock_right"
>
<td
class=
"td_pblock_right"
>
<b>
Bitstream type
:
</b>
<b>
Status
:
</b>
</td>
</td>
<td
class=
"td_arrow_right"
>
<td
class=
"td_arrow_right"
>
...
@@ -258,108 +222,6 @@ wb_sel_i[3:0]
...
@@ -258,108 +222,6 @@ wb_sel_i[3:0]
</td>
</td>
<td
class=
"td_sym_center"
>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
carrier_csr_bitstream_type_i[31:0]
</td>
<td
class=
"td_arrow_right"
>
⇐
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
→
</td>
<td
class=
"td_pblock_left"
>
wb_stb_i
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
→
</td>
<td
class=
"td_pblock_left"
>
wb_we_i
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Bitstream date:
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
←
</td>
<td
class=
"td_pblock_left"
>
wb_ack_o
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
carrier_csr_bitstream_date_i[31:0]
</td>
<td
class=
"td_arrow_right"
>
⇐
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
Status:
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
</td>
<td
class=
"td_pblock_right"
>
<td
class=
"td_pblock_right"
>
carrier_csr_stat_fmc_pres_i
carrier_csr_stat_fmc_pres_i
...
@@ -370,10 +232,10 @@ carrier_csr_stat_fmc_pres_i
...
@@ -370,10 +232,10 @@ carrier_csr_stat_fmc_pres_i
</tr>
</tr>
<tr>
<tr>
<td
class=
"td_arrow_left"
>
<td
class=
"td_arrow_left"
>
→
</td>
</td>
<td
class=
"td_pblock_left"
>
<td
class=
"td_pblock_left"
>
wb_stb_i
</td>
</td>
<td
class=
"td_sym_center"
>
<td
class=
"td_sym_center"
>
...
@@ -387,10 +249,10 @@ carrier_csr_stat_p2l_pll_lck_i
...
@@ -387,10 +249,10 @@ carrier_csr_stat_p2l_pll_lck_i
</tr>
</tr>
<tr>
<tr>
<td
class=
"td_arrow_left"
>
<td
class=
"td_arrow_left"
>
→
</td>
</td>
<td
class=
"td_pblock_left"
>
<td
class=
"td_pblock_left"
>
wb_we_i
</td>
</td>
<td
class=
"td_sym_center"
>
<td
class=
"td_sym_center"
>
...
@@ -404,10 +266,10 @@ carrier_csr_stat_sys_pll_lck_i
...
@@ -404,10 +266,10 @@ carrier_csr_stat_sys_pll_lck_i
</tr>
</tr>
<tr>
<tr>
<td
class=
"td_arrow_left"
>
<td
class=
"td_arrow_left"
>
←
</td>
</td>
<td
class=
"td_pblock_left"
>
<td
class=
"td_pblock_left"
>
wb_ack_o
</td>
</td>
<td
class=
"td_sym_center"
>
<td
class=
"td_sym_center"
>
...
@@ -805,17 +667,17 @@ RESERVED
...
@@ -805,17 +667,17 @@ RESERVED
<li><b>
<li><b>
TYPE
TYPE
</b>
[
<i>
read-only
</i>
]: Carrier type
</b>
[
<i>
read-only
</i>
]: Carrier type
<br>
Carrier type identifier
<br>
Carrier type identifier
<br>
1 = SPEC
<br>
2 = SVEC
<br>
3 = VFC
<br>
4 = SPEXI
</ul>
</ul>
<a
name=
"
BITSTREAM_TYPE
"
></a>
<a
name=
"
STAT
"
></a>
<h3><a
name=
"sect_3_2"
>
3.2.
Bitstream type
</a></h3>
<h3><a
name=
"sect_3_2"
>
3.2.
Status
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<tr>
<td
>
<td
>
<b>
HW prefix:
</b>
<b>
HW prefix:
</b>
</td>
</td>
<td
class=
"td_code"
>
<td
class=
"td_code"
>
carrier_csr_
bitstream_type
carrier_csr_
stat
</td>
</td>
</tr>
</tr>
<tr>
<tr>
...
@@ -831,7 +693,7 @@ carrier_csr_bitstream_type
...
@@ -831,7 +693,7 @@ carrier_csr_bitstream_type
<b>
C prefix:
</b>
<b>
C prefix:
</b>
</td>
</td>
<td
class=
"td_code"
>
<td
class=
"td_code"
>
BITSTREAM_TYPE
STAT
</td>
</td>
</tr>
</tr>
<tr>
<tr>
...
@@ -872,7 +734,7 @@ BITSTREAM_TYPE
...
@@ -872,7 +734,7 @@ BITSTREAM_TYPE
</tr>
</tr>
<tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
BITSTREAM_TYPE[31:24
]
RESERVED[27:20
]
</td>
</td>
<td
>
<td
>
...
@@ -926,7 +788,7 @@ BITSTREAM_TYPE[31:24]
...
@@ -926,7 +788,7 @@ BITSTREAM_TYPE[31:24]
</tr>
</tr>
<tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
BITSTREAM_TYPE[23:16
]
RESERVED[19:12
]
</td>
</td>
<td
>
<td
>
...
@@ -980,7 +842,7 @@ BITSTREAM_TYPE[23:16]
...
@@ -980,7 +842,7 @@ BITSTREAM_TYPE[23:16]
</tr>
</tr>
<tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
BITSTREAM_TYPE[15:8
]
RESERVED[11:4
]
</td>
</td>
<td
>
<td
>
...
@@ -1033,20 +895,20 @@ BITSTREAM_TYPE[15:8]
...
@@ -1033,20 +895,20 @@ BITSTREAM_TYPE[15:8]
</td>
</td>
</tr>
</tr>
<tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
<td
style=
"border: solid 1px black;"
colspan=
4
class=
"td_field"
>
BITSTREAM_TYPE[7
:0]
RESERVED[3
:0]
</td>
</td>
<td
>
<td
style=
"border: solid 1px black;"
colspan=
1
class=
"td_field"
>
DDR3_CAL_DONE
</td>
</td>
<td
>
<td
style=
"border: solid 1px black;"
colspan=
1
class=
"td_field"
>
SYS_PLL_LCK
</td>
</td>
<td
>
<td
style=
"border: solid 1px black;"
colspan=
1
class=
"td_field"
>
P2L_PLL_LCK
</td>
</td>
<td
>
<td
style=
"border: solid 1px black;"
colspan=
1
class=
"td_field"
>
FMC_PRES
</td>
</td>
<td
>
<td
>
...
@@ -1061,19 +923,35 @@ BITSTREAM_TYPE[7:0]
...
@@ -1061,19 +923,35 @@ BITSTREAM_TYPE[7:0]
</table>
</table>
<ul>
<ul>
<li><b>
<li><b>
BITSTREAM_TYPE
FMC_PRES
</b>
[
<i>
read-only
</i>
]: Bitstream type
</b>
[
<i>
read-only
</i>
]: FMC presence
<br>
Bitstream (firmware) type, unsigned 32-bit number.
<br>
0: FMC slot is populated
<br>
1: FMC slot is not populated.
<li><b>
P2L_PLL_LCK
</b>
[
<i>
read-only
</i>
]: GN4142 core P2L PLL status
<br>
0: not locked
<br>
1: locked.
<li><b>
SYS_PLL_LCK
</b>
[
<i>
read-only
</i>
]: System clock PLL status
<br>
0: not locked
<br>
1: locked.
<li><b>
DDR3_CAL_DONE
</b>
[
<i>
read-only
</i>
]: DDR3 calibration status
<br>
0: not done
<br>
1: done.
<li><b>
RESERVED
</b>
[
<i>
read-only
</i>
]: Reserved
<br>
Ignore on read, write with 0's.
</ul>
</ul>
<a
name=
"
BITSTREAM_DATE
"
></a>
<a
name=
"
CTRL
"
></a>
<h3><a
name=
"sect_3_3"
>
3.3.
Bitstream date
</a></h3>
<h3><a
name=
"sect_3_3"
>
3.3.
Control
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<tr>
<td
>
<td
>
<b>
HW prefix:
</b>
<b>
HW prefix:
</b>
</td>
</td>
<td
class=
"td_code"
>
<td
class=
"td_code"
>
carrier_csr_
bitstream_date
carrier_csr_
ctrl
</td>
</td>
</tr>
</tr>
<tr>
<tr>
...
@@ -1089,7 +967,7 @@ carrier_csr_bitstream_date
...
@@ -1089,7 +967,7 @@ carrier_csr_bitstream_date
<b>
C prefix:
</b>
<b>
C prefix:
</b>
</td>
</td>
<td
class=
"td_code"
>
<td
class=
"td_code"
>
BITSTREAM_DATE
CTRL
</td>
</td>
</tr>
</tr>
<tr>
<tr>
...
@@ -1130,538 +1008,6 @@ BITSTREAM_DATE
...
@@ -1130,538 +1008,6 @@ BITSTREAM_DATE
</tr>
</tr>
<tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
BITSTREAM_DATE[31:24]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
BITSTREAM_DATE[23:16]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
BITSTREAM_DATE[15:8]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
BITSTREAM_DATE[7:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
BITSTREAM_DATE
</b>
[
<i>
read-only
</i>
]: Bitstream date
<br>
Bitstream generation date, unsigned 32-bit UTC time.
</ul>
<a
name=
"STAT"
></a>
<h3><a
name=
"sect_3_4"
>
3.4. Status
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
carrier_csr_stat
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0x3
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
STAT
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0xc
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
RESERVED[27:20]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
RESERVED[19:12]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
RESERVED[11:4]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
4
class=
"td_field"
>
RESERVED[3:0]
</td>
<td
style=
"border: solid 1px black;"
colspan=
1
class=
"td_field"
>
DDR3_CAL_DONE
</td>
<td
style=
"border: solid 1px black;"
colspan=
1
class=
"td_field"
>
SYS_PLL_LCK
</td>
<td
style=
"border: solid 1px black;"
colspan=
1
class=
"td_field"
>
P2L_PLL_LCK
</td>
<td
style=
"border: solid 1px black;"
colspan=
1
class=
"td_field"
>
FMC_PRES
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
FMC_PRES
</b>
[
<i>
read-only
</i>
]: FMC presence
<br>
0: FMC slot is populated
<br>
1: FMC slot is not populated.
<li><b>
P2L_PLL_LCK
</b>
[
<i>
read-only
</i>
]: GN4142 core P2L PLL status
<br>
0: not locked
<br>
1: locked.
<li><b>
SYS_PLL_LCK
</b>
[
<i>
read-only
</i>
]: System clock PLL status
<br>
0: not locked
<br>
1: locked.
<li><b>
DDR3_CAL_DONE
</b>
[
<i>
read-only
</i>
]: DDR3 calibration status
<br>
0: not done
<br>
1: done.
<li><b>
RESERVED
</b>
[
<i>
read-only
</i>
]: Reserved
<br>
Ignore on read, write with 0's.
</ul>
<a
name=
"CTRL"
></a>
<h3><a
name=
"sect_3_5"
>
3.5. Control
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
carrier_csr_ctrl
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0x4
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
CTRL
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x10
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
style=
"border: solid 1px black;"
colspan=
8
class=
"td_field"
>
RESERVED[28:21]
RESERVED[28:21]
</td>
</td>
<td
>
<td
>
...
...
hdl/spec/wb_gen/carrier_csr.wb
View file @
9a65c3a9
...
@@ -31,7 +31,7 @@ peripheral {
...
@@ -31,7 +31,7 @@ peripheral {
field {
field {
name = "Carrier type";
name = "Carrier type";
description = "Carrier type identifier";
description = "Carrier type identifier
\n1 = SPEC\n2 = SVEC\n3 = VFC\n4 = SPEXI
";
prefix = "type";
prefix = "type";
type = SLV;
type = SLV;
size = 16;
size = 16;
...
@@ -40,34 +40,6 @@ peripheral {
...
@@ -40,34 +40,6 @@ peripheral {
};
};
};
};
reg {
name = "Bitstream type";
prefix = "bitstream_type";
field {
name = "Bitstream type";
description = "Bitstream (firmware) type, unsigned 32-bit number.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Bitstream date";
prefix = "bitstream_date";
field {
name = "Bitstream date";
description = "Bitstream generation date, unsigned 32-bit UTC time.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
reg {
name = "Status";
name = "Status";
prefix = "stat";
prefix = "stat";
...
...
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