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FMC ADC 100M 14b 4cha - Gateware
Commit 92c891b4 authored by Matthieu Cattin's avatar Matthieu Cattin
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syn: svec-fmc-adc firmware release 3.0

parent d6208778
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Showing with 4162 additions and 6065 deletions
hdl/svec/rtl/sdb_meta_pkg.vhd
View file @ 92c891b4
......@@ -54,13 +54,13 @@ package sdb_meta_pkg is
syn_module_name => "svec_top_fmc_adc",
-- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="%H" | cut -c1-32
syn_commit_id => "5a411766d8fdc519df7cf02a1832c76b",
syn_commit_id => "3f94d996746574776e3cf47cdb473a35",
-- Synthesis tool name (string, 8 char)
syn_tool_name => "ISE ",
-- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version => x"00000133",
-- Synthesis date (bcd encoded, 32-bit)
syn_date => x"20131004",
-- Synthesis date (bcd encoded, 32-bit, yyyymmdd)
syn_date => x"20140116",
-- Synthesised by (string, 15 char)
syn_username => "mcattin ");
......@@ -70,7 +70,7 @@ package sdb_meta_pkg is
vendor_id => x"000000000000CE42", -- CERN
device_id => x"5c01a632", -- echo "svec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version => x"00030000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20131203", -- yyyymmdd
date => x"20140116", -- yyyymmdd
name => "svec_fmcadc100m14b "));
......
hdl/svec/syn/svec_fmc_adc_100Ms.xise
View file @ 92c891b4
......@@ -351,784 +351,485 @@
<file xil_pn:name="../../ip_cores/wb_ddr_fifo.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/adc_serdes.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/monostable/monostable_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/utils/utils_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../rtl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../rtl/carrier_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../rtl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_mezzanine_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/timetag_core/rtl/timetag_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../rtl/sdb_meta_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/offset_gain_s.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/timetag_core/rtl/timetag_core_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/timetag_core/rtl/timetag_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_mezzanine.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_as.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="189"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="190"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="191"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="192"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="193"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="194"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
</file>
<file xil_pn:name="../rtl/irq_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
<association xil_pn:name="Implementation" xil_pn:seqID="127"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
<association xil_pn:name="Implementation" xil_pn:seqID="128"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="199"/>
<association xil_pn:name="Implementation" xil_pn:seqID="129"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="200"/>
<association xil_pn:name="Implementation" xil_pn:seqID="130"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="201"/>
<association xil_pn:name="Implementation" xil_pn:seqID="131"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/ddr3_ctrl_svec_bank4_64b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="202"/>
<association xil_pn:name="Implementation" xil_pn:seqID="132"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/memc4_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="203"/>
<association xil_pn:name="Implementation" xil_pn:seqID="133"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/memc4_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="204"/>
<association xil_pn:name="Implementation" xil_pn:seqID="134"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="205"/>
<association xil_pn:name="Implementation" xil_pn:seqID="135"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="206"/>
<association xil_pn:name="Implementation" xil_pn:seqID="136"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="207"/>
<association xil_pn:name="Implementation" xil_pn:seqID="137"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="208"/>
<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="209"/>
<association xil_pn:name="Implementation" xil_pn:seqID="139"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/ddr3_ctrl_svec_bank5_64b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="210"/>
<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/memc5_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="211"/>
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/memc5_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="212"/>
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="213"/>
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="214"/>
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="215"/>
<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="216"/>
<association xil_pn:name="Implementation" xil_pn:seqID="146"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="217"/>
<association xil_pn:name="Implementation" xil_pn:seqID="147"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/vme64x_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="218"/>
<association xil_pn:name="Implementation" xil_pn:seqID="148"/>
</file>
<file xil_pn:name="../rtl/svec_top_fmc_adc_100Ms.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="219"/>
<association xil_pn:name="Implementation" xil_pn:seqID="149"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="220"/>
<association xil_pn:name="Implementation" xil_pn:seqID="150"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="221"/>
<association xil_pn:name="Implementation" xil_pn:seqID="151"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Access_Decode.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="222"/>
<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Am_Match.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="223"/>
<association xil_pn:name="Implementation" xil_pn:seqID="153"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="224"/>
<association xil_pn:name="Implementation" xil_pn:seqID="154"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CSR_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="225"/>
<association xil_pn:name="Implementation" xil_pn:seqID="155"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="226"/>
<association xil_pn:name="Implementation" xil_pn:seqID="156"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="227"/>
<association xil_pn:name="Implementation" xil_pn:seqID="157"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CRAM.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="228"/>
<association xil_pn:name="Implementation" xil_pn:seqID="158"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Funct_Match.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="229"/>
<association xil_pn:name="Implementation" xil_pn:seqID="159"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="230"/>
<association xil_pn:name="Implementation" xil_pn:seqID="160"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="231"/>
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_SharedComps.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="232"/>
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_swapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="233"/>
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Wb_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="234"/>
<association xil_pn:name="Implementation" xil_pn:seqID="164"/>
</file>
</files>
......
hdl/svec/syn/svec_top_fmc_adc_100Ms.par
View file @ 92c891b4
Release 13.3 par O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
pcbe15575:: Mon Jul 29 12:34:43 2013
pcbe15575:: Thu Jan 16 18:43:33 2014
par -w -intstyle ise -ol high -mt off svec_top_fmc_adc_100Ms_map.ncd
svec_top_fmc_adc_100Ms.ncd svec_top_fmc_adc_100Ms.pcf
......@@ -22,36 +22,36 @@ Device speed data version: "PRODUCTION 1.20 2011-10-03".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 8,946 out of 184,304 4%
Number used as Flip Flops: 8,946
Number of Slice Registers: 9,051 out of 184,304 4%
Number used as Flip Flops: 9,051
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 10,792 out of 92,152 11%
Number used as logic: 10,331 out of 92,152 11%
Number using O6 output only: 7,741
Number of Slice LUTs: 11,186 out of 92,152 12%
Number used as logic: 10,781 out of 92,152 11%
Number using O6 output only: 8,189
Number using O5 output only: 317
Number using O5 and O6: 2,273
Number using O5 and O6: 2,275
Number used as ROM: 0
Number used as Memory: 27 out of 21,680 1%
Number used as Memory: 13 out of 21,680 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 27
Number using O6 output only: 9
Number used as Shift Register: 13
Number using O6 output only: 5
Number using O5 output only: 0
Number using O5 and O6: 18
Number used exclusively as route-thrus: 434
Number with same-slice register load: 417
Number with same-slice carry load: 17
Number using O5 and O6: 8
Number used exclusively as route-thrus: 392
Number with same-slice register load: 373
Number with same-slice carry load: 19
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 4,077 out of 23,038 17%
Nummber of MUXCYs used: 2,192 out of 46,076 4%
Number of LUT Flip Flop pairs used: 12,538
Number with an unused Flip Flop: 4,665 out of 12,538 37%
Number with an unused LUT: 1,746 out of 12,538 13%
Number of fully used LUT-FF pairs: 6,127 out of 12,538 48%
Number of occupied Slices: 4,219 out of 23,038 18%
Nummber of MUXCYs used: 2,224 out of 46,076 4%
Number of LUT Flip Flop pairs used: 13,002
Number with an unused Flip Flop: 4,961 out of 13,002 38%
Number with an unused LUT: 1,816 out of 13,002 13%
Number of fully used LUT-FF pairs: 6,225 out of 13,002 47%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
......@@ -66,8 +66,8 @@ IO Utilization:
Number of LOCed IOBs: 350 out of 350 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 41 out of 268 15%
Number of RAMB8BWERs: 8 out of 536 1%
Number of RAMB16BWERs: 38 out of 268 14%
Number of RAMB8BWERs: 12 out of 536 2%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0
......@@ -107,37 +107,35 @@ Specific Feature Utilization:
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 22 secs
Starting initial Timing Analysis. REAL time: 23 secs
Finished initial Timing Analysis. REAL time: 23 secs
Starting Router
Phase 1 : 69454 unrouted; REAL time: 27 secs
Phase 1 : 72061 unrouted; REAL time: 27 secs
Phase 2 : 60393 unrouted; REAL time: 1 mins
Phase 2 : 63190 unrouted; REAL time: 1 mins 1 secs
Phase 3 : 23648 unrouted; REAL time: 1 mins 52 secs
Phase 3 : 25274 unrouted; REAL time: 1 mins 51 secs
Phase 4 : 23989 unrouted; (Setup:2409, Hold:0, Component Switching Limit:0) REAL time: 2 mins 11 secs
Phase 4 : 25540 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 9 secs
Updating file: svec_top_fmc_adc_100Ms.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:2775, Hold:0, Component Switching Limit:0) REAL time: 3 mins 35 secs
Phase 5 : 0 unrouted; (Setup:413, Hold:0, Component Switching Limit:0) REAL time: 3 mins 45 secs
Phase 6 : 0 unrouted; (Setup:2273, Hold:0, Component Switching Limit:0) REAL time: 3 mins 43 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 57 secs
Updating file: svec_top_fmc_adc_100Ms.ncd with current fully routed design.
Phase 7 : 0 unrouted; (Setup:363, Hold:0, Component Switching Limit:0) REAL time: 6 mins 36 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 57 secs
Phase 8 : 0 unrouted; (Setup:363, Hold:0, Component Switching Limit:0) REAL time: 6 mins 36 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 57 secs
Phase 9 : 0 unrouted; (Setup:363, Hold:0, Component Switching Limit:0) REAL time: 6 mins 36 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 57 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 mins 41 secs
Total REAL time to Router completion: 6 mins 41 secs
Total CPU time to Router completion: 7 mins 1 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 mins 3 secs
Total REAL time to Router completion: 4 mins 3 secs
Total CPU time to Router completion: 4 mins 10 secs
Partition Implementation Status
-------------------------------
......@@ -155,36 +153,36 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|cmp_fmc_adc_mezzanin | | | | | |
|e_1/cmp_fmc_adc_100M | | | | | |
| s_core/fs_clk | BUFGMUX_X2Y10| No | 153 | 0.377 | 1.463 |
| sys_clk_125 | BUFGMUX_X2Y1| No | 1908 | 0.350 | 1.436 |
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_125 | BUFGMUX_X2Y1| No | 1820 | 0.352 | 1.436 |
|cmp_ddr_ctrl_bank4/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank4_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc4_infrastructure_i | | | | | |
| nst/sys_clk_ibufg | BUFGMUX_X2Y9| No | 5 | 0.179 | 1.277 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_fmc_adc_mezzanin | | | | | |
|e_0/cmp_fmc_adc_100M | | | | | |
| s_core/fs_clk | BUFGMUX_X2Y12| No | 165 | 0.375 | 1.463 |
| sys_clk_62_5 | BUFGMUX_X2Y2| No | 572 | 0.341 | 1.436 |
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_62_5 | BUFGMUX_X2Y2| No | 563 | 0.214 | 1.436 |
|cmp_ddr_ctrl_bank4/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank4_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/c4 | | | | | |
| _mcb_drp_clk | BUFGMUX_X2Y3| No | 78 | 0.163 | 1.438 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank5/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank5_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/c5 | | | | | |
| _mcb_drp_clk | BUFGMUX_X3Y13| No | 77 | 0.196 | 1.289 |
| _mcb_drp_clk | BUFGMUX_X3Y13| No | 76 | 0.187 | 1.289 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank4/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank4_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/c4 | | | | | |
| _mcb_drp_clk | BUFGMUX_X2Y3| No | 77 | 0.163 | 1.438 |
|cmp_fmc_adc_mezzanin | | | | | |
|e_1/cmp_fmc_adc_100M | | | | | |
| s_core/fs_clk | BUFGMUX_X2Y10| No | 163 | 0.373 | 1.463 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank4/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank4_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc4_infrastructure_i | | | | | |
| nst/sys_clk_ibufg | BUFGMUX_X2Y9| No | 3 | 0.000 | 1.281 |
|cmp_fmc_adc_mezzanin | | | | | |
|e_0/cmp_fmc_adc_100M | | | | | |
| s_core/fs_clk | BUFGMUX_X2Y12| No | 165 | 0.377 | 1.463 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_fmc_adc_mezzanin | | | | | |
|e_1/cmp_fmc_adc_100M | | | | | |
......@@ -317,7 +315,7 @@ for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 12
Number of Timing Constraints that were not applied: 11
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
......@@ -374,31 +372,31 @@ Asterisk (*) preceding a constraint indicates it was not met.
Ms_core_dco_clk" TS_adc1_dco_n_i | | | | |
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_ | SETUP | 0.157ns| 7.843ns| 0| 0
clk_125_buf" TS_clk_20m_vcxo_i / 6.25 | HOLD | 0.352ns| | 0| 0
TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_ | SETUP | 0.237ns| 7.763ns| 0| 0
clk_125_buf" TS_clk_20m_vcxo_i / 6.25 | HOLD | 0.077ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_10 | SETUP | 0.242ns| 7.758ns| 0| 0
0Ms_core_fs_clk_buf = PERIOD TIMEGRP | HOLD | 0.399ns| | 0| 0
TS_cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_10 | SETUP | 0.290ns| 7.710ns| 0| 0
0Ms_core_fs_clk_buf = PERIOD TIMEGRP | HOLD | 0.435ns| | 0| 0
"cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_ | | | | |
100Ms_core_fs_clk_buf" TS_cmp_fmc | | | | |
_adc_mezzanine_1_cmp_fmc_adc_100Ms_core_d | | | | |
co_clk / 0.25 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_10 | SETUP | 0.283ns| 7.717ns| 0| 0
0Ms_core_fs_clk_buf = PERIOD TIMEGRP | HOLD | 0.381ns| | 0| 0
TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_10 | SETUP | 0.370ns| 7.630ns| 0| 0
0Ms_core_fs_clk_buf = PERIOD TIMEGRP | HOLD | 0.353ns| | 0| 0
"cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_ | | | | |
100Ms_core_fs_clk_buf" TS_cmp_fmc | | | | |
_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_d | | | | |
co_clk / 0.25 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_sys_clk_62_5_buf = PERIOD TIMEGRP "sys | SETUP | 0.366ns| 15.634ns| 0| 0
_clk_62_5_buf" TS_clk_20m_vcxo_i / | HOLD | 0.265ns| | 0| 0
3.125 HIGH 50% | | | | |
TS_ddr_clk_buf = PERIOD TIMEGRP "ddr_clk_ | SETUP | 1.241ns| 1.758ns| 0| 0
buf" TS_clk_20m_vcxo_i / 16.6666667 | HOLD | 0.393ns| | 0| 0
HIGH 50% | MINLOWPULSE | 0.428ns| 2.572ns| 0| 0
----------------------------------------------------------------------------------------------------------
TS_ddr_clk_buf = PERIOD TIMEGRP "ddr_clk_ | MINLOWPULSE | 0.428ns| 2.572ns| 0| 0
buf" TS_clk_20m_vcxo_i / 16.6666667 | | | | |
HIGH 50% | | | | |
TS_sys_clk_62_5_buf = PERIOD TIMEGRP "sys | SETUP | 0.495ns| 15.505ns| 0| 0
_clk_62_5_buf" TS_clk_20m_vcxo_i / | HOLD | 0.042ns| | 0| 0
3.125 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_adc0_dco_n_i = PERIOD TIMEGRP "adc0_dc | MINPERIOD | 1.075ns| 0.925ns| 0| 0
o_n_i" 2 ns HIGH 50% | | | | |
......@@ -409,8 +407,8 @@ Asterisk (*) preceding a constraint indicates it was not met.
TS_clk_20m_vcxo_i = PERIOD TIMEGRP "clk_2 | MINLOWPULSE | 30.000ns| 20.000ns| 0| 0
0m_vcxo_i" 50 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapp | SETUP | 4.665ns| 7.334ns| 0| 0
er_gen_svec_bank5_64b_32b_cmp_ddr3_ctrl_m | HOLD | 0.425ns| | 0| 0
TS_cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapp | SETUP | 4.915ns| 7.084ns| 0| 0
er_gen_svec_bank5_64b_32b_cmp_ddr3_ctrl_m | HOLD | 0.393ns| | 0| 0
emc5_infrastructure_inst_mcb_drp_clk_bufg | | | | |
_in = PERIOD TIMEGRP "cmp | | | | |
_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapper_gen | | | | |
......@@ -418,8 +416,8 @@ Asterisk (*) preceding a constraint indicates it was not met.
nfrastructure_inst_mcb_drp_clk_bufg_in" | | | | |
TS_ddr_clk_buf / 0.25 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapp | SETUP | 4.967ns| 7.032ns| 0| 0
er_gen_svec_bank4_64b_32b_cmp_ddr3_ctrl_m | HOLD | 0.410ns| | 0| 0
TS_cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapp | SETUP | 5.025ns| 6.974ns| 0| 0
er_gen_svec_bank4_64b_32b_cmp_ddr3_ctrl_m | HOLD | 0.260ns| | 0| 0
emc4_infrastructure_inst_mcb_drp_clk_bufg | | | | |
_in = PERIOD TIMEGRP "cmp | | | | |
_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapper_gen | | | | |
......@@ -453,11 +451,11 @@ Derived Constraints for TS_clk_20m_vcxo_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk_20m_vcxo_i | 50.000ns| 20.000ns| 49.967ns| 0| 0| 0| 2572497|
| TS_sys_clk_62_5_buf | 16.000ns| 15.634ns| N/A| 0| 0| 1754810| 0|
| TS_sys_clk_125_buf | 8.000ns| 7.843ns| N/A| 0| 0| 796755| 0|
| TS_ddr_clk_buf | 3.000ns| 2.572ns| 2.998ns| 0| 0| 0| 20932|
| TS_cmp_ddr_ctrl_bank4_cmp_ddr| 12.000ns| 7.032ns| N/A| 0| 0| 10471| 0|
|TS_clk_20m_vcxo_i | 50.000ns| 20.000ns| 49.967ns| 0| 0| 0| 2559513|
| TS_sys_clk_62_5_buf | 16.000ns| 15.505ns| N/A| 0| 0| 1754511| 0|
| TS_sys_clk_125_buf | 8.000ns| 7.763ns| N/A| 0| 0| 784064| 0|
| TS_ddr_clk_buf | 3.000ns| 2.572ns| 2.998ns| 0| 0| 6| 20932|
| TS_cmp_ddr_ctrl_bank4_cmp_ddr| 12.000ns| 6.974ns| N/A| 0| 0| 10471| 0|
| 3_ctrl_wrapper_gen_svec_bank4| | | | | | | |
| _64b_32b_cmp_ddr3_ctrl_memc4_| | | | | | | |
| infrastructure_inst_mcb_drp_c| | | | | | | |
......@@ -471,7 +469,7 @@ Derived Constraints for TS_clk_20m_vcxo_i
| 3_ctrl_wrapper_gen_svec_bank4| | | | | | | |
| _64b_32b_cmp_ddr3_ctrl_memc4_| | | | | | | |
| infrastructure_inst_clk_2x_0 | | | | | | | |
| TS_cmp_ddr_ctrl_bank5_cmp_ddr| 12.000ns| 7.334ns| N/A| 0| 0| 10461| 0|
| TS_cmp_ddr_ctrl_bank5_cmp_ddr| 12.000ns| 7.084ns| N/A| 0| 0| 10461| 0|
| 3_ctrl_wrapper_gen_svec_bank5| | | | | | | |
| _64b_32b_cmp_ddr3_ctrl_memc5_| | | | | | | |
| infrastructure_inst_mcb_drp_c| | | | | | | |
......@@ -493,10 +491,10 @@ Derived Constraints for TS_adc0_dco_n_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_adc0_dco_n_i | 2.000ns| 0.925ns| 1.929ns| 0| 0| 0| 16183|
| TS_cmp_fmc_adc_mezzanine_0_cmp| 2.000ns| 1.636ns| 1.929ns| 0| 0| 0| 16183|
|TS_adc0_dco_n_i | 2.000ns| 0.925ns| 1.907ns| 0| 0| 0| 47910|
| TS_cmp_fmc_adc_mezzanine_0_cmp| 2.000ns| 1.636ns| 1.907ns| 0| 0| 0| 47910|
| _fmc_adc_100Ms_core_dco_clk | | | | | | | |
| TS_cmp_fmc_adc_mezzanine_0_cm| 8.000ns| 7.717ns| N/A| 0| 0| 16183| 0|
| TS_cmp_fmc_adc_mezzanine_0_cm| 8.000ns| 7.630ns| N/A| 0| 0| 47910| 0|
| p_fmc_adc_100Ms_core_fs_clk_b| | | | | | | |
| uf | | | | | | | |
| TS_cmp_fmc_adc_mezzanine_0_cm| 1.000ns| N/A| N/A| 0| 0| 0| 0|
......@@ -510,10 +508,10 @@ Derived Constraints for TS_adc1_dco_n_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_adc1_dco_n_i | 2.000ns| 0.925ns| 1.940ns| 0| 0| 0| 16183|
| TS_cmp_fmc_adc_mezzanine_1_cmp| 2.000ns| 1.636ns| 1.940ns| 0| 0| 0| 16183|
|TS_adc1_dco_n_i | 2.000ns| 0.925ns| 1.927ns| 0| 0| 0| 47928|
| TS_cmp_fmc_adc_mezzanine_1_cmp| 2.000ns| 1.636ns| 1.927ns| 0| 0| 0| 47928|
| _fmc_adc_100Ms_core_dco_clk | | | | | | | |
| TS_cmp_fmc_adc_mezzanine_1_cm| 8.000ns| 7.758ns| N/A| 0| 0| 16183| 0|
| TS_cmp_fmc_adc_mezzanine_1_cm| 8.000ns| 7.710ns| N/A| 0| 0| 47928| 0|
| p_fmc_adc_100Ms_core_fs_clk_b| | | | | | | |
| uf | | | | | | | |
| TS_cmp_fmc_adc_mezzanine_1_cm| 1.000ns| N/A| N/A| 0| 0| 0| 0|
......@@ -533,10 +531,10 @@ Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 6 mins 49 secs
Total CPU time to PAR completion: 7 mins 9 secs
Total REAL time to PAR completion: 4 mins 11 secs
Total CPU time to PAR completion: 4 mins 18 secs
Peak Memory Usage: 605 MB
Peak Memory Usage: 606 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
......
hdl/svec/syn/svec_top_fmc_adc_100Ms.syr
View file @ 92c891b4
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/svec/syn/svec_top_fmc_adc_100Ms.twr
View file @ 92c891b4
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/svec/syn/svec_top_fmc_adc_100Ms_map.mrp
View file @ 92c891b4
......@@ -11,46 +11,46 @@ Target Device : xc6slx150t
Target Package : fgg900
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Mon Jul 29 12:27:12 2013
Mapped Date : Thu Jan 16 18:35:40 2014
Design Summary
--------------
Number of errors: 0
Number of warnings: 7
Slice Logic Utilization:
Number of Slice Registers: 8,946 out of 184,304 4%
Number used as Flip Flops: 8,946
Number of Slice Registers: 9,051 out of 184,304 4%
Number used as Flip Flops: 9,051
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 10,792 out of 92,152 11%
Number used as logic: 10,331 out of 92,152 11%
Number using O6 output only: 7,741
Number of Slice LUTs: 11,186 out of 92,152 12%
Number used as logic: 10,781 out of 92,152 11%
Number using O6 output only: 8,189
Number using O5 output only: 317
Number using O5 and O6: 2,273
Number using O5 and O6: 2,275
Number used as ROM: 0
Number used as Memory: 27 out of 21,680 1%
Number used as Memory: 13 out of 21,680 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 27
Number using O6 output only: 9
Number used as Shift Register: 13
Number using O6 output only: 5
Number using O5 output only: 0
Number using O5 and O6: 18
Number used exclusively as route-thrus: 434
Number with same-slice register load: 417
Number with same-slice carry load: 17
Number using O5 and O6: 8
Number used exclusively as route-thrus: 392
Number with same-slice register load: 373
Number with same-slice carry load: 19
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 4,077 out of 23,038 17%
Nummber of MUXCYs used: 2,192 out of 46,076 4%
Number of LUT Flip Flop pairs used: 12,538
Number with an unused Flip Flop: 4,665 out of 12,538 37%
Number with an unused LUT: 1,746 out of 12,538 13%
Number of fully used LUT-FF pairs: 6,127 out of 12,538 48%
Number of unique control sets: 347
Number of occupied Slices: 4,219 out of 23,038 18%
Nummber of MUXCYs used: 2,224 out of 46,076 4%
Number of LUT Flip Flop pairs used: 13,002
Number with an unused Flip Flop: 4,961 out of 13,002 38%
Number with an unused LUT: 1,816 out of 13,002 13%
Number of fully used LUT-FF pairs: 6,225 out of 13,002 47%
Number of unique control sets: 342
Number of slice register sites lost
to control set restrictions: 777 out of 184,304 1%
to control set restrictions: 744 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
......@@ -63,8 +63,8 @@ IO Utilization:
Number of LOCed IOBs: 350 out of 350 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 41 out of 268 15%
Number of RAMB8BWERs: 8 out of 536 1%
Number of RAMB16BWERs: 38 out of 268 14%
Number of RAMB8BWERs: 12 out of 536 2%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0
......@@ -100,11 +100,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 4.02
Average Fanout of Non-Clock Nets: 4.06
Peak Memory Usage: 622 MB
Total REAL time to MAP completion: 7 mins 24 secs
Total CPU time to MAP completion (all processors): 7 mins 40 secs
Peak Memory Usage: 631 MB
Total REAL time to MAP completion: 7 mins 47 secs
Total CPU time to MAP completion (all processors): 8 mins 4 secs
Table of Contents
-----------------
......@@ -168,10 +168,10 @@ INFO:LIT:395 - The above info message is repeated 6 more times for the following
(max. 5 shown):
cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl
/memc5_infrastructure_inst/rst0_sync_r<24>,
N1685,
N1687,
N1691,
N1693
N1821,
N1823,
N1827,
N1829
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
......
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