hdl: Add svec design files.

7f782cc2 · Matthieu Cattin · 13354443 · 7f782cc2 · 7f782cc2 · 7f782cc2
Commit 7f782cc2 authored Jul 17, 2013 by Matthieu Cattin
19 changed files
--- a/hdl/svec/rtl/Manifest.py
+++ b/hdl/svec/rtl/Manifest.py
+files = [
+    "svec_top_fmc_adc_100Ms.vhd",
+    "carrier_csr.vhd",
+    "irq_controller.vhd",
+    "irq_controller_regs.vhd",
+    "bicolor_led_ctrl.vhd",
+    "bicolor_led_ctrl_pkg.vhd",
+    "sdb_meta_pkg.vhd"]
--- a/hdl/svec/rtl/bicolor_led_ctrl.vhd
+++ b/hdl/svec/rtl/bicolor_led_ctrl.vhd
+--------------------------------------------------------------------------------
+-- CERN (BE-CO-HT)
+-- Bi-color LED controller
+-- http://www.ohwr.org/projects/svec
+--------------------------------------------------------------------------------
+--
+-- unit name: bicolor_led_ctrl
+--
+-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
+--
+-- date: 11-07-2012
+--
+-- version: 1.0
+--
+-- description: Bi-color LED controller. It controls a matrix of bi-color LED.
+--              The FPGA ouputs for the columns (C) are connected to buffers
+--              and serial resistances and then to the LEDs. The FPGA outputs
+--              for lines (L) are connected to tri-state buffers and the to
+--              the LEDs. The FPGA outputs for lines output enable (L_OEN) are
+--              connected to the output enable of the tri-state buffers.
+--
+--   Example with three lines and two columns:
+--
+--              |<refresh period>|
+--
+--   L1/L2/L3   __|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__
+--
+--   L1_OEN     -----|___________|-----|___________|-----|___________|-----|___________|--
+--
+--   L2_OEN     _____|-----|___________|-----|___________|-----|___________|-----|________
+--
+--   L3_OEN     ___________|-----|___________|-----|___________|-----|___________|-----|__
+--
+--   Cn         __|--|__|--|__|--|_________________|-----------------|--|__|--|__|--|__|--
+--
+--   LED Ln/Cn         OFF       |     color_1     |     color_2     |   both_colors   |
+--
+--
+-- dependencies:
+--
+--------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--------------------------------------------------------------------------------
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--------------------------------------------------------------------------------
+-- last changes: see log.
+--------------------------------------------------------------------------------
+-- TODO: - 
+--------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+library work;
+use work.bicolor_led_ctrl_pkg.all;
+
+
+entity bicolor_led_ctrl is
+  generic(
+    g_NB_COLUMN    : natural := 4;
+    g_NB_LINE      : natural := 2;
+    g_CLK_FREQ     : natural := 125000000;  -- in Hz
+    g_REFRESH_RATE : natural := 250         -- in Hz
+    );
+  port
+    (
+      rst_n_i : in std_logic;
+      clk_i   : in std_logic;
+
+      led_intensity_i : in std_logic_vector(6 downto 0);
+
+      led_state_i : in std_logic_vector((g_NB_LINE * g_NB_COLUMN * 2) - 1 downto 0);
+
+      column_o   : out std_logic_vector(g_NB_COLUMN - 1 downto 0);
+      line_o     : out std_logic_vector(g_NB_LINE - 1 downto 0);
+      line_oen_o : out std_logic_vector(g_NB_LINE - 1 downto 0)
+      );
+end bicolor_led_ctrl;
+
+
+
+architecture rtl of bicolor_led_ctrl is
+
+  ------------------------------------------------------------------------------
+  -- Components declaration
+  ------------------------------------------------------------------------------
+
+  ------------------------------------------------------------------------------
+  -- Constants declaration
+  ------------------------------------------------------------------------------
+  constant c_REFRESH_CNT_INIT     : natural := natural(g_CLK_FREQ/(2 * g_NB_LINE * g_REFRESH_RATE)) - 1;
+  constant c_REFRESH_CNT_NB_BITS  : natural := log2_ceil(c_REFRESH_CNT_INIT);
+  constant c_LINE_OEN_CNT_NB_BITS : natural := log2_ceil(g_NB_LINE);
+
+
+  ------------------------------------------------------------------------------
+  -- Signals declaration
+  ------------------------------------------------------------------------------
+  signal refresh_rate_cnt   : unsigned(c_REFRESH_CNT_NB_BITS - 1 downto 0);
+  signal refresh_rate       : std_logic;
+  signal line_ctrl          : std_logic;
+  signal intensity_ctrl_cnt : unsigned(c_REFRESH_CNT_NB_BITS - 1 downto 0);
+  signal intensity_ctrl     : std_logic;
+  signal line_oen_cnt       : unsigned(c_LINE_OEN_CNT_NB_BITS - 1 downto 0);
+  signal line_oen           : std_logic_vector(2**c_LINE_OEN_CNT_NB_BITS - 1 downto 0);
+  signal led_state          : std_logic_vector((g_NB_LINE * g_NB_COLUMN) -1 downto 0);
+
+
+begin
+
+  ------------------------------------------------------------------------------
+  -- Refresh rate counter
+  ------------------------------------------------------------------------------
+  p_refresh_rate_cnt : process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        refresh_rate_cnt <= (others => '0');
+        refresh_rate     <= '0';
+      elsif refresh_rate_cnt = 0 then
+        refresh_rate_cnt <= to_unsigned(c_REFRESH_CNT_INIT, c_REFRESH_CNT_NB_BITS);
+        refresh_rate     <= '1';
+      else
+        refresh_rate_cnt <= refresh_rate_cnt - 1;
+        refresh_rate     <= '0';
+      end if;
+    end if;
+  end process p_refresh_rate_cnt;
+
+
+  ------------------------------------------------------------------------------
+  -- Intensity control
+  ------------------------------------------------------------------------------
+  p_intensity_ctrl_cnt : process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        intensity_ctrl_cnt <= (others => '0');
+      elsif refresh_rate = '1' then
+        intensity_ctrl_cnt <= to_unsigned(natural(c_REFRESH_CNT_INIT/100) * to_integer(unsigned(led_intensity_i)), c_REFRESH_CNT_NB_BITS);
+      else
+        intensity_ctrl_cnt <= intensity_ctrl_cnt - 1;
+      end if;
+    end if;
+  end process p_intensity_ctrl_cnt;
+
+  p_intensity_ctrl : process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        intensity_ctrl <= '0';
+      elsif refresh_rate = '1' then
+        intensity_ctrl <= '1';
+      elsif intensity_ctrl_cnt = 0 then
+        intensity_ctrl <= '0';
+      end if;
+    end if;
+  end process p_intensity_ctrl;
+
+
+  ------------------------------------------------------------------------------
+  -- Lines ouput
+  ------------------------------------------------------------------------------
+  p_line_ctrl : process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        line_ctrl <= '0';
+      elsif refresh_rate = '1' then
+        line_ctrl <= not(line_ctrl);
+      end if;
+    end if;
+  end process p_line_ctrl;
+
+  f_line_o : for I in 0 to g_NB_LINE - 1 generate
+    line_o(I) <= line_ctrl and intensity_ctrl;
+  end generate f_line_o;
+
+  ------------------------------------------------------------------------------
+  -- Lines output enable
+  ------------------------------------------------------------------------------
+  p_line_oen_cnt : process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        line_oen_cnt <= (others => '0');
+      elsif line_ctrl = '1' and refresh_rate = '1' then
+        if line_oen_cnt = 0 then
+          line_oen_cnt <= to_unsigned(g_NB_LINE - 1, c_LINE_OEN_CNT_NB_BITS);
+        else
+          line_oen_cnt <= line_oen_cnt - 1;
+        end if;
+      end if;
+    end if;
+  end process p_line_oen_cnt;
+
+  p_line_oen_decode : process(line_oen_cnt)
+    variable v_onehot : std_logic_vector((2**line_oen_cnt'length)-1 downto 0);
+    variable v_index  : integer range 0 to (2**line_oen_cnt'length)-1;
+  begin
+    v_onehot := (others => '0');
+    v_index  := 0;
+    for i in line_oen_cnt'range loop
+      if (line_oen_cnt(i) = '1') then
+        v_index := 2*v_index+1;
+      else
+        v_index := 2*v_index;
+      end if;
+    end loop;
+    v_onehot(v_index) := '1';
+    line_oen          <= v_onehot;
+  end process p_line_oen_decode;
+
+  line_oen_o <= line_oen(line_oen_o'left downto 0);
+
+
+  ------------------------------------------------------------------------------
+  -- Columns output
+  ------------------------------------------------------------------------------
+  f_led_state : for I in 0 to (g_NB_COLUMN * g_NB_LINE) - 1 generate
+    led_state(I) <= '0' when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED else
+                    '1'                               when led_state_i(2 * I + 1 downto 2 * I) = c_LED_GREEN else
+                    (line_ctrl and intensity_ctrl)    when led_state_i(2 * I + 1 downto 2 * I) = c_LED_OFF   else
+                    not(line_ctrl and intensity_ctrl) when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED_GREEN;
+  end generate f_led_state;
+
+  f_column_o : for C in 0 to g_NB_COLUMN - 1 generate
+    column_o(C) <= led_state(g_NB_COLUMN * to_integer(line_oen_cnt) + C);
+  end generate f_column_o;
+
+
+end rtl;
--- a/hdl/svec/rtl/bicolor_led_ctrl_pkg.vhd
+++ b/hdl/svec/rtl/bicolor_led_ctrl_pkg.vhd
+--------------------------------------------------------------------------------
+-- CERN (BE-CO-HT)
+-- Bi-color LED controller package
+-- http://www.ohwr.org/projects/svec
+--------------------------------------------------------------------------------
+--
+-- unit name: bicolor_led_ctrl_pkg
+--
+-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
+--
+-- date: 11-07-2012
+--
+-- version: 1.0
+--
+-- description: Package for Bi-color LED controller.
+--
+-- dependencies:
+--
+--------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--------------------------------------------------------------------------------
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--------------------------------------------------------------------------------
+-- last changes: see log.
+--------------------------------------------------------------------------------
+-- TODO: - 
+--------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+
+package bicolor_led_ctrl_pkg is
+
+  ------------------------------------------------------------------------------
+  -- Constants declaration
+  ------------------------------------------------------------------------------
+  constant c_LED_RED       : std_logic_vector(1 downto 0) := "10";
+  constant c_LED_GREEN     : std_logic_vector(1 downto 0) := "01";
+  constant c_LED_RED_GREEN : std_logic_vector(1 downto 0) := "11";
+  constant c_LED_OFF       : std_logic_vector(1 downto 0) := "00";
+
+  ------------------------------------------------------------------------------
+  -- Functions declaration
+  ------------------------------------------------------------------------------
+  function log2_ceil(N : natural) return positive;
+
+  ------------------------------------------------------------------------------
+  -- Components declaration
+  ------------------------------------------------------------------------------
+  component bicolor_led_ctrl
+    generic(
+      g_NB_COLUMN    : natural := 4;
+      g_NB_LINE      : natural := 2;
+      g_CLK_FREQ     : natural := 125000000;  -- in Hz
+      g_REFRESH_RATE : natural := 250         -- in Hz
+      );
+    port
+      (
+        rst_n_i         : in  std_logic;
+        clk_i           : in  std_logic;
+        led_intensity_i : in  std_logic_vector(6 downto 0);
+        led_state_i     : in  std_logic_vector((g_NB_LINE * g_NB_COLUMN * 2) - 1 downto 0);
+        column_o        : out std_logic_vector(g_NB_COLUMN - 1 downto 0);
+        line_o          : out std_logic_vector(g_NB_LINE - 1 downto 0);
+        line_oen_o      : out std_logic_vector(g_NB_LINE - 1 downto 0)
+        );
+  end component;
+
+end bicolor_led_ctrl_pkg;
+
+
+package body bicolor_led_ctrl_pkg is
+
+  ------------------------------------------------------------------------------
+  -- Function : Returns log of 2 of a natural number
+  ------------------------------------------------------------------------------
+  function log2_ceil(N : natural) return positive is
+  begin
+    if N <= 2 then
+      return 1;
+    elsif N mod 2 = 0 then
+      return 1 + log2_ceil(N/2);
+    else
+      return 1 + log2_ceil((N+1)/2);
+    end if;
+  end;
+
+end bicolor_led_ctrl_pkg;
--- a/hdl/svec/rtl/carrier_csr.vhd
+++ b/hdl/svec/rtl/carrier_csr.vhd
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for SVEC carrier control and status registers
+---------------------------------------------------------------------------------------
+-- File           : ../rtl/svec_carrier_csr.vhd
+-- Author         : auto-generated by wbgen2 from svec_carrier_csr.wb
+-- Created        : Fri Jul  5 10:44:08 2013
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE svec_carrier_csr.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity carrier_csr is
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(1 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+-- Port for std_logic_vector field: 'PCB revision' in reg: 'Carrier type and PCB version'
+    carrier_csr_carrier_pcb_rev_i            : in     std_logic_vector(4 downto 0);
+-- Port for std_logic_vector field: 'Reserved register' in reg: 'Carrier type and PCB version'
+    carrier_csr_carrier_reserved_i           : in     std_logic_vector(10 downto 0);
+-- Port for std_logic_vector field: 'Carrier type' in reg: 'Carrier type and PCB version'
+    carrier_csr_carrier_type_i               : in     std_logic_vector(15 downto 0);
+-- Port for BIT field: 'FMC 1 presence' in reg: 'Status'
+    carrier_csr_stat_fmc0_pres_i             : in     std_logic;
+-- Port for BIT field: 'FMC 2 presence' in reg: 'Status'
+    carrier_csr_stat_fmc1_pres_i             : in     std_logic;
+-- Port for BIT field: 'System clock PLL status' in reg: 'Status'
+    carrier_csr_stat_sys_pll_lck_i           : in     std_logic;
+-- Port for BIT field: 'DDR3 bank 4 calibration status' in reg: 'Status'
+    carrier_csr_stat_ddr0_cal_done_i         : in     std_logic;
+-- Port for BIT field: 'DDR3 bank 5 calibration status' in reg: 'Status'
+    carrier_csr_stat_ddr1_cal_done_i         : in     std_logic;
+-- Port for std_logic_vector field: 'Reserved' in reg: 'Status'
+    carrier_csr_stat_reserved_i              : in     std_logic_vector(26 downto 0);
+-- Port for std_logic_vector field: 'Front panel LED manual control' in reg: 'Control'
+    carrier_csr_ctrl_fp_leds_man_o           : out    std_logic_vector(15 downto 0);
+-- Port for std_logic_vector field: 'Reserved' in reg: 'Control'
+    carrier_csr_ctrl_reserved_o              : out    std_logic_vector(15 downto 0)
+  );
+end carrier_csr;
+
+architecture syn of carrier_csr is
+
+signal carrier_csr_ctrl_fp_leds_man_int         : std_logic_vector(15 downto 0);
+signal carrier_csr_ctrl_reserved_int            : std_logic_vector(15 downto 0);
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal bwsel_reg                                : std_logic_vector(3 downto 0);
+signal rwaddr_reg                               : std_logic_vector(1 downto 0);
+signal ack_in_progress                          : std_logic      ;
+signal wr_int                                   : std_logic      ;
+signal rd_int                                   : std_logic      ;
+signal allones                                  : std_logic_vector(31 downto 0);
+signal allzeros                                 : std_logic_vector(31 downto 0);
+
+begin
+-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
+  wrdata_reg <= wb_dat_i;
+  bwsel_reg <= wb_sel_i;
+  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
+  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
+  allones <= (others => '1');
+  allzeros <= (others => '0');
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      carrier_csr_ctrl_fp_leds_man_int <= "0000000000000000";
+      carrier_csr_ctrl_reserved_int <= "0000000000000000";
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          ack_in_progress <= '0';
+        else
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(1 downto 0) is
+          when "00" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(4 downto 0) <= carrier_csr_carrier_pcb_rev_i;
+            rddata_reg(15 downto 5) <= carrier_csr_carrier_reserved_i;
+            rddata_reg(31 downto 16) <= carrier_csr_carrier_type_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01" => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(0) <= carrier_csr_stat_fmc0_pres_i;
+            rddata_reg(1) <= carrier_csr_stat_fmc1_pres_i;
+            rddata_reg(2) <= carrier_csr_stat_sys_pll_lck_i;
+            rddata_reg(3) <= carrier_csr_stat_ddr0_cal_done_i;
+            rddata_reg(4) <= carrier_csr_stat_ddr1_cal_done_i;
+            rddata_reg(31 downto 5) <= carrier_csr_stat_reserved_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10" => 
+            if (wb_we_i = '1') then
+              carrier_csr_ctrl_fp_leds_man_int <= wrdata_reg(15 downto 0);
+              carrier_csr_ctrl_reserved_int <= wrdata_reg(31 downto 16);
+            end if;
+            rddata_reg(15 downto 0) <= carrier_csr_ctrl_fp_leds_man_int;
+            rddata_reg(31 downto 16) <= carrier_csr_ctrl_reserved_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- PCB revision
+-- Reserved register
+-- Carrier type
+-- FMC 1 presence
+-- FMC 2 presence
+-- System clock PLL status
+-- DDR3 bank 4 calibration status
+-- DDR3 bank 5 calibration status
+-- Reserved
+-- Front panel LED manual control
+  carrier_csr_ctrl_fp_leds_man_o <= carrier_csr_ctrl_fp_leds_man_int;
+-- Reserved
+  carrier_csr_ctrl_reserved_o <= carrier_csr_ctrl_reserved_int;
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
--- a/hdl/svec/rtl/irq_controller.vhd
+++ b/hdl/svec/rtl/irq_controller.vhd
+--------------------------------------------------------------------------------
+-- CERN (BE-CO-HT)
+-- IRQ controller
+-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
+--------------------------------------------------------------------------------
+--
+-- unit name: irq_controller (irq_controller.vhd)
+--
+-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
+--
+-- date: 18-11-2011
+--
+-- version: 1.0
+--
+-- description: 
+--
+-- dependencies:
+--
+--------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--------------------------------------------------------------------------------
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--------------------------------------------------------------------------------
+-- last changes: see svn log.
+--------------------------------------------------------------------------------
+-- TODO: - 
+--------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+
+--library UNISIM;
+--use UNISIM.vcomponents.all;
+
+
+entity irq_controller is
+  port (
+    -- Clock, reset
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+    -- Interrupt sources input, must be 1 clk_i tick long
+    irq_src_p_i : in std_logic_vector(31 downto 0);
+
+    -- IRQ pulse output
+    irq_p_o : out std_logic;
+
+    -- Wishbone interface
+    wb_adr_i : in  std_logic_vector(1 downto 0);
+    wb_dat_i : in  std_logic_vector(31 downto 0);
+    wb_dat_o : out std_logic_vector(31 downto 0);
+    wb_cyc_i : in  std_logic;
+    wb_sel_i : in  std_logic_vector(3 downto 0);
+    wb_stb_i : in  std_logic;
+    wb_we_i  : in  std_logic;
+    wb_ack_o : out std_logic
+    );
+end irq_controller;
+
+
+architecture rtl of irq_controller is
+
+
+  ------------------------------------------------------------------------------
+  -- Components declaration
+  ------------------------------------------------------------------------------
+  component irq_controller_regs
+    port (
+      rst_n_i                   : in  std_logic;
+      clk_sys_i                 : in  std_logic;
+      wb_adr_i                  : in  std_logic_vector(1 downto 0);
+      wb_dat_i                  : in  std_logic_vector(31 downto 0);
+      wb_dat_o                  : out std_logic_vector(31 downto 0);
+      wb_cyc_i                  : in  std_logic;
+      wb_sel_i                  : in  std_logic_vector(3 downto 0);
+      wb_stb_i                  : in  std_logic;
+      wb_we_i                   : in  std_logic;
+      wb_ack_o                  : out std_logic;
+      wb_stall_o                  : out std_logic;
+      irq_ctrl_multi_irq_o      : out std_logic_vector(31 downto 0);
+      irq_ctrl_multi_irq_i      : in  std_logic_vector(31 downto 0);
+      irq_ctrl_multi_irq_load_o : out std_logic;
+      irq_ctrl_src_o            : out std_logic_vector(31 downto 0);
+      irq_ctrl_src_i            : in  std_logic_vector(31 downto 0);
+      irq_ctrl_src_load_o       : out std_logic;
+      irq_ctrl_en_mask_o        : out std_logic_vector(31 downto 0)
+      );
+  end component irq_controller_regs;
+
+  ------------------------------------------------------------------------------
+  -- Signals declaration
+  ------------------------------------------------------------------------------
+  signal irq_en_mask      : std_logic_vector(31 downto 0);
+  signal irq_pending      : std_logic_vector(31 downto 0);
+  signal irq_pending_d    : std_logic_vector(31 downto 0);
+  signal irq_pending_re   : std_logic_vector(31 downto 0);
+  signal irq_src_rst      : std_logic_vector(31 downto 0);
+  signal irq_src_rst_en   : std_logic;
+  signal multi_irq        : std_logic_vector(31 downto 0);
+  signal multi_irq_rst    : std_logic_vector(31 downto 0);
+  signal multi_irq_rst_en : std_logic;
+  signal irq_p_or         : std_logic_vector(32 downto 0);
+
+
+begin
+
+  ------------------------------------------------------------------------------
+  -- Wishbone interface to IRQ controller registers
+  ------------------------------------------------------------------------------
+  cmp_irq_controller_regs : irq_controller_regs
+    port map(
+      rst_n_i                   => rst_n_i,
+      clk_sys_i                 => clk_i,
+      wb_adr_i                  => wb_adr_i,
+      wb_dat_i                  => wb_dat_i,
+      wb_dat_o                  => wb_dat_o,
+      wb_cyc_i                  => wb_cyc_i,
+      wb_sel_i                  => wb_sel_i,
+      wb_stb_i                  => wb_stb_i,
+      wb_we_i                   => wb_we_i,
+      wb_ack_o                  => wb_ack_o,
+      wb_stall_o                => open,
+      irq_ctrl_multi_irq_o      => multi_irq_rst,
+      irq_ctrl_multi_irq_load_o => multi_irq_rst_en,
+      irq_ctrl_multi_irq_i      => multi_irq,
+      irq_ctrl_src_o            => irq_src_rst,
+      irq_ctrl_src_i            => irq_pending,
+      irq_ctrl_src_load_o       => irq_src_rst_en,
+      irq_ctrl_en_mask_o        => irq_en_mask
+      );
+
+  ------------------------------------------------------------------------------
+  -- Register interrupt sources
+  -- IRQ is pending until a '1' is written to the corresponding bit
+  ------------------------------------------------------------------------------
+  p_irq_src : process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      for I in 0 to irq_pending'length-1 loop
+        if rst_n_i = '0' then
+          irq_pending(I) <= '0';
+        elsif irq_src_p_i(I) = '1' and irq_en_mask(I) = '1' then
+          irq_pending(I) <= '1';
+        elsif irq_src_rst_en = '1' and irq_src_rst(I) = '1' then
+          irq_pending(I) <= '0';
+        end if;
+      end loop;  -- I
+    end if;
+  end process p_irq_src;
+
+  ------------------------------------------------------------------------------
+  -- Multiple interrupt detection
+  -- Rise a flag if an interrupt occurs while an irq is still pending
+  -- Write '1' to the flag to clear it
+  ------------------------------------------------------------------------------
+  p_multi_irq_detect : process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      for I in 0 to multi_irq'length-1 loop
+        if rst_n_i = '0' then
+          multi_irq(I) <= '0';
+        elsif irq_src_p_i(I) = '1' and irq_pending(I) = '1' then
+          multi_irq(I) <= '1';
+        elsif multi_irq_rst_en = '1' and multi_irq_rst(I) = '1' then
+          multi_irq(I) <= '0';
+        end if;
+      end loop;  -- I
+    end if;
+  end process p_multi_irq_detect;
+
+  ------------------------------------------------------------------------------
+  -- Generate IRQ output pulse
+  ------------------------------------------------------------------------------
+  irq_p_or(0) <= '0';
+  l_irq_out_pulse : for I in 0 to irq_src_p_i'length-1 generate
+    irq_p_or(I+1) <= irq_p_or(I) or (irq_src_p_i(I) and irq_en_mask(I));
+  end generate l_irq_out_pulse;
+
+  p_irq_out_pulse : process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        irq_p_o <= '0';
+      else
+        irq_p_o <= irq_p_or(32);
+      end if;
+    end if;
+  end process p_irq_out_pulse;
+
+
+end rtl;
--- a/hdl/svec/rtl/irq_controller_regs.vhd
+++ b/hdl/svec/rtl/irq_controller_regs.vhd
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for IRQ controller registers
+---------------------------------------------------------------------------------------
+-- File           : ../rtl/svec_irq_controller_regs.vhd
+-- Author         : auto-generated by wbgen2 from svec_irq_controller_regs.wb
+-- Created        : Fri Jul  5 10:18:32 2013
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE svec_irq_controller_regs.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity irq_controller_regs is
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(1 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+-- Port for std_logic_vector field: 'Multiple interrupt' in reg: 'Multiple interrupt register'
+    irq_ctrl_multi_irq_o                     : out    std_logic_vector(31 downto 0);
+    irq_ctrl_multi_irq_i                     : in     std_logic_vector(31 downto 0);
+    irq_ctrl_multi_irq_load_o                : out    std_logic;
+-- Port for std_logic_vector field: 'Interrupt sources' in reg: 'Interrupt sources register '
+    irq_ctrl_src_o                           : out    std_logic_vector(31 downto 0);
+    irq_ctrl_src_i                           : in     std_logic_vector(31 downto 0);
+    irq_ctrl_src_load_o                      : out    std_logic;
+-- Port for std_logic_vector field: 'Interrupt enable mask' in reg: 'Interrupt enable mask register'
+    irq_ctrl_en_mask_o                       : out    std_logic_vector(31 downto 0)
+  );
+end irq_controller_regs;
+
+architecture syn of irq_controller_regs is
+
+signal irq_ctrl_en_mask_int                     : std_logic_vector(31 downto 0);
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal bwsel_reg                                : std_logic_vector(3 downto 0);
+signal rwaddr_reg                               : std_logic_vector(1 downto 0);
+signal ack_in_progress                          : std_logic      ;
+signal wr_int                                   : std_logic      ;
+signal rd_int                                   : std_logic      ;
+signal allones                                  : std_logic_vector(31 downto 0);
+signal allzeros                                 : std_logic_vector(31 downto 0);
+
+begin
+-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
+  wrdata_reg <= wb_dat_i;
+  bwsel_reg <= wb_sel_i;
+  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
+  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
+  allones <= (others => '1');
+  allzeros <= (others => '0');
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      irq_ctrl_multi_irq_load_o <= '0';
+      irq_ctrl_src_load_o <= '0';
+      irq_ctrl_en_mask_int <= "00000000000000000000000000000000";
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          irq_ctrl_multi_irq_load_o <= '0';
+          irq_ctrl_src_load_o <= '0';
+          ack_in_progress <= '0';
+        else
+          irq_ctrl_multi_irq_load_o <= '0';
+          irq_ctrl_src_load_o <= '0';
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(1 downto 0) is
+          when "00" => 
+            if (wb_we_i = '1') then
+              irq_ctrl_multi_irq_load_o <= '1';
+            end if;
+            rddata_reg(31 downto 0) <= irq_ctrl_multi_irq_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "01" => 
+            if (wb_we_i = '1') then
+              irq_ctrl_src_load_o <= '1';
+            end if;
+            rddata_reg(31 downto 0) <= irq_ctrl_src_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "10" => 
+            if (wb_we_i = '1') then
+              irq_ctrl_en_mask_int <= wrdata_reg(31 downto 0);
+            end if;
+            rddata_reg(31 downto 0) <= irq_ctrl_en_mask_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- Multiple interrupt
+  irq_ctrl_multi_irq_o <= wrdata_reg(31 downto 0);
+-- Interrupt sources
+  irq_ctrl_src_o <= wrdata_reg(31 downto 0);
+-- Interrupt enable mask
+  irq_ctrl_en_mask_o <= irq_ctrl_en_mask_int;
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
--- a/hdl/svec/rtl/sdb_meta_pkg.vhd
+++ b/hdl/svec/rtl/sdb_meta_pkg.vhd
+--------------------------------------------------------------------------------
+-- CERN (BE-CO-HT)
+-- FMC ADC 100Ms/s for SVEC carrier
+-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
+--------------------------------------------------------------------------------
+--
+-- unit name: sdb_meta_pkg (sdb_meta_pkg.vhd)
+--
+-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
+--
+-- date: 05-07-2013
+--
+-- description: Sdb meta-information for the FMC ADC 100Ms/s design for SVEC.
+--
+--------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--------------------------------------------------------------------------------
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--------------------------------------------------------------------------------
+-- last changes: see git log.
+--------------------------------------------------------------------------------
+-- TODO: - 
+--------------------------------------------------------------------------------
+
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.wishbone_pkg.all;
+
+package sdb_meta_pkg is
+
+  ------------------------------------------------------------------------------
+  -- Meta-information sdb records
+  ------------------------------------------------------------------------------
+
+  -- Top module repository url
+  constant c_SDB_REPO_URL : t_sdb_repo_url := (
+    -- url (string, 63 char)
+    repo_url => "git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha.git            ");
+
+  -- Synthesis informations
+  constant c_SDB_SYNTHESIS : t_sdb_synthesis := (
+    -- Top module name (string, 16 char)
+    syn_module_name  => "svec_top_fmc_adc",
+    -- Commit ID (hex string, 128-bit = 32 char)
+    -- git log -1 --format="%H" | cut -c1-320
+    syn_commit_id    => "d8644900e0d9b8544a5e20da9d0567dd",
+    -- Synthesis tool name (string, 8 char)
+    syn_tool_name    => "ISE     ",
+    -- Synthesis tool version (bcd encoded, 32-bit)
+    syn_tool_version => x"00000133",
+    -- Synthesis date (bcd encoded, 32-bit)
+    syn_date         => x"20130704",
+    -- Synthesised by (string, 15 char)
+    syn_username     => "mcattin        ");
+
+  -- Integration record
+  constant c_SDB_INTEGRATION : t_sdb_integration := (
+    product     => (
+      vendor_id => x"000000000000CE42",  -- CERN
+      device_id => x"5c01a632",          -- echo "spec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
+      version   => x"00010001",          -- bcd encoded, [31:16] = major, [15:0] = minor
+      date      => x"20130704",          -- yyyymmdd
+      name      => "svec_fmcadc100m14b "));
+
+
+end sdb_meta_pkg;
+
+
+package body sdb_meta_pkg is
+end sdb_meta_pkg;
--- a/hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
+++ b/hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
+--------------------------------------------------------------------------------
+-- CERN (BE-CO-HT)
+-- Top level entity for Simple VME FMC Carrier
+-- http://www.ohwr.org/projects/svec
+--------------------------------------------------------------------------------
+--
+-- unit name: svec_top_fmc_adc_100Ms (svec_top_fmc_adc_100Ms.vhd)
+--
+-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
+--
+-- date: 04-07-2013
+--
+-- version: see sdb_meta_pkg.vhd
+--
+-- description: Top entity of FMC ADC 100Ms/s design for SVEC board.
+--
+-- dependencies:
+--
+--------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--------------------------------------------------------------------------------
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--------------------------------------------------------------------------------
+-- last changes: see git log.
+--------------------------------------------------------------------------------
+-- TODO: - 
+--------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+library work;
+
+use work.ddr3_ctrl_pkg.all;
+use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
+use work.fmc_adc_mezzanine_pkg.all;
+use work.sdb_meta_pkg.all;
+use work.xvme64x_core_pkg.all;
+use work.timetag_core_pkg.all;
+use work.bicolor_led_ctrl_pkg.all;
+
+
+entity svec_top_fmc_adc_100Ms is
+  generic(
+    g_SIMULATION    : string := "FALSE";
+    g_CALIB_SOFT_IP : string := "TRUE");
+  port
+    (
+      -- Local 20MHz VCXO oscillator
+      clk_20m_vcxo_i : in std_logic;
+
+      -- Reset from system fpga
+      rst_n_i : in std_logic;
+
+      -- Carrier font panel LEDs
+      fp_led_line_oen_o : out std_logic_vector(1 downto 0);
+      fp_led_line_o     : out std_logic_vector(1 downto 0);
+      fp_led_column_o   : out std_logic_vector(3 downto 0);
+
+      -- Carrier I2C eeprom
+      carrier_scl_b : inout std_logic;
+      carrier_sda_b : inout std_logic;
+
+      -- PCB revision
+      pcbrev_i : in std_logic_vector(4 downto 0);
+
+      -- Carrier 1-wire interface (DS18B20 thermometer + unique ID)
+      carrier_one_wire_b : inout std_logic;
+
+      ------------------------------------------
+      -- VME interface
+      ------------------------------------------
+      vme_write_n_i    : in    std_logic;
+      vme_sysreset_n_i : in    std_logic;
+      --vme_sysclk_i     : in    std_logic;
+      vme_retry_oe_o   : out   std_logic;
+      vme_retry_n_o    : out   std_logic;
+      vme_lword_n_b    : inout std_logic;
+      vme_iackout_n_o  : out   std_logic;
+      vme_iackin_n_i   : in    std_logic;
+      vme_iack_n_i     : in    std_logic;
+      vme_gap_i        : in    std_logic;
+      vme_dtack_oe_o   : out   std_logic;
+      vme_dtack_n_o    : out   std_logic;
+      vme_ds_n_i       : in    std_logic_vector(1 downto 0);
+      vme_data_oe_n_o  : out   std_logic;
+      vme_data_dir_o   : out   std_logic;
+      vme_berr_o       : out   std_logic;
+      vme_as_n_i       : in    std_logic;
+      vme_addr_oe_n_o  : out   std_logic;
+      vme_addr_dir_o   : out   std_logic;
+      vme_irq_n_o      : out   std_logic_vector(7 downto 1);
+      vme_ga_i         : in    std_logic_vector(5 downto 0);
+      vme_data_b       : inout std_logic_vector(31 downto 0);
+      vme_am_i         : in    std_logic_vector(5 downto 0);
+      vme_addr_b       : inout std_logic_vector(31 downto 1);
+
+      ------------------------------------------
+      -- DDR0 (bank 4)
+      ------------------------------------------
+      ddr0_we_n_o    : out   std_logic;
+      ddr0_udqs_p_b  : inout std_logic;
+      ddr0_udqs_n_b  : inout std_logic;
+      ddr0_udm_o     : out   std_logic;
+      ddr0_reset_n_o : out   std_logic;
+      ddr0_ras_n_o   : out   std_logic;
+      ddr0_odt_o     : out   std_logic;
+      ddr0_ldqs_p_b  : inout std_logic;
+      ddr0_ldqs_n_b  : inout std_logic;
+      ddr0_ldm_o     : out   std_logic;
+      ddr0_cke_o     : out   std_logic;
+      ddr0_ck_p_o    : out   std_logic;
+      ddr0_ck_n_o    : out   std_logic;
+      ddr0_cas_n_o   : out   std_logic;
+      ddr0_dq_b      : inout std_logic_vector(15 downto 0);
+      ddr0_ba_o      : out   std_logic_vector(2 downto 0);
+      ddr0_a_o       : out   std_logic_vector(13 downto 0);
+      ddr0_zio_b     : inout std_logic;
+      ddr0_rzq_b     : inout std_logic;
+
+      ------------------------------------------
+      -- DDR1 (bank 5)
+      ------------------------------------------
+      ddr1_we_n_o    : out   std_logic;
+      ddr1_udqs_p_b  : inout std_logic;
+      ddr1_udqs_n_b  : inout std_logic;
+      ddr1_udm_o     : out   std_logic;
+      ddr1_reset_n_o : out   std_logic;
+      ddr1_ras_n_o   : out   std_logic;
+      ddr1_odt_o     : out   std_logic;
+      ddr1_ldqs_p_b  : inout std_logic;
+      ddr1_ldqs_n_b  : inout std_logic;
+      ddr1_ldm_o     : out   std_logic;
+      ddr1_cke_o     : out   std_logic;
+      ddr1_ck_p_o    : out   std_logic;
+      ddr1_ck_n_o    : out   std_logic;
+      ddr1_cas_n_o   : out   std_logic;
+      ddr1_dq_b      : inout std_logic_vector(15 downto 0);
+      ddr1_ba_o      : out   std_logic_vector(2 downto 0);
+      ddr1_a_o       : out   std_logic_vector(13 downto 0);
+      ddr1_zio_b     : inout std_logic;
+      ddr1_rzq_b     : inout std_logic;
+
+      ------------------------------------------
+      -- FMC slot 0
+      ------------------------------------------
+      adc0_ext_trigger_p_i : in std_logic;  -- External trigger
+      adc0_ext_trigger_n_i : in std_logic;
+
+      adc0_dco_p_i  : in std_logic;                     -- ADC data clock
+      adc0_dco_n_i  : in std_logic;
+      adc0_fr_p_i   : in std_logic;                     -- ADC frame start
+      adc0_fr_n_i   : in std_logic;
+      adc0_outa_p_i : in std_logic_vector(3 downto 0);  -- ADC serial data (odd bits)
+      adc0_outa_n_i : in std_logic_vector(3 downto 0);
+      adc0_outb_p_i : in std_logic_vector(3 downto 0);  -- ADC serial data (even bits)
+      adc0_outb_n_i : in std_logic_vector(3 downto 0);
+
+      adc0_spi_din_i       : in  std_logic;  -- SPI data from FMC
+      adc0_spi_dout_o      : out std_logic;  -- SPI data to FMC
+      adc0_spi_sck_o       : out std_logic;  -- SPI clock
+      adc0_spi_cs_adc_n_o  : out std_logic;  -- SPI ADC chip select (active low)
+      adc0_spi_cs_dac1_n_o : out std_logic;  -- SPI channel 1 offset DAC chip select (active low)
+      adc0_spi_cs_dac2_n_o : out std_logic;  -- SPI channel 2 offset DAC chip select (active low)
+      adc0_spi_cs_dac3_n_o : out std_logic;  -- SPI channel 3 offset DAC chip select (active low)
+      adc0_spi_cs_dac4_n_o : out std_logic;  -- SPI channel 4 offset DAC chip select (active low)
+
+      adc0_gpio_dac_clr_n_o : out std_logic;                     -- offset DACs clear (active low)
+      adc0_gpio_led_acq_o   : out std_logic;                     -- Mezzanine front panel power LED (PWR)
+      adc0_gpio_led_trig_o  : out std_logic;                     -- Mezzanine front panel trigger LED (TRIG)
+      adc0_gpio_ssr_ch1_o   : out std_logic_vector(6 downto 0);  -- Channel 1 solid state relays control
+      adc0_gpio_ssr_ch2_o   : out std_logic_vector(6 downto 0);  -- Channel 2 solid state relays control
+      adc0_gpio_ssr_ch3_o   : out std_logic_vector(6 downto 0);  -- Channel 3 solid state relays control
+      adc0_gpio_ssr_ch4_o   : out std_logic_vector(6 downto 0);  -- Channel 4 solid state relays control
+      adc0_gpio_si570_oe_o  : out std_logic;                     -- Si570 (programmable oscillator) output enable
+
+      adc0_si570_scl_b : inout std_logic;  -- I2C bus clock (Si570)
+      adc0_si570_sda_b : inout std_logic;  -- I2C bus data (Si570)
+
+      adc0_one_wire_b : inout std_logic;  -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
+
+      ------------------------------------------
+      -- FMC slot 1
+      ------------------------------------------
+      adc1_ext_trigger_p_i : in std_logic;  -- External trigger
+      adc1_ext_trigger_n_i : in std_logic;
+
+      adc1_dco_p_i  : in std_logic;                     -- ADC data clock
+      adc1_dco_n_i  : in std_logic;
+      adc1_fr_p_i   : in std_logic;                     -- ADC frame start
+      adc1_fr_n_i   : in std_logic;
+      adc1_outa_p_i : in std_logic_vector(3 downto 0);  -- ADC serial data (odd bits)
+      adc1_outa_n_i : in std_logic_vector(3 downto 0);
+      adc1_outb_p_i : in std_logic_vector(3 downto 0);  -- ADC serial data (even bits)
+      adc1_outb_n_i : in std_logic_vector(3 downto 0);
+
+      adc1_spi_din_i       : in  std_logic;  -- SPI data from FMC
+      adc1_spi_dout_o      : out std_logic;  -- SPI data to FMC
+      adc1_spi_sck_o       : out std_logic;  -- SPI clock
+      adc1_spi_cs_adc_n_o  : out std_logic;  -- SPI ADC chip select (active low)
+      adc1_spi_cs_dac1_n_o : out std_logic;  -- SPI channel 1 offset DAC chip select (active low)
+      adc1_spi_cs_dac2_n_o : out std_logic;  -- SPI channel 2 offset DAC chip select (active low)
+      adc1_spi_cs_dac3_n_o : out std_logic;  -- SPI channel 3 offset DAC chip select (active low)
+      adc1_spi_cs_dac4_n_o : out std_logic;  -- SPI channel 4 offset DAC chip select (active low)
+
+      adc1_gpio_dac_clr_n_o : out std_logic;                     -- offset DACs clear (active low)
+      adc1_gpio_led_acq_o   : out std_logic;                     -- Mezzanine front panel power LED (PWR)
+      adc1_gpio_led_trig_o  : out std_logic;                     -- Mezzanine front panel trigger LED (TRIG)
+      adc1_gpio_ssr_ch1_o   : out std_logic_vector(6 downto 0);  -- Channel 1 solid state relays control
+      adc1_gpio_ssr_ch2_o   : out std_logic_vector(6 downto 0);  -- Channel 2 solid state relays control
+      adc1_gpio_ssr_ch3_o   : out std_logic_vector(6 downto 0);  -- Channel 3 solid state relays control
+      adc1_gpio_ssr_ch4_o   : out std_logic_vector(6 downto 0);  -- Channel 4 solid state relays control
+      adc1_gpio_si570_oe_o  : out std_logic;                     -- Si570 (programmable oscillator) output enable
+
+      adc1_si570_scl_b : inout std_logic;  -- I2C bus clock (Si570)
+      adc1_si570_sda_b : inout std_logic;  -- I2C bus data (Si570)
+
+      adc1_one_wire_b : inout std_logic;  -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
+
+      ------------------------------------------
+      -- FMC slot management
+      ------------------------------------------
+      fmc0_prsnt_m2c_n_i : in    std_logic;  -- Mezzanine present (active low)
+      fmc0_scl_b         : inout std_logic;  -- Mezzanine system I2C clock (EEPROM)
+      fmc0_sda_b         : inout std_logic;  -- Mezzanine system I2C data (EEPROM)
+
+      fmc1_prsnt_m2c_n_i : in    std_logic;  -- Mezzanine present (active low)
+      fmc1_scl_b         : inout std_logic;  -- Mezzanine system I2C clock (EEPROM)
+      fmc1_sda_b         : inout std_logic   -- Mezzanine system I2C data (EEPROM)
+      );
+end svec_top_fmc_adc_100Ms;
+
+
+architecture rtl of svec_top_fmc_adc_100Ms is
+
+  ------------------------------------------------------------------------------
+  -- Components declaration
+  ------------------------------------------------------------------------------
+  component carrier_csr
+    port (
+      rst_n_i                          : in  std_logic;
+      clk_sys_i                        : in  std_logic;
+      wb_adr_i                         : in  std_logic_vector(1 downto 0);
+      wb_dat_i                         : in  std_logic_vector(31 downto 0);
+      wb_dat_o                         : out std_logic_vector(31 downto 0);
+      wb_cyc_i                         : in  std_logic;
+      wb_sel_i                         : in  std_logic_vector(3 downto 0);
+      wb_stb_i                         : in  std_logic;
+      wb_we_i                          : in  std_logic;
+      wb_ack_o                         : out std_logic;
+      wb_stall_o                       : out std_logic;
+      carrier_csr_carrier_pcb_rev_i    : in  std_logic_vector(4 downto 0);
+      carrier_csr_carrier_reserved_i   : in  std_logic_vector(10 downto 0);
+      carrier_csr_carrier_type_i       : in  std_logic_vector(15 downto 0);
+      carrier_csr_stat_fmc0_pres_i     : in  std_logic;
+      carrier_csr_stat_fmc1_pres_i     : in  std_logic;
+      carrier_csr_stat_sys_pll_lck_i   : in  std_logic;
+      carrier_csr_stat_ddr0_cal_done_i : in  std_logic;
+      carrier_csr_stat_ddr1_cal_done_i : in  std_logic;
+      carrier_csr_stat_reserved_i      : in  std_logic_vector(26 downto 0);
+      carrier_csr_ctrl_fp_leds_man_o   : out std_logic_vector(15 downto 0);
+      carrier_csr_ctrl_reserved_o      : out std_logic_vector(15 downto 0)
+      );
+  end component carrier_csr;
+
+  component irq_controller
+    port (
+      clk_i       : in  std_logic;
+      rst_n_i     : in  std_logic;
+      irq_src_p_i : in  std_logic_vector(31 downto 0);
+      irq_p_o     : out std_logic;
+      wb_adr_i    : in  std_logic_vector(1 downto 0);
+      wb_dat_i    : in  std_logic_vector(31 downto 0);
+      wb_dat_o    : out std_logic_vector(31 downto 0);
+      wb_cyc_i    : in  std_logic;
+      wb_sel_i    : in  std_logic_vector(3 downto 0);
+      wb_stb_i    : in  std_logic;
+      wb_we_i     : in  std_logic;
+      wb_ack_o    : out std_logic
+      );
+  end component irq_controller;
+
+  ------------------------------------------------------------------------------
+  -- SDB crossbar constants declaration
+  --
+  -- WARNING: All address in sdb and crossbar are BYTE addresses!
+  ------------------------------------------------------------------------------
+
+  -- Number of master port(s) on the wishbone crossbar
+  constant c_NUM_WB_MASTERS : integer := 12;
+
+  -- Number of slave port(s) on the wishbone crossbar
+  constant c_NUM_WB_SLAVES : integer := 1;
+
+  -- Wishbone master(s)
+  constant c_WB_MASTER_VME : integer := 0;
+
+  -- Wishbone slave(s)
+  constant c_WB_SLAVE_I2C          : integer := 0;   -- Carrier I2C master
+  constant c_WB_SLAVE_ONEWIRE      : integer := 1;   -- Carrier onewire interface
+  constant c_WB_SLAVE_SVEC_CSR     : integer := 2;   -- SVEC control and status registers
+  constant c_WB_SLAVE_INT          : integer := 3;   -- Interrupt controller
+  constant c_WB_SLAVE_FMC0_TIMETAG : integer := 4;   -- FMC slot 1 timetag core
+  constant c_WB_SLAVE_FMC0_DDR_ADR : integer := 5;   -- FMC slot 1 DDR address
+  constant c_WB_SLAVE_FMC0_DDR_DAT : integer := 6;   -- FMC slot 1 DDR data
+  constant c_WB_SLAVE_FMC0_ADC     : integer := 7;   -- FMC slot 1 ADC mezzanine
+  constant c_WB_SLAVE_FMC1_TIMETAG : integer := 8;   -- FMC slot 2 timetag core
+  constant c_WB_SLAVE_FMC1_DDR_ADR : integer := 9;   -- FMC slot 2 DDR address
+  constant c_WB_SLAVE_FMC1_DDR_DAT : integer := 10;  -- FMC slot 2 DDR data
+  constant c_WB_SLAVE_FMC1_ADC     : integer := 11;  -- FMC slot 2 ADC mezzanine
+
+
+  -- Devices sdb description
+  constant c_DMA_SDB_DEVICE : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"4",                 -- 32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"000000000000003F",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"00000601",
+        version   => x"00000001",
+        date      => x"20121116",
+        name      => "WB-DMA.Control     ")));
+
+  constant c_ONEWIRE_SDB_DEVICE : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"4",                 -- 32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"0000000000000007",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"00000602",
+        version   => x"00000001",
+        date      => x"20121116",
+        name      => "WB-Onewire.Control ")));
+
+  constant c_SVEC_CSR_SDB_DEVICE : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"4",                 -- 32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"000000000000001F",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"00006603",
+        version   => x"00000001",
+        date      => x"20121116",
+        name      => "WB-SVEC-CSR        ")));
+
+  constant c_TIMETAG_SDB_DEVICE : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"4",                 -- 32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"000000000000007F",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"00000604",
+        version   => x"00000001",
+        date      => x"20121116",
+        name      => "WB-Timetag-Core    ")));
+
+  constant c_INT_SDB_DEVICE : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"4",                 -- 32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"000000000000000F",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"00000605",
+        version   => x"00000001",
+        date      => x"20121116",
+        name      => "WB-Int.Control     ")));
+
+  constant c_I2C_SDB_DEVICE : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"4",                 -- 32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"000000000000001F",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"00000606",
+        version   => x"00000001",
+        date      => x"20121116",
+        name      => "WB-I2C.Control     ")));
+
+  constant c_DDR_DAT_SDB_DEVICE : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"4",                 -- 32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"0000000000000007",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"10006610",
+        version   => x"00000001",
+        date      => x"20130704",
+        name      => "WB-DDR-Data-Access ")));
+
+  constant c_DDR_ADR_SDB_DEVICE : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"4",                 -- 32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"0000000000000007",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"10006611",
+        version   => x"00000001",
+        date      => x"20130704",
+        name      => "WB-DDR-Addr-Access ")));
+
+  -- f_xwb_bridge_manual_sdb(size, sdb_addr)
+  constant c_FMC_ADC0_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00003000");
+  constant c_FMC_ADC1_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00006000");
+
+  -- sdb header address
+  constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
+
+  -- Wishbone crossbar layout
+  constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(14 downto 0) :=
+    (
+      0  => f_sdb_embed_device(c_I2C_SDB_DEVICE, x"00001000"),
+      1  => f_sdb_embed_device(c_ONEWIRE_SDB_DEVICE, x"00001100"),
+      2  => f_sdb_embed_device(c_SVEC_CSR_SDB_DEVICE, x"00001200"),
+      3  => f_sdb_embed_device(c_INT_SDB_DEVICE, x"00001300"),
+      4  => f_sdb_embed_device(c_TIMETAG_SDB_DEVICE, x"00002000"),
+      5  => f_sdb_embed_device(c_DDR_DAT_SDB_DEVICE, x"00002100"),
+      6  => f_sdb_embed_device(c_DDR_ADR_SDB_DEVICE, x"00002200"),
+      7  => f_sdb_embed_bridge(c_FMC_ADC0_SDB_BRIDGE, x"00004000"),
+      8  => f_sdb_embed_device(c_TIMETAG_SDB_DEVICE, x"00006000"),
+      9  => f_sdb_embed_device(c_DDR_DAT_SDB_DEVICE, x"00006100"),
+      10 => f_sdb_embed_device(c_DDR_ADR_SDB_DEVICE, x"00006200"),
+      11 => f_sdb_embed_bridge(c_FMC_ADC1_SDB_BRIDGE, x"00008000"),
+      12 => f_sdb_embed_repo_url(c_SDB_REPO_URL),
+      13 => f_sdb_embed_synthesis(c_SDB_SYNTHESIS),
+      14 => f_sdb_embed_integration(c_SDB_INTEGRATION)
+      );
+
+  ------------------------------------------------------------------------------
+  -- Other constants declaration
+  ------------------------------------------------------------------------------
+
+  -- SVEC carrier CSR constants
+  constant c_CARRIER_TYPE : std_logic_vector(15 downto 0) := X"0002";
+
+  -- Number of FMC slots
+  constant c_NB_FMC_SLOTS : natural := 2;
+
+  ------------------------------------------------------------------------------
+  -- Signals declaration
+  ------------------------------------------------------------------------------
+
+  -- System clock
+  signal sys_clk_in         : std_logic;
+  signal sys_clk_62_5_buf   : std_logic;
+  signal sys_clk_62_5       : std_logic;
+  signal sys_clk_125_buf    : std_logic;
+  signal sys_clk_125        : std_logic;
+  signal sys_clk_fb         : std_logic;
+  signal sys_clk_pll_locked : std_logic;
+
+  -- DDR3 clock
+  signal ddr_clk     : std_logic;
+  signal ddr_clk_buf : std_logic;
+
+  -- Reset
+  signal powerup_reset_cnt : unsigned(7 downto 0) := "00000000";
+  signal powerup_rst_n     : std_logic            := '0';
+  signal sys_rst_n         : std_logic;
+  signal ddr_rst_n         : std_logic;
+
+  -- VME
+  signal vme_data_b_out    : std_logic_vector(31 downto 0);
+  signal vme_addr_b_out    : std_logic_vector(31 downto 1);
+  signal vme_lword_n_b_out : std_logic;
+  signal Vme_data_dir_int  : std_logic;
+  signal vme_addr_dir_int  : std_logic;
+
+  signal vme_access : std_logic;
+
+  -- Wishbone buses from vme core master
+  signal vme_master_out : t_wishbone_master_out;
+  signal vme_master_in  : t_wishbone_master_in;
+
+  -- Wishbone buses from vme core master (synchronised to 125MHz system clock)
+  signal vme_sync_master_out : t_wishbone_master_out;
+  signal vme_sync_master_in  : t_wishbone_master_in;
+
+  -- Wishbone buse(s) from crossbar master port(s)
+  signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
+  signal cnx_master_in  : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
+
+  -- Wishbone buse(s) to crossbar slave port(s)
+  signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
+  signal cnx_slave_in  : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
+
+  -- Wishbone buses from FMC ADC cores to DDR controller
+  signal wb_ddr0_adc_adr   : std_logic_vector(31 downto 0);
+  signal wb_ddr0_adc_dat_o : std_logic_vector(63 downto 0);
+  signal wb_ddr0_adc_sel   : std_logic_vector(7 downto 0);
+  signal wb_ddr0_adc_cyc   : std_logic;
+  signal wb_ddr0_adc_stb   : std_logic;
+  signal wb_ddr0_adc_we    : std_logic;
+  signal wb_ddr0_adc_ack   : std_logic;
+  signal wb_ddr0_adc_stall : std_logic;
+
+  signal wb_ddr1_adc_adr   : std_logic_vector(31 downto 0);
+  signal wb_ddr1_adc_dat_o : std_logic_vector(63 downto 0);
+  signal wb_ddr1_adc_sel   : std_logic_vector(7 downto 0);
+  signal wb_ddr1_adc_cyc   : std_logic;
+  signal wb_ddr1_adc_stb   : std_logic;
+  signal wb_ddr1_adc_we    : std_logic;
+  signal wb_ddr1_adc_ack   : std_logic;
+  signal wb_ddr1_adc_stall : std_logic;
+
+  -- Interrupts stuff
+  signal irq_sources          : std_logic_vector(31 downto 0);
+  signal irq_to_vme           : std_logic;
+  signal irq_sources_2_led    : std_logic_vector(31 downto 0);
+  signal ddr_wr_fifo_empty    : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
+  signal ddr_wr_fifo_empty_d  : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
+  signal ddr_wr_fifo_empty_d1 : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
+  signal ddr_wr_fifo_empty_p  : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
+  signal acq_end_irq_p        : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
+  signal acq_end_extend       : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
+
+  -- Front panel LED control
+  signal led_state     : std_logic_vector(15 downto 0);
+  signal led_state_man : std_logic_vector(15 downto 0);
+
+  -- DDR0 (bank 4)
+  signal ddr0_status     : std_logic_vector(31 downto 0);
+  signal ddr0_calib_done : std_logic;
+  signal ddr0_addr_cnt   : unsigned(31 downto 0);
+
+  -- DDR1 (bank 5)
+  signal ddr1_status     : std_logic_vector(31 downto 0);
+  signal ddr1_calib_done : std_logic;
+  signal ddr1_addr_cnt   : unsigned(31 downto 0);
+
+  -- Carrier 1-wire
+  signal carrier_owr_en : std_logic_vector(0 downto 0);
+  signal carrier_owr_i  : std_logic_vector(0 downto 0);
+
+  -- Carrier I2C for EEPROM
+  signal carrier_scl_in   : std_logic;
+  signal carrier_scl_out  : std_logic;
+  signal carrier_scl_oe_n : std_logic;
+  signal carrier_sda_in   : std_logic;
+  signal carrier_sda_out  : std_logic;
+  signal carrier_sda_oe_n : std_logic;
+
+  -- Time-tagging core
+  signal trig_p      : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
+  signal acq_start_p : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
+  signal acq_stop_p  : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
+  signal acq_end_p   : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
+
+  -- led pwm
+  signal led_pwm_update_cnt : unsigned(9 downto 0);
+  signal led_pwm_update     : std_logic;
+  signal led_pwm_val        : unsigned(16 downto 0);
+  signal led_pwm_val_down   : std_logic;
+  signal led_pwm_cnt        : unsigned(16 downto 0);
+  signal led_pwm            : std_logic;
+
+
+begin
+
+
+  ------------------------------------------------------------------------------
+  -- Clocks distribution from 20MHz TCXO
+  --  62.500 MHz system clock
+  -- 125.000 MHz system clock
+  -- 333.333 MHz DDR3 clock
+  ------------------------------------------------------------------------------
+  cmp_sys_clk_buf : IBUFG
+    port map (
+      I => clk_20m_vcxo_i,
+      O => sys_clk_in);
+
+  cmp_sys_clk_pll : PLL_BASE
+    generic map (
+      BANDWIDTH          => "OPTIMIZED",
+      CLK_FEEDBACK       => "CLKFBOUT",
+      COMPENSATION       => "INTERNAL",
+      DIVCLK_DIVIDE      => 1,
+      CLKFBOUT_MULT      => 50,
+      CLKFBOUT_PHASE     => 0.000,
+      CLKOUT0_DIVIDE     => 8,
+      CLKOUT0_PHASE      => 0.000,
+      CLKOUT0_DUTY_CYCLE => 0.500,
+      CLKOUT1_DIVIDE     => 16,
+      CLKOUT1_PHASE      => 0.000,
+      CLKOUT1_DUTY_CYCLE => 0.500,
+      CLKOUT2_DIVIDE     => 3,
+      CLKOUT2_PHASE      => 0.000,
+      CLKOUT2_DUTY_CYCLE => 0.500,
+      CLKIN_PERIOD       => 50.0,
+      REF_JITTER         => 0.016)
+    port map (
+      CLKFBOUT => sys_clk_fb,
+      CLKOUT0  => sys_clk_125_buf,
+      CLKOUT1  => sys_clk_62_5_buf,
+      CLKOUT2  => ddr_clk_buf,
+      CLKOUT3  => open,
+      CLKOUT4  => open,
+      CLKOUT5  => open,
+      LOCKED   => sys_clk_pll_locked,
+      RST      => '0',
+      CLKFBIN  => sys_clk_fb,
+      CLKIN    => sys_clk_in);
+
+  cmp_clk_62_5_buf : BUFG
+    port map (
+      O => sys_clk_62_5,
+      I => sys_clk_62_5_buf);
+
+  cmp_clk_125_buf : BUFG
+    port map (
+      O => sys_clk_125,
+      I => sys_clk_125_buf);
+
+  cmp_ddr_clk_buf : BUFG
+    port map (
+      O => ddr_clk,
+      I => ddr_clk_buf);
+
+  ------------------------------------------------------------------------------
+  -- System reset
+  ------------------------------------------------------------------------------
+  p_powerup_reset : process(sys_clk_62_5)
+  begin
+    if rising_edge(sys_clk_62_5) then
+      if(vme_sysreset_n_i = '0' or rst_n_i = '0') then
+        powerup_rst_n <= '0';
+      elsif sys_clk_pll_locked = '1' then
+        if(powerup_reset_cnt = "11111111") then
+          powerup_rst_n <= '1';
+        else
+          powerup_rst_n     <= '0';
+          powerup_reset_cnt <= powerup_reset_cnt + 1;
+        end if;
+      else
+        powerup_rst_n     <= '0';
+        powerup_reset_cnt <= "00000000";
+      end if;
+    end if;
+  end process;
+
+  --Reset synchronisation to 125MHz system clock domain
+  cmp_sync_rst : gc_sync_ffs
+    port map (
+      clk_i    => sys_clk_125,
+      rst_n_i  => '1',
+      data_i   => powerup_rst_n,
+      synced_o => sys_rst_n
+      );
+
+  -- Reset synchronisation to DDR clock domain
+  cmp_sync_ddr_rst : gc_sync_ffs
+    port map (
+      clk_i    => ddr_clk,
+      rst_n_i  => '1',
+      data_i   => powerup_rst_n,
+      synced_o => ddr_rst_n
+      );
+
+  ------------------------------------------------------------------------------
+  -- VME interface
+  ------------------------------------------------------------------------------
+  cmp_vme_Core : xvme64x_core
+    port map (
+      clk_i           => sys_clk_62_5,
+      rst_n_i         => powerup_rst_n,
+      VME_AS_n_i      => vme_as_n_i,
+      VME_RST_n_i     => powerup_rst_n,
+      VME_WRITE_n_i   => vme_write_n_i,
+      VME_AM_i        => vme_am_i,
+      VME_DS_n_i      => vme_ds_n_i,
+      VME_GA_i        => vme_ga_i,
+      VME_BERR_o      => vme_berr_o,
+      VME_DTACK_n_o   => vme_dtack_n_o,
+      VME_RETRY_n_o   => vme_retry_n_o,
+      VME_RETRY_OE_o  => vme_retry_oe_o,
+      VME_LWORD_n_b_i => vme_lword_n_b,
+      VME_LWORD_n_b_o => vme_lword_n_b_out,
+      VME_ADDR_b_i    => vme_addr_b,
+      VME_DATA_b_o    => vme_data_b_out,
+      VME_ADDR_b_o    => vme_addr_b_out,
+      VME_DATA_b_i    => vme_data_b,
+      VME_IRQ_n_o     => vme_irq_n_o,
+      VME_IACK_n_i    => vme_iack_n_i,
+      VME_IACKIN_n_i  => vme_iackin_n_i,
+      VME_IACKOUT_n_o => vme_iackout_n_o,
+      VME_DTACK_OE_o  => vme_dtack_oe_o,
+      VME_DATA_DIR_o  => vme_data_dir_int,
+      VME_DATA_OE_N_o => vme_data_oe_n_o,
+      VME_ADDR_DIR_o  => vme_addr_dir_int,
+      VME_ADDR_OE_N_o => vme_addr_oe_n_o,
+      master_o        => vme_master_out,
+      master_i        => vme_master_in,
+      irq_i           => irq_to_vme
+      );
+
+  -- VME tri-state buffers
+  vme_data_b    <= vme_data_b_out    when vme_data_dir_int = '1' else (others => 'Z');
+  vme_addr_b    <= vme_addr_b_out    when vme_addr_dir_int = '1' else (others => 'Z');
+  vme_lword_n_b <= vme_lword_n_b_out when vme_addr_dir_int = '1' else 'Z';
+
+  vme_addr_dir_o <= vme_addr_dir_int;
+  vme_data_dir_o <= vme_data_dir_int;
+
+  -- Wishbone bus synchronisation from vme 62.5MHz clock to 125MHz system clock
+  cmp_xwb_clock_crossing : xwb_clock_crossing
+    generic map(
+      sync_depth => 3,
+      log2fifo   => 4
+      )
+    port map(
+      slave_clk_i    => sys_clk_62_5,
+      slave_rst_n_i  => sys_rst_n,
+      slave_i        => vme_master_out,
+      slave_o        => vme_master_in,
+      master_clk_i   => sys_clk_125,
+      master_rst_n_i => sys_rst_n,
+      master_i       => vme_sync_master_in,
+      master_o       => vme_sync_master_out
+      );
+
+  cnx_slave_in(c_WB_MASTER_VME) <= vme_sync_master_out;
+  vme_sync_master_in            <= cnx_slave_out(c_WB_MASTER_VME);
+
+
+  ------------------------------------------------------------------------------
+  -- CSR wishbone crossbar
+  ------------------------------------------------------------------------------
+  cmp_sdb_crossbar : xwb_sdb_crossbar
+    generic map (
+      g_num_masters => c_NUM_WB_SLAVES,
+      g_num_slaves  => c_NUM_WB_MASTERS,
+      g_registered  => true,
+      g_wraparound  => true,
+      g_layout      => c_INTERCONNECT_LAYOUT,
+      g_sdb_addr    => c_SDB_ADDRESS)
+    port map (
+      clk_sys_i => sys_clk_125,
+      rst_n_i   => sys_rst_n,
+      slave_i   => cnx_slave_in,
+      slave_o   => cnx_slave_out,
+      master_i  => cnx_master_in,
+      master_o  => cnx_master_out);
+
+  ------------------------------------------------------------------------------
+  -- Carrier 1-wire master
+  --    DS18B20 (thermometer + unique ID)
+  ------------------------------------------------------------------------------
+  cmp_carrier_onewire : xwb_onewire_master
+    generic map(
+      g_interface_mode      => CLASSIC,
+      g_address_granularity => BYTE,
+      g_num_ports           => 1,
+      g_ow_btp_normal       => "5.0",
+      g_ow_btp_overdrive    => "1.0"
+      )
+    port map(
+      clk_sys_i => sys_clk_125,
+      rst_n_i   => sys_rst_n,
+
+      slave_i => cnx_master_out(c_WB_SLAVE_ONEWIRE),
+      slave_o => cnx_master_in(c_WB_SLAVE_ONEWIRE),
+      desc_o  => open,
+
+      owr_pwren_o => open,
+      owr_en_o    => carrier_owr_en,
+      owr_i       => carrier_owr_i
+      );
+
+  carrier_one_wire_b <= '0' when carrier_owr_en(0) = '1' else 'Z';
+  carrier_owr_i(0)   <= carrier_one_wire_b;
+
+  ------------------------------------------------------------------------------
+  -- I2C master
+  --    Carrier EEPROM
+  ------------------------------------------------------------------------------
+  cmp_carrier_i2c : xwb_i2c_master
+    generic map(
+      g_interface_mode      => CLASSIC,
+      g_address_granularity => BYTE
+      )
+    port map (
+      clk_sys_i => sys_clk_125,
+      rst_n_i   => sys_rst_n,
+
+      slave_i => cnx_master_out(c_WB_SLAVE_I2C),
+      slave_o => cnx_master_in(c_WB_SLAVE_I2C),
+      desc_o  => open,
+
+      scl_pad_i    => carrier_scl_in,
+      scl_pad_o    => carrier_scl_out,
+      scl_padoen_o => carrier_scl_oe_n,
+      sda_pad_i    => carrier_sda_in,
+      sda_pad_o    => carrier_sda_out,
+      sda_padoen_o => carrier_sda_oe_n
+      );
+
+  -- Tri-state buffer for SDA and SCL
+  carrier_scl_b  <= carrier_scl_out when carrier_scl_oe_n = '0' else 'Z';
+  carrier_scl_in <= carrier_scl_b;
+
+  carrier_sda_b  <= carrier_sda_out when carrier_sda_oe_n = '0' else 'Z';
+  carrier_sda_in <= carrier_sda_b;
+
+  ------------------------------------------------------------------------------
+  -- Carrier CSR
+  --    Carrier type and PCB version
+  --    Carrier status (PLL, FMC presence)
+  --    Front panel LED manual control
+  ------------------------------------------------------------------------------
+  cmp_carrier_csr : carrier_csr
+    port map(
+      rst_n_i                          => sys_rst_n,
+      clk_sys_i                        => sys_clk_125,
+      wb_adr_i                         => cnx_master_out(c_WB_SLAVE_SVEC_CSR).adr(3 downto 2),  -- cnx_master_out.adr is byte address
+      wb_dat_i                         => cnx_master_out(c_WB_SLAVE_SVEC_CSR).dat,
+      wb_dat_o                         => cnx_master_in(c_WB_SLAVE_SVEC_CSR).dat,
+      wb_cyc_i                         => cnx_master_out(c_WB_SLAVE_SVEC_CSR).cyc,
+      wb_sel_i                         => cnx_master_out(c_WB_SLAVE_SVEC_CSR).sel,
+      wb_stb_i                         => cnx_master_out(c_WB_SLAVE_SVEC_CSR).stb,
+      wb_we_i                          => cnx_master_out(c_WB_SLAVE_SVEC_CSR).we,
+      wb_ack_o                         => cnx_master_in(c_WB_SLAVE_SVEC_CSR).ack,
+      wb_stall_o                       => open,
+      carrier_csr_carrier_pcb_rev_i    => pcbrev_i,
+      carrier_csr_carrier_reserved_i   => (others => '0'),
+      carrier_csr_carrier_type_i       => c_CARRIER_TYPE,
+      carrier_csr_stat_fmc0_pres_i     => fmc0_prsnt_m2c_n_i,
+      carrier_csr_stat_fmc1_pres_i     => fmc1_prsnt_m2c_n_i,
+      carrier_csr_stat_sys_pll_lck_i   => sys_clk_pll_locked,
+      carrier_csr_stat_ddr0_cal_done_i => ddr0_calib_done,
+      carrier_csr_stat_ddr1_cal_done_i => ddr1_calib_done,
+      carrier_csr_stat_reserved_i      => (others => '0'),
+      carrier_csr_ctrl_fp_leds_man_o   => led_state_man,
+      carrier_csr_ctrl_reserved_o      => open
+      );
+
+  -- Unused wishbone signals
+  cnx_master_in(c_WB_SLAVE_SVEC_CSR).err   <= '0';
+  cnx_master_in(c_WB_SLAVE_SVEC_CSR).rty   <= '0';
+  cnx_master_in(c_WB_SLAVE_SVEC_CSR).stall <= '0';
+  cnx_master_in(c_WB_SLAVE_SVEC_CSR).int   <= '0';
+
+  ------------------------------------------------------------------------------
+  -- Interrupt controller
+  ------------------------------------------------------------------------------
+  cmp_irq_controller : irq_controller
+    port map(
+      clk_i       => sys_clk_125,
+      rst_n_i     => sys_rst_n,
+      irq_src_p_i => irq_sources,
+      irq_p_o     => irq_to_vme,
+      wb_adr_i    => cnx_master_out(c_WB_SLAVE_INT).adr(3 downto 2),  -- cnx_master_out.adr is byte address
+      wb_dat_i    => cnx_master_out(c_WB_SLAVE_INT).dat,
+      wb_dat_o    => cnx_master_in(c_WB_SLAVE_INT).dat,
+      wb_cyc_i    => cnx_master_out(c_WB_SLAVE_INT).cyc,
+      wb_sel_i    => cnx_master_out(c_WB_SLAVE_INT).sel,
+      wb_stb_i    => cnx_master_out(c_WB_SLAVE_INT).stb,
+      wb_we_i     => cnx_master_out(c_WB_SLAVE_INT).we,
+      wb_ack_o    => cnx_master_in(c_WB_SLAVE_INT).ack
+      );
+
+  -- Unused wishbone signals
+  cnx_master_in(c_WB_SLAVE_INT).err   <= '0';
+  cnx_master_in(c_WB_SLAVE_INT).rty   <= '0';
+  cnx_master_in(c_WB_SLAVE_INT).stall <= '0';
+  cnx_master_in(c_WB_SLAVE_INT).int   <= '0';
+
+  -- IRQ sources
+  --   0    -> FMC slot 1 trigger
+  --   1    -> FMC slot 1 end of acquisition (data written to DDR)
+  --   2    -> FMC slot 2 trigger
+  --   3    -> FMC slot 2 end of acquisition (data written to DDR)
+  --   4-31 -> Unused
+  irq_sources(0)           <= trig_p(0);
+  irq_sources(1)           <= acq_end_irq_p(0);
+  irq_sources(2)           <= trig_p(1);
+  irq_sources(3)           <= acq_end_irq_p(1);
+  irq_sources(31 downto 4) <= (others => '0');
+
+  -- Detects end of adc core writing to ddr
+  l_ddr_wr_fifo_empty : for I in 0 to c_NB_FMC_SLOTS-1 generate
+    p_ddr_wr_fifo_empty : process (sys_clk_125)
+    begin
+      if rising_edge(sys_clk_125) then
+        if sys_rst_n = '0' then
+          ddr_wr_fifo_empty_d(I) <= '0';
+          ddr_wr_fifo_empty_d1(I) <= '0';
+        else
+          ddr_wr_fifo_empty_d(I) <= ddr_wr_fifo_empty(I);
+          ddr_wr_fifo_empty_d1(I) <= ddr_wr_fifo_empty_d(I);
+        end if;
+      end if;
+    end process p_ddr_wr_fifo_empty;
+    ddr_wr_fifo_empty_p(I) <= ddr_wr_fifo_empty_d(I) and not(ddr_wr_fifo_empty_d1(I));
+  end generate l_ddr_wr_fifo_empty;
+
+  -- End of acquisition interrupt generation
+  l_acq_end_irq : for I in 0 to c_NB_FMC_SLOTS-1 generate
+    p_acq_end_extend : process (sys_clk_125)
+    begin
+      if rising_edge(sys_clk_125) then
+        if sys_rst_n = '0' then
+          acq_end_extend(I) <= '0';
+        elsif acq_end_p(I) = '1' then
+          acq_end_extend(I) <= '1';
+        elsif ddr_wr_fifo_empty_p(I) = '1' then
+          acq_end_extend(I) <= '0';
+        end if;
+      end if;
+    end process p_acq_end_extend;
+    acq_end_irq_p(I) <= ddr_wr_fifo_empty_p(I) and acq_end_extend(I);
+  end generate l_acq_end_irq;
+
+  ------------------------------------------------------------------------------
+  -- Slot 1 : FMC ADC mezzanine (wb bridge)
+  --    Mezzanine system managment I2C master
+  --    Mezzanine SPI master
+  --    Mezzanine I2C
+  --    ADC core
+  --    Mezzanine 1-wire master
+  ------------------------------------------------------------------------------
+  cmp_fmc_adc_mezzanine_0 : fmc_adc_mezzanine
+    generic map(
+      g_multishot_ram_size => 2048
+      )
+    port map(
+      sys_clk_i   => sys_clk_125,
+      sys_rst_n_i => sys_rst_n,
+
+      wb_csr_adr_i   => cnx_master_out(c_WB_SLAVE_FMC0_ADC).adr,
+      wb_csr_dat_i   => cnx_master_out(c_WB_SLAVE_FMC0_ADC).dat,
+      wb_csr_dat_o   => cnx_master_in(c_WB_SLAVE_FMC0_ADC).dat,
+      wb_csr_cyc_i   => cnx_master_out(c_WB_SLAVE_FMC0_ADC).cyc,
+      wb_csr_sel_i   => cnx_master_out(c_WB_SLAVE_FMC0_ADC).sel,
+      wb_csr_stb_i   => cnx_master_out(c_WB_SLAVE_FMC0_ADC).stb,
+      wb_csr_we_i    => cnx_master_out(c_WB_SLAVE_FMC0_ADC).we,
+      wb_csr_ack_o   => cnx_master_in(c_WB_SLAVE_FMC0_ADC).ack,
+      wb_csr_stall_o => cnx_master_in(c_WB_SLAVE_FMC0_ADC).stall,
+
+      wb_ddr_clk_i   => sys_clk_125,
+      wb_ddr_adr_o   => wb_ddr0_adc_adr,
+      wb_ddr_dat_o   => wb_ddr0_adc_dat_o,
+      wb_ddr_sel_o   => wb_ddr0_adc_sel,
+      wb_ddr_stb_o   => wb_ddr0_adc_stb,
+      wb_ddr_we_o    => wb_ddr0_adc_we,
+      wb_ddr_cyc_o   => wb_ddr0_adc_cyc,
+      wb_ddr_ack_i   => wb_ddr0_adc_ack,
+      wb_ddr_stall_i => wb_ddr0_adc_stall,
+
+      trigger_p_o   => trig_p(0),
+      acq_start_p_o => acq_start_p(0),
+      acq_stop_p_o  => acq_stop_p(0),
+      acq_end_p_o   => acq_end_p(0),
+
+      ext_trigger_p_i => adc0_ext_trigger_p_i,
+      ext_trigger_n_i => adc0_ext_trigger_n_i,
+
+      adc_dco_p_i  => adc0_dco_p_i,
+      adc_dco_n_i  => adc0_dco_n_i,
+      adc_fr_p_i   => adc0_fr_p_i,
+      adc_fr_n_i   => adc0_fr_n_i,
+      adc_outa_p_i => adc0_outa_p_i,
+      adc_outa_n_i => adc0_outa_n_i,
+      adc_outb_p_i => adc0_outb_p_i,
+      adc_outb_n_i => adc0_outb_n_i,
+
+      gpio_dac_clr_n_o => adc0_gpio_dac_clr_n_o,
+      gpio_led_acq_o   => adc0_gpio_led_acq_o,
+      gpio_led_trig_o  => adc0_gpio_led_trig_o,
+      gpio_ssr_ch1_o   => adc0_gpio_ssr_ch1_o,
+      gpio_ssr_ch2_o   => adc0_gpio_ssr_ch2_o,
+      gpio_ssr_ch3_o   => adc0_gpio_ssr_ch3_o,
+      gpio_ssr_ch4_o   => adc0_gpio_ssr_ch4_o,
+      gpio_si570_oe_o  => adc0_gpio_si570_oe_o,
+
+      spi_din_i       => adc0_spi_din_i,
+      spi_dout_o      => adc0_spi_dout_o,
+      spi_sck_o       => adc0_spi_sck_o,
+      spi_cs_adc_n_o  => adc0_spi_cs_adc_n_o,
+      spi_cs_dac1_n_o => adc0_spi_cs_dac1_n_o,
+      spi_cs_dac2_n_o => adc0_spi_cs_dac2_n_o,
+      spi_cs_dac3_n_o => adc0_spi_cs_dac3_n_o,
+      spi_cs_dac4_n_o => adc0_spi_cs_dac4_n_o,
+
+      si570_scl_b => adc0_si570_scl_b,
+      si570_sda_b => adc0_si570_sda_b,
+
+      mezz_one_wire_b => adc0_one_wire_b,
+
+      sys_scl_b => fmc0_scl_b,
+      sys_sda_b => fmc0_sda_b
+      );
+
+  -- Unused wishbone signals
+  cnx_master_in(c_WB_SLAVE_FMC0_ADC).err <= '0';
+  cnx_master_in(c_WB_SLAVE_FMC0_ADC).rty <= '0';
+  cnx_master_in(c_WB_SLAVE_FMC0_ADC).int <= '0';
+
+  ------------------------------------------------------------------------------
+  -- Slot 2 : FMC ADC mezzanine (wb bridge)
+  --    Mezzanine system managment I2C master
+  --    Mezzanine SPI master
+  --    Mezzanine I2C
+  --    ADC core
+  --    Mezzanine 1-wire master
+  ------------------------------------------------------------------------------
+  cmp_fmc_adc_mezzanine_1 : fmc_adc_mezzanine
+    generic map(
+      g_multishot_ram_size => 2048
+      )
+    port map(
+      sys_clk_i   => sys_clk_125,
+      sys_rst_n_i => sys_rst_n,
+
+      wb_csr_adr_i   => cnx_master_out(c_WB_SLAVE_FMC1_ADC).adr,
+      wb_csr_dat_i   => cnx_master_out(c_WB_SLAVE_FMC1_ADC).dat,
+      wb_csr_dat_o   => cnx_master_in(c_WB_SLAVE_FMC1_ADC).dat,
+      wb_csr_cyc_i   => cnx_master_out(c_WB_SLAVE_FMC1_ADC).cyc,
+      wb_csr_sel_i   => cnx_master_out(c_WB_SLAVE_FMC1_ADC).sel,
+      wb_csr_stb_i   => cnx_master_out(c_WB_SLAVE_FMC1_ADC).stb,
+      wb_csr_we_i    => cnx_master_out(c_WB_SLAVE_FMC1_ADC).we,
+      wb_csr_ack_o   => cnx_master_in(c_WB_SLAVE_FMC1_ADC).ack,
+      wb_csr_stall_o => cnx_master_in(c_WB_SLAVE_FMC1_ADC).stall,
+
+      wb_ddr_clk_i   => sys_clk_125,
+      wb_ddr_adr_o   => wb_ddr1_adc_adr,
+      wb_ddr_dat_o   => wb_ddr1_adc_dat_o,
+      wb_ddr_sel_o   => wb_ddr1_adc_sel,
+      wb_ddr_stb_o   => wb_ddr1_adc_stb,
+      wb_ddr_we_o    => wb_ddr1_adc_we,
+      wb_ddr_cyc_o   => wb_ddr1_adc_cyc,
+      wb_ddr_ack_i   => wb_ddr1_adc_ack,
+      wb_ddr_stall_i => wb_ddr1_adc_stall,
+
+      trigger_p_o   => trig_p(1),
+      acq_start_p_o => acq_start_p(1),
+      acq_stop_p_o  => acq_stop_p(1),
+      acq_end_p_o   => acq_end_p(1),
+
+      ext_trigger_p_i => adc1_ext_trigger_p_i,
+      ext_trigger_n_i => adc1_ext_trigger_n_i,
+
+      adc_dco_p_i  => adc1_dco_p_i,
+      adc_dco_n_i  => adc1_dco_n_i,
+      adc_fr_p_i   => adc1_fr_p_i,
+      adc_fr_n_i   => adc1_fr_n_i,
+      adc_outa_p_i => adc1_outa_p_i,
+      adc_outa_n_i => adc1_outa_n_i,
+      adc_outb_p_i => adc1_outb_p_i,
+      adc_outb_n_i => adc1_outb_n_i,
+
+      gpio_dac_clr_n_o => adc1_gpio_dac_clr_n_o,
+      gpio_led_acq_o   => adc1_gpio_led_acq_o,
+      gpio_led_trig_o  => adc1_gpio_led_trig_o,
+      gpio_ssr_ch1_o   => adc1_gpio_ssr_ch1_o,
+      gpio_ssr_ch2_o   => adc1_gpio_ssr_ch2_o,
+      gpio_ssr_ch3_o   => adc1_gpio_ssr_ch3_o,
+      gpio_ssr_ch4_o   => adc1_gpio_ssr_ch4_o,
+      gpio_si570_oe_o  => adc1_gpio_si570_oe_o,
+
+      spi_din_i       => adc1_spi_din_i,
+      spi_dout_o      => adc1_spi_dout_o,
+      spi_sck_o       => adc1_spi_sck_o,
+      spi_cs_adc_n_o  => adc1_spi_cs_adc_n_o,
+      spi_cs_dac1_n_o => adc1_spi_cs_dac1_n_o,
+      spi_cs_dac2_n_o => adc1_spi_cs_dac2_n_o,
+      spi_cs_dac3_n_o => adc1_spi_cs_dac3_n_o,
+      spi_cs_dac4_n_o => adc1_spi_cs_dac4_n_o,
+
+      si570_scl_b => adc1_si570_scl_b,
+      si570_sda_b => adc1_si570_sda_b,
+
+      mezz_one_wire_b => adc1_one_wire_b,
+
+      sys_scl_b => fmc1_scl_b,
+      sys_sda_b => fmc1_sda_b
+      );
+
+  -- Unused wishbone signals
+  cnx_master_in(c_WB_SLAVE_FMC1_ADC).err <= '0';
+  cnx_master_in(c_WB_SLAVE_FMC1_ADC).rty <= '0';
+  cnx_master_in(c_WB_SLAVE_FMC1_ADC).int <= '0';
+
+  ------------------------------------------------------------------------------
+  -- DDR0 controller (bank 4)
+  ------------------------------------------------------------------------------
+  cmp_ddr_ctrl_bank4 : ddr3_ctrl
+    generic map(
+      g_BANK_PORT_SELECT   => "SVEC_BANK4_64B_32B",
+      g_MEMCLK_PERIOD      => 3000,
+      g_SIMULATION         => g_SIMULATION,
+      g_CALIB_SOFT_IP      => g_CALIB_SOFT_IP,
+      g_P0_MASK_SIZE       => 8,
+      g_P0_DATA_PORT_SIZE  => 64,
+      g_P0_BYTE_ADDR_WIDTH => 30,
+      g_P1_MASK_SIZE       => 4,
+      g_P1_DATA_PORT_SIZE  => 32,
+      g_P1_BYTE_ADDR_WIDTH => 30)
+    port map (
+      clk_i   => ddr_clk,
+      rst_n_i => ddr_rst_n,
+
+      status_o => ddr0_status,
+
+      ddr3_dq_b     => ddr0_dq_b,
+      ddr3_a_o      => ddr0_a_o,
+      ddr3_ba_o     => ddr0_ba_o,
+      ddr3_ras_n_o  => ddr0_ras_n_o,
+      ddr3_cas_n_o  => ddr0_cas_n_o,
+      ddr3_we_n_o   => ddr0_we_n_o,
+      ddr3_odt_o    => ddr0_odt_o,
+      ddr3_rst_n_o  => ddr0_reset_n_o,
+      ddr3_cke_o    => ddr0_cke_o,
+      ddr3_dm_o     => ddr0_ldm_o,
+      ddr3_udm_o    => ddr0_udm_o,
+      ddr3_dqs_p_b  => ddr0_ldqs_p_b,
+      ddr3_dqs_n_b  => ddr0_ldqs_n_b,
+      ddr3_udqs_p_b => ddr0_udqs_p_b,
+      ddr3_udqs_n_b => ddr0_udqs_n_b,
+      ddr3_clk_p_o  => ddr0_ck_p_o,
+      ddr3_clk_n_o  => ddr0_ck_n_o,
+      ddr3_rzq_b    => ddr0_rzq_b,
+      ddr3_zio_b    => ddr0_zio_b,
+
+      wb0_clk_i   => sys_clk_125,
+      wb0_sel_i   => wb_ddr0_adc_sel,
+      wb0_cyc_i   => wb_ddr0_adc_cyc,
+      wb0_stb_i   => wb_ddr0_adc_stb,
+      wb0_we_i    => wb_ddr0_adc_we,
+      wb0_addr_i  => wb_ddr0_adc_adr,
+      wb0_data_i  => wb_ddr0_adc_dat_o,
+      wb0_data_o  => open,
+      wb0_ack_o   => wb_ddr0_adc_ack,
+      wb0_stall_o => wb_ddr0_adc_stall,
+
+      p0_cmd_empty_o   => open,
+      p0_cmd_full_o    => open,
+      p0_rd_full_o     => open,
+      p0_rd_empty_o    => open,
+      p0_rd_count_o    => open,
+      p0_rd_overflow_o => open,
+      p0_rd_error_o    => open,
+      p0_wr_full_o     => open,
+      p0_wr_empty_o    => ddr_wr_fifo_empty(0),
+      p0_wr_count_o    => open,
+      p0_wr_underrun_o => open,
+      p0_wr_error_o    => open,
+
+      wb1_clk_i   => sys_clk_125,
+      wb1_sel_i   => cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).sel,
+      wb1_cyc_i   => cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).cyc,
+      wb1_stb_i   => cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).stb,
+      wb1_we_i    => cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).we,
+      wb1_addr_i  => std_logic_vector(ddr0_addr_cnt),
+      wb1_data_i  => cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).dat,
+      wb1_data_o  => cnx_master_in(c_WB_SLAVE_FMC0_DDR_DAT).dat,
+      wb1_ack_o   => cnx_master_in(c_WB_SLAVE_FMC0_DDR_DAT).ack,
+      wb1_stall_o => cnx_master_in(c_WB_SLAVE_FMC0_DDR_DAT).stall,
+
+      p1_cmd_empty_o   => open,
+      p1_cmd_full_o    => open,
+      p1_rd_full_o     => open,
+      p1_rd_empty_o    => open,
+      p1_rd_count_o    => open,
+      p1_rd_overflow_o => open,
+      p1_rd_error_o    => open,
+      p1_wr_full_o     => open,
+      p1_wr_empty_o    => open,
+      p1_wr_count_o    => open,
+      p1_wr_underrun_o => open,
+      p1_wr_error_o    => open
+
+      );
+
+  ddr0_calib_done <= ddr0_status(0);
+
+  -- DDR0 (bank 4) address counter
+  --  The address counter is set by writing to the c_WB_SLAVE_FMC0_DDR_ADR wishbone periph.
+  --  Than the counter is incremented on every access to the c_WB_SLAVE_FMC0_DDR_DAT wishbone periph.
+  p_ddr0_addr_cnt : process (sys_clk_125)
+  begin
+    if rising_edge(sys_clk_125) then
+      if (sys_rst_n = '0') then
+        ddr0_addr_cnt <= (others => '0');
+      elsif (cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).we = '1' and
+             cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).stb = '1' and
+             cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).cyc = '1') then
+        ddr0_addr_cnt <= unsigned(cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).dat);
+      elsif (cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).stb = '1' and
+             cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).cyc = '1') then
+        ddr0_addr_cnt <= ddr0_addr_cnt + 1;
+      end if;
+    end if;
+  end process p_ddr0_addr_cnt;
+
+  -- ACK generation
+  p_ddr0_addr_ack : process (sys_clk_125)
+  begin
+    if rising_edge(sys_clk_125) then
+      if (sys_rst_n = '0') then
+        cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).ack <= '0';
+      elsif (cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).stb = '1' and
+             cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).cyc = '1') then
+        cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).ack <= '1';
+      else
+        cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).ack <= '0';
+      end if;
+    end if;
+  end process p_ddr0_addr_ack;
+
+  -- Address counter read back
+  cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).dat <= std_logic_vector(ddr0_addr_cnt);
+
+  -- Unused wishbone signals
+  cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).err   <= '0';
+  cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).rty   <= '0';
+  cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).stall <= '0';
+  cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).int   <= '0';
+
+  ------------------------------------------------------------------------------
+  -- DDR1 controller (bank 5)
+  ------------------------------------------------------------------------------
+  cmp_ddr_ctrl_bank5 : ddr3_ctrl
+    generic map(
+      g_BANK_PORT_SELECT   => "SVEC_BANK5_64B_32B",
+      g_MEMCLK_PERIOD      => 3000,
+      g_SIMULATION         => g_SIMULATION,
+      g_CALIB_SOFT_IP      => g_CALIB_SOFT_IP,
+      g_P0_MASK_SIZE       => 8,
+      g_P0_DATA_PORT_SIZE  => 64,
+      g_P0_BYTE_ADDR_WIDTH => 30,
+      g_P1_MASK_SIZE       => 4,
+      g_P1_DATA_PORT_SIZE  => 32,
+      g_P1_BYTE_ADDR_WIDTH => 30)
+    port map (
+      clk_i   => ddr_clk,
+      rst_n_i => ddr_rst_n,
+
+      status_o => ddr1_status,
+
+      ddr3_dq_b     => ddr1_dq_b,
+      ddr3_a_o      => ddr1_a_o,
+      ddr3_ba_o     => ddr1_ba_o,
+      ddr3_ras_n_o  => ddr1_ras_n_o,
+      ddr3_cas_n_o  => ddr1_cas_n_o,
+      ddr3_we_n_o   => ddr1_we_n_o,
+      ddr3_odt_o    => ddr1_odt_o,
+      ddr3_rst_n_o  => ddr1_reset_n_o,
+      ddr3_cke_o    => ddr1_cke_o,
+      ddr3_dm_o     => ddr1_ldm_o,
+      ddr3_udm_o    => ddr1_udm_o,
+      ddr3_dqs_p_b  => ddr1_ldqs_p_b,
+      ddr3_dqs_n_b  => ddr1_ldqs_n_b,
+      ddr3_udqs_p_b => ddr1_udqs_p_b,
+      ddr3_udqs_n_b => ddr1_udqs_n_b,
+      ddr3_clk_p_o  => ddr1_ck_p_o,
+      ddr3_clk_n_o  => ddr1_ck_n_o,
+      ddr3_rzq_b    => ddr1_rzq_b,
+      ddr3_zio_b    => ddr1_zio_b,
+
+      wb0_clk_i   => sys_clk_125,
+      wb0_sel_i   => wb_ddr1_adc_sel,
+      wb0_cyc_i   => wb_ddr1_adc_cyc,
+      wb0_stb_i   => wb_ddr1_adc_stb,
+      wb0_we_i    => wb_ddr1_adc_we,
+      wb0_addr_i  => wb_ddr1_adc_adr,
+      wb0_data_i  => wb_ddr1_adc_dat_o,
+      wb0_data_o  => open,
+      wb0_ack_o   => wb_ddr1_adc_ack,
+      wb0_stall_o => wb_ddr1_adc_stall,
+
+      p0_cmd_empty_o   => open,
+      p0_cmd_full_o    => open,
+      p0_rd_full_o     => open,
+      p0_rd_empty_o    => open,
+      p0_rd_count_o    => open,
+      p0_rd_overflow_o => open,
+      p0_rd_error_o    => open,
+      p0_wr_full_o     => open,
+      p0_wr_empty_o    => ddr_wr_fifo_empty(1),
+      p0_wr_count_o    => open,
+      p0_wr_underrun_o => open,
+      p0_wr_error_o    => open,
+
+      wb1_clk_i   => sys_clk_125,
+      wb1_sel_i   => cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).sel,
+      wb1_cyc_i   => cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).cyc,
+      wb1_stb_i   => cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).stb,
+      wb1_we_i    => cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).we,
+      wb1_addr_i  => std_logic_vector(ddr1_addr_cnt),
+      wb1_data_i  => cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).dat,
+      wb1_data_o  => cnx_master_in(c_WB_SLAVE_FMC1_DDR_DAT).dat,
+      wb1_ack_o   => cnx_master_in(c_WB_SLAVE_FMC1_DDR_DAT).ack,
+      wb1_stall_o => cnx_master_in(c_WB_SLAVE_FMC1_DDR_DAT).stall,
+
+      p1_cmd_empty_o   => open,
+      p1_cmd_full_o    => open,
+      p1_rd_full_o     => open,
+      p1_rd_empty_o    => open,
+      p1_rd_count_o    => open,
+      p1_rd_overflow_o => open,
+      p1_rd_error_o    => open,
+      p1_wr_full_o     => open,
+      p1_wr_empty_o    => open,
+      p1_wr_count_o    => open,
+      p1_wr_underrun_o => open,
+      p1_wr_error_o    => open
+
+      );
+
+  ddr1_calib_done <= ddr1_status(0);
+
+  -- DDR1 (bank 5) address counter
+  --  The address counter is set by writing to the c_WB_SLAVE_FMC1_DDR_ADR wishbone periph.
+  --  Than the counter is incremented on every access to the c_WB_SLAVE_FMC1_DDR_DAT wishbone periph.
+  p_ddr1_addr_cnt : process (sys_clk_125)
+  begin
+    if rising_edge(sys_clk_125) then
+      if (sys_rst_n = '0') then
+        ddr1_addr_cnt <= (others => '0');
+      elsif (cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).we = '1' and
+             cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).stb = '1' and
+             cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).cyc = '1') then
+        ddr1_addr_cnt <= unsigned(cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).dat);
+      elsif (cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).stb = '1' and
+             cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).cyc = '1') then
+        ddr1_addr_cnt <= ddr1_addr_cnt + 1;
+      end if;
+    end if;
+  end process p_ddr1_addr_cnt;
+
+  -- ACK generation
+  p_ddr1_addr_ack : process (sys_clk_125)
+  begin
+    if rising_edge(sys_clk_125) then
+      if (sys_rst_n = '0') then
+        cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).ack <= '0';
+      elsif (cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).stb = '1' and
+             cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).cyc = '1') then
+        cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).ack <= '1';
+      else
+        cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).ack <= '0';
+      end if;
+    end if;
+  end process p_ddr1_addr_ack;
+
+  -- Address counter read back
+  cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).dat <= std_logic_vector(ddr1_addr_cnt);
+
+  -- Unused wishbone signals
+  cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).err   <= '0';
+  cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).rty   <= '0';
+  cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).stall <= '0';
+  cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).int   <= '0';
+
+  ------------------------------------------------------------------------------
+  -- FMC slot 1 : Time-tagging core
+  ------------------------------------------------------------------------------
+  cmp_fmc0_timetag_core : timetag_core
+    port map(
+      clk_i   => sys_clk_125,
+      rst_n_i => sys_rst_n,
+
+      trigger_p_i   => trig_p(0),
+      acq_start_p_i => acq_start_p(0),
+      acq_stop_p_i  => acq_stop_p(0),
+      acq_end_p_i   => acq_end_p(0),
+
+      wb_adr_i => cnx_master_out(c_WB_SLAVE_FMC0_TIMETAG).adr(6 downto 2),  -- cnx_master_out.adr is byte address
+      wb_dat_i => cnx_master_out(c_WB_SLAVE_FMC0_TIMETAG).dat,
+      wb_dat_o => cnx_master_in(c_WB_SLAVE_FMC0_TIMETAG).dat,
+      wb_cyc_i => cnx_master_out(c_WB_SLAVE_FMC0_TIMETAG).cyc,
+      wb_sel_i => cnx_master_out(c_WB_SLAVE_FMC0_TIMETAG).sel,
+      wb_stb_i => cnx_master_out(c_WB_SLAVE_FMC0_TIMETAG).stb,
+      wb_we_i  => cnx_master_out(c_WB_SLAVE_FMC0_TIMETAG).we,
+      wb_ack_o => cnx_master_in(c_WB_SLAVE_FMC0_TIMETAG).ack
+      );
+
+  -- Unused wishbone signals
+  cnx_master_in(c_WB_SLAVE_FMC0_TIMETAG).err   <= '0';
+  cnx_master_in(c_WB_SLAVE_FMC0_TIMETAG).rty   <= '0';
+  cnx_master_in(c_WB_SLAVE_FMC0_TIMETAG).stall <= '0';
+  cnx_master_in(c_WB_SLAVE_FMC0_TIMETAG).int   <= '0';
+
+  ------------------------------------------------------------------------------
+  -- FMC slot 2 : Time-tagging core
+  ------------------------------------------------------------------------------
+  cmp_fmc1_timetag_core : timetag_core
+    port map(
+      clk_i   => sys_clk_125,
+      rst_n_i => sys_rst_n,
+
+      trigger_p_i   => trig_p(1),
+      acq_start_p_i => acq_start_p(1),
+      acq_stop_p_i  => acq_stop_p(1),
+      acq_end_p_i   => acq_end_p(1),
+
+      wb_adr_i => cnx_master_out(c_WB_SLAVE_FMC1_TIMETAG).adr(6 downto 2),  -- cnx_master_out.adr is byte address
+      wb_dat_i => cnx_master_out(c_WB_SLAVE_FMC1_TIMETAG).dat,
+      wb_dat_o => cnx_master_in(c_WB_SLAVE_FMC1_TIMETAG).dat,
+      wb_cyc_i => cnx_master_out(c_WB_SLAVE_FMC1_TIMETAG).cyc,
+      wb_sel_i => cnx_master_out(c_WB_SLAVE_FMC1_TIMETAG).sel,
+      wb_stb_i => cnx_master_out(c_WB_SLAVE_FMC1_TIMETAG).stb,
+      wb_we_i  => cnx_master_out(c_WB_SLAVE_FMC1_TIMETAG).we,
+      wb_ack_o => cnx_master_in(c_WB_SLAVE_FMC1_TIMETAG).ack
+      );
+
+  -- Unused wishbone signals
+  cnx_master_in(c_WB_SLAVE_FMC1_TIMETAG).err   <= '0';
+  cnx_master_in(c_WB_SLAVE_FMC1_TIMETAG).rty   <= '0';
+  cnx_master_in(c_WB_SLAVE_FMC1_TIMETAG).stall <= '0';
+  cnx_master_in(c_WB_SLAVE_FMC1_TIMETAG).int   <= '0';
+
+  ------------------------------------------------------------------------------
+  -- Front panel LED control
+  --  
+  ------------------------------------------------------------------------------
+  cmp_led_controller : bicolor_led_ctrl
+    generic map(
+      g_NB_COLUMN    => 4,
+      g_NB_LINE      => 2,
+      g_CLK_FREQ     => 125000000,      -- in Hz
+      g_REFRESH_RATE => 250             -- in Hz
+      )
+    port map(
+      rst_n_i => sys_rst_n,
+      clk_i   => sys_clk_125,
+
+      led_intensity_i => "1100100",     -- in %
+
+      led_state_i => led_state,
+
+      column_o   => fp_led_column_o,
+      line_o     => fp_led_line_o,
+      line_oen_o => fp_led_line_oen_o
+      );
+
+  cmp_vme_access_Led : gc_extend_pulse
+    generic map (
+      g_width => 5000000)
+    port map (
+      clk_i      => sys_clk_125,
+      rst_n_i    => sys_rst_n,
+      pulse_i    => cnx_slave_in(c_WB_MASTER_VME).cyc,
+      extended_o => vme_access
+      );
+
+  -- LED 1 : VME access
+  led_state(1 downto 0) <= c_LED_GREEN when vme_access = '1' else c_LED_OFF;
+
+  -- LED 2 : 
+  led_state(3 downto 2) <= c_LED_RED;
+
+  -- LED 3 : 
+  led_state(5 downto 4) <= c_LED_RED_GREEN;
+
+  -- LED 4 : 
+  led_state(7 downto 6) <= '0' & led_pwm;
+
+  led_state(15 downto 8) <= led_state_man(15 downto 8);
+
+  -- LED 5 : 
+  --led_state(9 downto 8) <= c_LED_OFF;
+
+  -- LED 6 : 
+  --led_state(11 downto 10) <= c_LED_OFF;
+
+  -- LED 7 : 
+  --led_state(13 downto 12) <= c_LED_OFF;
+
+  -- LED 8 : 
+  --led_state(15 downto 14) <= c_LED_OFF;
+
+  ------------------------------------------------------------------------------
+  -- FPGA loaded led (heart beat)
+  ------------------------------------------------------------------------------
+  p_led_pwn_update_cnt : process (sys_clk_125)
+  begin
+    if rising_edge(sys_clk_125) then
+      if (sys_rst_n = '0') then
+        led_pwm_update_cnt <= (others => '0');
+        led_pwm_update     <= '0';
+      elsif (led_pwm_update_cnt = to_unsigned(954, 10)) then
+        led_pwm_update_cnt <= (others => '0');
+        led_pwm_update     <= '1';
+      else
+        led_pwm_update_cnt <= led_pwm_update_cnt + 1;
+        led_pwm_update     <= '0';
+      end if;
+    end if;
+  end process p_led_pwn_update_cnt;
+
+  p_led_pwn_val : process (sys_clk_125)
+  begin
+    if rising_edge(sys_clk_125) then
+      if (sys_rst_n = '0') then
+        led_pwm_val      <= (others => '0');
+        led_pwm_val_down <= '0';
+      elsif (led_pwm_update = '1') then
+        if led_pwm_val_down = '1' then
+          if led_pwm_val = X"100" then
+            led_pwm_val_down <= '0';
+          end if;
+          led_pwm_val <= led_pwm_val - 1;
+        else
+          if led_pwm_val = X"1FFFE" then
+            led_pwm_val_down <= '1';
+          end if;
+          led_pwm_val <= led_pwm_val + 1;
+        end if;
+      end if;
+    end if;
+  end process p_led_pwn_val;
+
+  p_led_pwn_cnt : process (sys_clk_125)
+  begin
+    if rising_edge(sys_clk_125) then
+      if (sys_rst_n = '0') then
+        led_pwm_cnt <= (others => '0');
+      else
+        led_pwm_cnt <= led_pwm_cnt + 1;
+      end if;
+    end if;
+  end process p_led_pwn_cnt;
+
+  p_led_pwn : process (sys_clk_125)
+  begin
+    if rising_edge(sys_clk_125) then
+      if (sys_rst_n = '0') then
+        led_pwm <= '0';
+      elsif (led_pwm_cnt = 0) then
+        led_pwm <= '1';
+      elsif (led_pwm_cnt = led_pwm_val) then
+        led_pwm <= '0';
+      end if;
+    end if;
+  end process p_led_pwn;
+
+  -- LED pwm ready to be used
+  -- <= led_pwm;
+
+  ------------------------------------------------------------------------------
+  -- Assign unused outputs
+  ------------------------------------------------------------------------------
+
+
+end rtl;
--- a/hdl/svec/svec_top_fmc_adc_100Ms.ucf
+++ b/hdl/svec/svec_top_fmc_adc_100Ms.ucf
+#===============================================================================
+# The IO Location Constraints
+#===============================================================================
+
+#----------------------------------------
+# VME interface
+#----------------------------------------
+NET "vme_write_n_i" LOC = R1;
+NET "vme_sysreset_n_i" LOC = P4;
+#NET "vme_sysclk_i" LOC = P3;
+NET "vme_retry_oe_o" LOC = R4;
+NET "vme_retry_n_o" LOC = AB2;
+NET "vme_lword_n_b" LOC = M7;
+NET "vme_iackout_n_o" LOC = N3;
+NET "vme_iackin_n_i" LOC = P7;
+NET "vme_iack_n_i" LOC = N1;
+NET "vme_dtack_oe_o" LOC = T1;
+NET "vme_dtack_n_o" LOC = R5;
+NET "vme_ds_n_i[1]" LOC = Y7;
+NET "vme_ds_n_i[0]" LOC = Y6;
+NET "vme_data_oe_n_o" LOC = P1;
+NET "vme_data_dir_o" LOC = P2;
+NET "vme_berr_o" LOC = R3;
+NET "vme_as_n_i" LOC = P6;
+NET "vme_addr_oe_n_o" LOC = N4;
+NET "vme_addr_dir_o" LOC = N5;
+NET "vme_irq_n_o[7]" LOC = R7;
+NET "vme_irq_n_o[6]" LOC = AH2;
+NET "vme_irq_n_o[5]" LOC = AF2;
+NET "vme_irq_n_o[4]" LOC = N9;
+NET "vme_irq_n_o[3]" LOC = N10;
+NET "vme_irq_n_o[2]" LOC = AH4;
+NET "vme_irq_n_o[1]" LOC = AG4;
+NET "vme_ga_i[5]" LOC = M6;
+NET "vme_ga_i[4]" LOC = V9;
+NET "vme_ga_i[3]" LOC = V10;
+NET "vme_ga_i[2]" LOC = AJ1;
+NET "vme_ga_i[1]" LOC = AH1;
+NET "vme_ga_i[0]" LOC = V7;
+NET "vme_data_b[31]" LOC = AK3;
+NET "vme_data_b[30]" LOC = AH3;
+NET "vme_data_b[29]" LOC = T8;
+NET "vme_data_b[28]" LOC = T9;
+NET "vme_data_b[27]" LOC = AK4;
+NET "vme_data_b[26]" LOC = AJ4;
+NET "vme_data_b[25]" LOC = W6;
+NET "vme_data_b[24]" LOC = W7;
+NET "vme_data_b[23]" LOC = AB6;
+NET "vme_data_b[22]" LOC = AB7;
+NET "vme_data_b[21]" LOC = W9;
+NET "vme_data_b[20]" LOC = W10;
+NET "vme_data_b[19]" LOC = AK5;
+NET "vme_data_b[18]" LOC = AH5;
+NET "vme_data_b[17]" LOC = AD6;
+NET "vme_data_b[16]" LOC = AC6;
+NET "vme_data_b[15]" LOC = AA6;
+NET "vme_data_b[14]" LOC = AA7;
+NET "vme_data_b[13]" LOC = T6;
+NET "vme_data_b[12]" LOC = T7;
+NET "vme_data_b[11]" LOC = AG5;
+NET "vme_data_b[10]" LOC = AE5;
+NET "vme_data_b[9]" LOC = Y11;
+NET "vme_data_b[8]" LOC = W11;
+NET "vme_data_b[7]" LOC = AF6;
+NET "vme_data_b[6]" LOC = AE6;
+NET "vme_data_b[5]" LOC = Y8;
+NET "vme_data_b[4]" LOC = Y9;
+NET "vme_data_b[3]" LOC = AE7;
+NET "vme_data_b[2]" LOC = AD7;
+NET "vme_data_b[1]" LOC = AA9;
+NET "vme_data_b[0]" LOC = AA10;
+NET "vme_am_i[5]" LOC = V8;
+NET "vme_am_i[4]" LOC = AG3;
+NET "vme_am_i[3]" LOC = AF3;
+NET "vme_am_i[2]" LOC = AF4;
+NET "vme_am_i[1]" LOC = AE4;
+NET "vme_am_i[0]" LOC = AK2;
+NET "vme_addr_b[31]" LOC = T2;
+NET "vme_addr_b[30]" LOC = T3;
+NET "vme_addr_b[29]" LOC = T4;
+NET "vme_addr_b[28]" LOC = U1;
+NET "vme_addr_b[27]" LOC = U3;
+NET "vme_addr_b[26]" LOC = U4;
+NET "vme_addr_b[25]" LOC = U5;
+NET "vme_addr_b[24]" LOC = V1;
+NET "vme_addr_b[23]" LOC = V2;
+NET "vme_addr_b[22]" LOC = W1;
+NET "vme_addr_b[21]" LOC = W3;
+NET "vme_addr_b[20]" LOC = AA4;
+NET "vme_addr_b[19]" LOC = AA5;
+NET "vme_addr_b[18]" LOC = Y1;
+NET "vme_addr_b[17]" LOC = Y2;
+NET "vme_addr_b[16]" LOC = Y3;
+NET "vme_addr_b[15]" LOC = Y4;
+NET "vme_addr_b[14]" LOC = AC1;
+NET "vme_addr_b[13]" LOC = AC3;
+NET "vme_addr_b[12]" LOC = AD1;
+NET "vme_addr_b[11]" LOC = AD2;
+NET "vme_addr_b[10]" LOC = AB3;
+NET "vme_addr_b[9]" LOC = AB4;
+NET "vme_addr_b[8]" LOC = AD3;
+NET "vme_addr_b[7]" LOC = AD4;
+NET "vme_addr_b[6]" LOC = AC4;
+NET "vme_addr_b[5]" LOC = AC5;
+NET "vme_addr_b[4]" LOC = N7;
+NET "vme_addr_b[3]" LOC = N8;
+NET "vme_addr_b[2]" LOC = AE1;
+NET "vme_addr_b[1]" LOC = AE3;
+NET "vme_write_n_i" IOSTANDARD = "LVCMOS33";
+NET "vme_sysreset_n_i" IOSTANDARD = "LVCMOS33";
+#NET "vme_sysclk_i" IOSTANDARD = "LVCMOS33";
+NET "vme_retry_oe_o" IOSTANDARD = "LVCMOS33";
+NET "vme_retry_n_o" IOSTANDARD = "LVCMOS33";
+NET "vme_lword_n_b" IOSTANDARD = "LVCMOS33";
+NET "vme_iackout_n_o" IOSTANDARD = "LVCMOS33";
+NET "vme_iackin_n_i" IOSTANDARD = "LVCMOS33";
+NET "vme_iack_n_i" IOSTANDARD = "LVCMOS33";
+NET "vme_dtack_oe_o" IOSTANDARD = "LVCMOS33";
+NET "vme_dtack_n_o" IOSTANDARD = "LVCMOS33";
+NET "vme_ds_n_i[1]" IOSTANDARD = "LVCMOS33";
+NET "vme_ds_n_i[0]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_oe_n_o" IOSTANDARD = "LVCMOS33";
+NET "vme_data_dir_o" IOSTANDARD = "LVCMOS33";
+NET "vme_berr_o" IOSTANDARD = "LVCMOS33";
+NET "vme_as_n_i" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_oe_n_o" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_dir_o" IOSTANDARD = "LVCMOS33";
+NET "vme_irq_n_o[7]" IOSTANDARD = "LVCMOS33";
+NET "vme_irq_n_o[6]" IOSTANDARD = "LVCMOS33";
+NET "vme_irq_n_o[5]" IOSTANDARD = "LVCMOS33";
+NET "vme_irq_n_o[4]" IOSTANDARD = "LVCMOS33";
+NET "vme_irq_n_o[3]" IOSTANDARD = "LVCMOS33";
+NET "vme_irq_n_o[2]" IOSTANDARD = "LVCMOS33";
+NET "vme_irq_n_o[1]" IOSTANDARD = "LVCMOS33";
+NET "vme_ga_i[5]" IOSTANDARD = "LVCMOS33";
+NET "vme_ga_i[4]" IOSTANDARD = "LVCMOS33";
+NET "vme_ga_i[3]" IOSTANDARD = "LVCMOS33";
+NET "vme_ga_i[2]" IOSTANDARD = "LVCMOS33";
+NET "vme_ga_i[1]" IOSTANDARD = "LVCMOS33";
+NET "vme_ga_i[0]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[31]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[30]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[29]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[28]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[27]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[26]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[25]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[24]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[23]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[22]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[21]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[20]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[19]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[18]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[17]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[16]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[15]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[14]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[13]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[12]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[11]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[10]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[9]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[8]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[7]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[6]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[5]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[4]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[3]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[2]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[1]" IOSTANDARD = "LVCMOS33";
+NET "vme_data_b[0]" IOSTANDARD = "LVCMOS33";
+NET "vme_am_i[5]" IOSTANDARD = "LVCMOS33";
+NET "vme_am_i[4]" IOSTANDARD = "LVCMOS33";
+NET "vme_am_i[3]" IOSTANDARD = "LVCMOS33";
+NET "vme_am_i[2]" IOSTANDARD = "LVCMOS33";
+NET "vme_am_i[1]" IOSTANDARD = "LVCMOS33";
+NET "vme_am_i[0]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[31]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[30]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[29]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[28]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[27]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[26]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[25]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[24]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[23]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[22]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[21]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[20]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[19]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[18]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[17]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[16]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[15]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[14]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[13]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[12]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[11]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[10]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[9]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[8]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[7]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[6]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[5]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[4]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[3]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[2]" IOSTANDARD = "LVCMOS33";
+NET "vme_addr_b[1]" IOSTANDARD = "LVCMOS33";
+
+#----------------------------------------
+# DDR0 (bank 4)
+#----------------------------------------
+NET "ddr0_zio_b" LOC = J6;
+NET "ddr0_rzq_b" LOC = L7;
+NET "ddr0_we_n_o" LOC = F4;
+NET "ddr0_udqs_p_b" LOC = K2;
+NET "ddr0_udqs_n_b" LOC = K1;
+NET "ddr0_udm_o" LOC = K4;
+NET "ddr0_reset_n_o" LOC = G5;
+NET "ddr0_ras_n_o" LOC = C1;
+NET "ddr0_odt_o" LOC = E4;
+NET "ddr0_ldqs_p_b" LOC = J5;
+NET "ddr0_ldqs_n_b" LOC = J4;
+NET "ddr0_ldm_o" LOC = K3;
+NET "ddr0_cke_o" LOC = C4;
+NET "ddr0_ck_p_o" LOC = E3;
+NET "ddr0_ck_n_o" LOC = E1;
+NET "ddr0_cas_n_o" LOC = B1;
+NET "ddr0_dq_b[15]" LOC = M1;
+NET "ddr0_dq_b[14]" LOC = M2;
+NET "ddr0_dq_b[13]" LOC = L1;
+NET "ddr0_dq_b[12]" LOC = L3;
+NET "ddr0_dq_b[11]" LOC = L4;
+NET "ddr0_dq_b[10]" LOC = L5;
+NET "ddr0_dq_b[9]" LOC = M3;
+NET "ddr0_dq_b[8]" LOC = M4;
+NET "ddr0_dq_b[7]" LOC = H1;
+NET "ddr0_dq_b[6]" LOC = H2;
+NET "ddr0_dq_b[5]" LOC = G1;
+NET "ddr0_dq_b[4]" LOC = G3;
+NET "ddr0_dq_b[3]" LOC = J1;
+NET "ddr0_dq_b[2]" LOC = J3;
+NET "ddr0_dq_b[1]" LOC = H3;
+NET "ddr0_dq_b[0]" LOC = H4;
+NET "ddr0_ba_o[2]" LOC = F3;
+NET "ddr0_ba_o[1]" LOC = D1;
+NET "ddr0_ba_o[0]" LOC = D2;
+#NET "ddr0_a_o[14]" LOC = A5;
+NET "ddr0_a_o[13]" LOC = B5;
+NET "ddr0_a_o[12]" LOC = A4;
+NET "ddr0_a_o[11]" LOC = G4;
+NET "ddr0_a_o[10]" LOC = D5;
+NET "ddr0_a_o[9]" LOC = A2;
+NET "ddr0_a_o[8]" LOC = B2;
+NET "ddr0_a_o[7]" LOC = B3;
+NET "ddr0_a_o[6]" LOC = F1;
+NET "ddr0_a_o[5]" LOC = F2;
+NET "ddr0_a_o[4]" LOC = C5;
+NET "ddr0_a_o[3]" LOC = E5;
+NET "ddr0_a_o[2]" LOC = A3;
+NET "ddr0_a_o[1]" LOC = D3;
+NET "ddr0_a_o[0]" LOC = D4;
+NET "ddr0_zio_b" IOSTANDARD = "SSTL15_II";
+NET "ddr0_rzq_b" IOSTANDARD = "SSTL15_II";
+NET "ddr0_we_n_o" IOSTANDARD = "SSTL15_II";
+NET "ddr0_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
+NET "ddr0_udqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
+NET "ddr0_udm_o" IOSTANDARD = "SSTL15_II";
+NET "ddr0_reset_n_o" IOSTANDARD = "SSTL15_II";
+NET "ddr0_ras_n_o" IOSTANDARD = "SSTL15_II";
+NET "ddr0_odt_o" IOSTANDARD = "SSTL15_II";
+NET "ddr0_ldqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
+NET "ddr0_ldqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
+NET "ddr0_ldm_o" IOSTANDARD = "SSTL15_II";
+NET "ddr0_cke_o" IOSTANDARD = "SSTL15_II";
+NET "ddr0_ck_p_o" IOSTANDARD = "DIFF_SSTL15_II";
+NET "ddr0_ck_n_o" IOSTANDARD = "DIFF_SSTL15_II";
+NET "ddr0_cas_n_o" IOSTANDARD = "SSTL15_II";
+NET "ddr0_dq_b[15]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_dq_b[14]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_dq_b[13]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_dq_b[12]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_dq_b[11]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_dq_b[10]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_dq_b[9]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_dq_b[8]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_dq_b[7]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_dq_b[6]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_dq_b[5]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_dq_b[4]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_dq_b[3]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_dq_b[2]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_dq_b[1]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_dq_b[0]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_ba_o[2]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_ba_o[1]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_ba_o[0]" IOSTANDARD = "SSTL15_II";
+#NET "ddr0_a_o[14]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_a_o[13]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_a_o[12]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_a_o[11]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_a_o[10]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_a_o[9]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_a_o[8]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_a_o[7]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_a_o[6]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_a_o[5]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_a_o[4]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_a_o[3]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_a_o[2]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_a_o[1]" IOSTANDARD = "SSTL15_II";
+NET "ddr0_a_o[0]" IOSTANDARD = "SSTL15_II";
+
+#----------------------------------------
+# DDR1 (bank 5)
+#----------------------------------------
+NET "ddr1_zio_b" LOC = L24;
+NET "ddr1_rzq_b" LOC = G25;
+NET "ddr1_we_n_o" LOC = E26;
+NET "ddr1_udqs_p_b" LOC = K28;
+NET "ddr1_udqs_n_b" LOC = K30;
+NET "ddr1_udm_o" LOC = J27;
+NET "ddr1_reset_n_o" LOC = C26;
+NET "ddr1_ras_n_o" LOC = K26;
+NET "ddr1_odt_o" LOC = E30;
+NET "ddr1_ldqs_p_b" LOC = J29;
+NET "ddr1_ldqs_n_b" LOC = J30;
+NET "ddr1_ldm_o" LOC = J28;
+NET "ddr1_cke_o" LOC = B29;
+NET "ddr1_ck_p_o" LOC = E27;
+NET "ddr1_ck_n_o" LOC = E28;
+NET "ddr1_cas_n_o" LOC = K27;
+NET "ddr1_dq_b[15]" LOC = M30;
+NET "ddr1_dq_b[14]" LOC = M28;
+NET "ddr1_dq_b[13]" LOC = M27;
+NET "ddr1_dq_b[12]" LOC = M26;
+NET "ddr1_dq_b[11]" LOC = L30;
+NET "ddr1_dq_b[10]" LOC = L29;
+NET "ddr1_dq_b[9]" LOC = L28;
+NET "ddr1_dq_b[8]" LOC = L27;
+NET "ddr1_dq_b[7]" LOC = F30;
+NET "ddr1_dq_b[6]" LOC = F28;
+NET "ddr1_dq_b[5]" LOC = G28;
+NET "ddr1_dq_b[4]" LOC = G27;
+NET "ddr1_dq_b[3]" LOC = G30;
+NET "ddr1_dq_b[2]" LOC = G29;
+NET "ddr1_dq_b[1]" LOC = H30;
+NET "ddr1_dq_b[0]" LOC = H28;
+NET "ddr1_ba_o[2]" LOC = D26;
+NET "ddr1_ba_o[1]" LOC = C27;
+NET "ddr1_ba_o[0]" LOC = D27;
+#NET "ddr1_a_o[14]" LOC = A29;
+NET "ddr1_a_o[13]" LOC = A28;
+NET "ddr1_a_o[12]" LOC = B30;
+NET "ddr1_a_o[11]" LOC = A26;
+NET "ddr1_a_o[10]" LOC = F26;
+NET "ddr1_a_o[9]" LOC = A27;
+NET "ddr1_a_o[8]" LOC = B27;
+NET "ddr1_a_o[7]" LOC = C29;
+NET "ddr1_a_o[6]" LOC = H27;
+NET "ddr1_a_o[5]" LOC = H26;
+NET "ddr1_a_o[4]" LOC = F27;
+NET "ddr1_a_o[3]" LOC = E29;
+NET "ddr1_a_o[2]" LOC = C30;
+NET "ddr1_a_o[1]" LOC = D30;
+NET "ddr1_a_o[0]" LOC = D28;
+NET "ddr1_zio_b" IOSTANDARD = "SSTL15_II";
+NET "ddr1_rzq_b" IOSTANDARD = "SSTL15_II";
+NET "ddr1_we_n_o" IOSTANDARD = "SSTL15_II";
+NET "ddr1_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
+NET "ddr1_udqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
+NET "ddr1_udm_o" IOSTANDARD = "SSTL15_II";
+NET "ddr1_reset_n_o" IOSTANDARD = "SSTL15_II";
+NET "ddr1_ras_n_o" IOSTANDARD = "SSTL15_II";
+NET "ddr1_odt_o" IOSTANDARD = "SSTL15_II";
+NET "ddr1_ldqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
+NET "ddr1_ldqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
+NET "ddr1_ldm_o" IOSTANDARD = "SSTL15_II";
+NET "ddr1_cke_o" IOSTANDARD = "SSTL15_II";
+NET "ddr1_ck_p_o" IOSTANDARD = "DIFF_SSTL15_II";
+NET "ddr1_ck_n_o" IOSTANDARD = "DIFF_SSTL15_II";
+NET "ddr1_cas_n_o" IOSTANDARD = "SSTL15_II";
+NET "ddr1_dq_b[15]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_dq_b[14]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_dq_b[13]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_dq_b[12]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_dq_b[11]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_dq_b[10]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_dq_b[9]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_dq_b[8]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_dq_b[7]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_dq_b[6]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_dq_b[5]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_dq_b[4]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_dq_b[3]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_dq_b[2]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_dq_b[1]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_dq_b[0]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_ba_o[2]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_ba_o[1]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_ba_o[0]" IOSTANDARD = "SSTL15_II";
+#NET "ddr1_a_o[14]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_a_o[13]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_a_o[12]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_a_o[11]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_a_o[10]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_a_o[9]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_a_o[8]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_a_o[7]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_a_o[6]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_a_o[5]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_a_o[4]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_a_o[3]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_a_o[2]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_a_o[1]" IOSTANDARD = "SSTL15_II";
+NET "ddr1_a_o[0]" IOSTANDARD = "SSTL15_II";
+
+#----------------------------------------
+# Clock and reset inputs
+#----------------------------------------
+NET "rst_n_i" LOC = AD28;
+NET "rst_n_i" IOSTANDARD = "LVCMOS33";
+
+NET "clk_20m_vcxo_i" LOC = V26;
+#NET "clk_125m_pllref_n_i" LOC = AB30;
+#NET "clk_125m_pllref_p_i" LOC = AB28;
+NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS33";
+#NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
+#NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
+
+#----------------------------------------
+# SFP slot
+#----------------------------------------
+#NET "sfp_txp_o" LOC = B23;
+#NET "sfp_txn_o" LOC = A23;
+#NET "sfp_rxp_i" LOC = D22;
+#NET "sfp_rxn_i" LOC = C22;
+#NET "clk_125m_gtp_p_i" LOC = B19;
+#NET "clk_125m_gtp_n_i" LOC = A19;
+
+#NET "sfp_los_i" LOC = W25;
+#NET "sfp_mod_def0_b" LOC = Y26;
+#NET "sfp_mod_def1_b" LOC = Y27;
+#NET "sfp_mod_def2_b" LOC = AA24;
+#NET "sfp_rate_select_o" LOC = W24;
+#NET "sfp_tx_disable_o" LOC = AA25;
+#NET "sfp_tx_fault_i" LOC = AA27;
+#NET "sfp_los_i" IOSTANDARD = "LVCMOS33";
+#NET "sfp_mod_def0_b" IOSTANDARD = "LVCMOS33";
+#NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS33";
+#NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS33";
+#NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
+#NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
+#NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
+
+#----------------------------------------
+# Clock controls
+#----------------------------------------
+#NET "pll20dac_din_o" LOC = U28;
+#NET "pll20dac_sclk_o" LOC = AA28;
+#NET "pll20dac_sync_n_o" LOC = N28;
+#NET "pll25dac_din_o" LOC = P25;
+#NET "pll25dac_sclk_o" LOC = N27;
+#NET "pll25dac_sync_n_o" LOC = P26;
+#NET "pll20dac_din_o" IOSTANDARD = "LVCMOS33";
+#NET "pll20dac_sclk_o" IOSTANDARD = "LVCMOS33";
+#NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS33";
+#NET "pll25dac_din_o" IOSTANDARD = "LVCMOS33";
+#NET "pll25dac_sclk_o" IOSTANDARD = "LVCMOS33";
+#NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS33";
+
+#----------------------------------------
+# UART
+#----------------------------------------
+#NET "uart_txd_o" LOC = U27;
+#NET "uart_rxd_i" LOC = U25;
+#NET "uart_txd_o" IOSTANDARD = "LVCMOS33";
+#NET "uart_rxd_i" IOSTANDARD = "LVCMOS33";
+
+#----------------------------------------
+# 1-wire thermoeter + unique ID
+#----------------------------------------
+NET "carrier_one_wire_b" LOC = AC30;
+NET "carrier_one_wire_b" IOSTANDARD = "LVCMOS33";
+
+#----------------------------------------
+# Front panel LEDs
+#----------------------------------------
+NET "fp_led_line_oen_o[0]" LOC = AD26;
+NET "fp_led_line_oen_o[1]" LOC = AD27;
+NET "fp_led_line_o[0]" LOC = AC27;
+NET "fp_led_line_o[1]" LOC = AC28;
+NET "fp_led_column_o[0]" LOC = AE30;
+NET "fp_led_column_o[1]" LOC = AE27;
+NET "fp_led_column_o[2]" LOC = AE28;
+NET "fp_led_column_o[3]" LOC = AF28;
+NET "fp_led_line_oen_o[0]" IOSTANDARD="LVCMOS33";
+NET "fp_led_line_oen_o[1]" IOSTANDARD="LVCMOS33";
+NET "fp_led_line_o[0]" IOSTANDARD="LVCMOS33";
+NET "fp_led_line_o[1]" IOSTANDARD="LVCMOS33";
+NET "fp_led_column_o[0]" IOSTANDARD="LVCMOS33";
+NET "fp_led_column_o[1]" IOSTANDARD="LVCMOS33";
+NET "fp_led_column_o[2]" IOSTANDARD="LVCMOS33";
+NET "fp_led_column_o[3]" IOSTANDARD="LVCMOS33";
+
+#----------------------------------------
+# Front panel IOs
+#----------------------------------------
+#NET "fp_gpio_b[1]" LOC = R30;
+#NET "fp_gpio_b[2]" LOC = T28;
+#NET "fp_gpio_b[3]" LOC = U29;
+#NET "fp_gpio_b[4]" LOC = V27;
+#NET "fpgpio1_a2b_o" LOC = R29;
+#NET "fpgpio2_a2b_o" LOC = T30;
+#NET "fpgpio34_a2b_o" LOC = V28;
+#NET "term_en_o[1]" LOC = AB1;
+#NET "term_en_o[2]" LOC = W5;
+#NET "term_en_o[3]" LOC = W4;
+#NET "term_en_o[4]" LOC = V4;
+#NET "fp_gpio_b[1]" IOSTANDARD = "LVCMOS33";
+#NET "fp_gpio_b[2]" IOSTANDARD = "LVCMOS33";
+#NET "fp_gpio_b[3]" IOSTANDARD = "LVCMOS33";
+#NET "fp_gpio_b[4]" IOSTANDARD = "LVCMOS33";
+#NET "fpgpio1_a2b_o" IOSTANDARD = "LVCMOS33";
+#NET "fpgpio2_a2b_o" IOSTANDARD = "LVCMOS33";
+#NET "fpgpio34_a2b_o" IOSTANDARD = "LVCMOS33";
+#NET "term_en_o[1]" IOSTANDARD = "LVCMOS33";
+#NET "term_en_o[2]" IOSTANDARD = "LVCMOS33";
+#NET "term_en_o[3]" IOSTANDARD = "LVCMOS33";
+#NET "term_en_o[4]" IOSTANDARD = "LVCMOS33";
+
+#----------------------------------------
+# Debug LEDs
+#----------------------------------------
+#NET "dbg_led_n_o[4]" LOC = U7;
+#NET "dbg_led_n_o[3]" LOC = AG1;
+#NET "dbg_led_n_o[2]" LOC = AF1;
+#NET "dbg_led_n_o[1]" LOC = R6;
+#NET "dbg_led_n_o[4]" IOSTANDARD = "LVCMOS33";
+#NET "dbg_led_n_o[3]" IOSTANDARD = "LVCMOS33";
+#NET "dbg_led_n_o[2]" IOSTANDARD = "LVCMOS33";
+#NET "dbg_led_n_o[1]" IOSTANDARD = "LVCMOS33";
+
+#----------------------------------------
+# Switches and button
+#----------------------------------------
+#NET "pushbutton_i" LOC = P24;
+#NET "noga_i[0]" LOC = AE26;
+#NET "noga_i[1]" LOC = P23;
+#NET "noga_i[2]" LOC = Y24;
+#NET "noga_i[3]" LOC = Y23;
+#NET "noga_i[4]" LOC = V23;
+#NET "switch_i[0]" LOC = W22;
+#NET "switch_i[1]" LOC = W21;
+#NET "usega_i" LOC = Y22;
+#NET "pushbutton_i" IOSTANDARD = "LVCMOS33";
+#NET "noga_i[0]" IOSTANDARD = "LVCMOS33";
+#NET "noga_i[1]" IOSTANDARD = "LVCMOS33";
+#NET "noga_i[2]" IOSTANDARD = "LVCMOS33";
+#NET "noga_i[3]" IOSTANDARD = "LVCMOS33";
+#NET "noga_i[4]" IOSTANDARD = "LVCMOS33";
+#NET "switch_i[0]" IOSTANDARD = "LVCMOS33";
+#NET "switch_i[1]" IOSTANDARD = "LVCMOS33";
+#NET "usega_i" IOSTANDARD = "LVCMOS33";
+
+#----------------------------------------
+# Inter-FPGA lines
+#----------------------------------------
+#NET "rsvd_b[0]" LOC = AG26;
+#NET "rsvd_b[1]" LOC = AH26;
+#NET "rsvd_b[2]" LOC = AG27;
+#NET "rsvd_b[3]" LOC = AH27;
+#NET "rsvd_b[4]" LOC = AK27;
+#NET "rsvd_b[5]" LOC = AG28;
+#NET "rsvd_b[6]" LOC = AJ28;
+#NET "rsvd_b[7]" LOC = AK28;
+#NET "rsvd_b[0]" IOSTANDARD = "LVCMOS33";
+#NET "rsvd_b[1]" IOSTANDARD = "LVCMOS33";
+#NET "rsvd_b[2]" IOSTANDARD = "LVCMOS33";
+#NET "rsvd_b[3]" IOSTANDARD = "LVCMOS33";
+#NET "rsvd_b[4]" IOSTANDARD = "LVCMOS33";
+#NET "rsvd_b[5]" IOSTANDARD = "LVCMOS33";
+#NET "rsvd_b[6]" IOSTANDARD = "LVCMOS33";
+#NET "rsvd_b[7]" IOSTANDARD = "LVCMOS33";
+
+#----------------------------------------
+# PCB revision
+#----------------------------------------
+NET "pcbrev_i[4]" LOC = AF17;
+NET "pcbrev_i[3]" LOC = AE17;
+NET "pcbrev_i[2]" LOC = AD18;
+NET "pcbrev_i[1]" LOC = AE20;
+NET "pcbrev_i[0]" LOC = AD20;
+NET "pcbrev_i[4]" IOSTANDARD = "LVCMOS25";
+NET "pcbrev_i[3]" IOSTANDARD = "LVCMOS25";
+NET "pcbrev_i[2]" IOSTANDARD = "LVCMOS25";
+NET "pcbrev_i[1]" IOSTANDARD = "LVCMOS25";
+NET "pcbrev_i[0]" IOSTANDARD = "LVCMOS25";
+
+#----------------------------------------
+# Carrier I2C EEPROM
+#----------------------------------------
+NET "carrier_scl_b" LOC = AC29;
+NET "carrier_sda_b" LOC = AA30;
+NET "carrier_scl_b" IOSTANDARD = "LVCMOS33";
+NET "carrier_sda_b" IOSTANDARD = "LVCMOS33";
+
+#----------------------------------------
+# FMC slots management
+#----------------------------------------
+NET "fmc0_prsnt_m2c_n_i" LOC = N30;
+NET "fmc0_scl_b" LOC = P28;
+NET "fmc0_sda_b" LOC = P30;
+NET "fmc0_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS33";
+NET "fmc0_scl_b" IOSTANDARD = "LVCMOS33";
+NET "fmc0_sda_b" IOSTANDARD = "LVCMOS33";
+
+NET "fmc1_prsnt_m2c_n_i" LOC = AE29;
+NET "fmc1_scl_b" LOC = W29;
+NET "fmc1_sda_b" LOC = V30;
+NET "fmc1_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS33";
+NET "fmc1_scl_b" IOSTANDARD = "LVCMOS33";
+NET "fmc1_sda_b" IOSTANDARD = "LVCMOS33";
+
+#----------------------------------------
+# FMC slots
+#----------------------------------------
+# <ucfgen_start>
+
+# This section has bee generated automatically by ucfgen.py. Do not hand-modify if not really necessary.
+# ucfgen pin assignments for mezzanine fmc-adc-v5 slot 0
+NET "adc0_ext_trigger_n_i" LOC = "A15";
+NET "adc0_ext_trigger_n_i" IOSTANDARD = "LVDS_25";
+NET "adc0_ext_trigger_p_i" LOC = "B15";
+NET "adc0_ext_trigger_p_i" IOSTANDARD = "LVDS_25";
+NET "adc0_dco_n_i" LOC = "A16";
+NET "adc0_dco_n_i" IOSTANDARD = "LVDS_25";
+NET "adc0_dco_p_i" LOC = "C16";
+NET "adc0_dco_p_i" IOSTANDARD = "LVDS_25";
+NET "adc0_fr_n_i" LOC = "G21";
+NET "adc0_fr_n_i" IOSTANDARD = "LVDS_25";
+NET "adc0_fr_p_i" LOC = "H21";
+NET "adc0_fr_p_i" IOSTANDARD = "LVDS_25";
+NET "adc0_outa_n_i[0]" LOC = "E17";
+NET "adc0_outa_n_i[0]" IOSTANDARD = "LVDS_25";
+NET "adc0_outa_p_i[0]" LOC = "F17";
+NET "adc0_outa_p_i[0]" IOSTANDARD = "LVDS_25";
+NET "adc0_outb_n_i[0]" LOC = "G16";
+NET "adc0_outb_n_i[0]" IOSTANDARD = "LVDS_25";
+NET "adc0_outb_p_i[0]" LOC = "H16";
+NET "adc0_outb_p_i[0]" IOSTANDARD = "LVDS_25";
+NET "adc0_outa_n_i[1]" LOC = "E19";
+NET "adc0_outa_n_i[1]" IOSTANDARD = "LVDS_25";
+NET "adc0_outa_p_i[1]" LOC = "F19";
+NET "adc0_outa_p_i[1]" IOSTANDARD = "LVDS_25";
+NET "adc0_outb_n_i[1]" LOC = "F18";
+NET "adc0_outb_n_i[1]" IOSTANDARD = "LVDS_25";
+NET "adc0_outb_p_i[1]" LOC = "G18";
+NET "adc0_outb_p_i[1]" IOSTANDARD = "LVDS_25";
+NET "adc0_outa_n_i[2]" LOC = "K21";
+NET "adc0_outa_n_i[2]" IOSTANDARD = "LVDS_25";
+NET "adc0_outa_p_i[2]" LOC = "L21";
+NET "adc0_outa_p_i[2]" IOSTANDARD = "LVDS_25";
+NET "adc0_outb_n_i[2]" LOC = "L20";
+NET "adc0_outb_n_i[2]" IOSTANDARD = "LVDS_25";
+NET "adc0_outb_p_i[2]" LOC = "M20";
+NET "adc0_outb_p_i[2]" IOSTANDARD = "LVDS_25";
+NET "adc0_outa_n_i[3]" LOC = "F22";
+NET "adc0_outa_n_i[3]" IOSTANDARD = "LVDS_25";
+NET "adc0_outa_p_i[3]" LOC = "G22";
+NET "adc0_outa_p_i[3]" IOSTANDARD = "LVDS_25";
+NET "adc0_outb_n_i[3]" LOC = "L19";
+NET "adc0_outb_n_i[3]" IOSTANDARD = "LVDS_25";
+NET "adc0_outb_p_i[3]" LOC = "M19";
+NET "adc0_outb_p_i[3]" IOSTANDARD = "LVDS_25";
+NET "adc0_spi_din_i" LOC = "F11";
+NET "adc0_spi_din_i" IOSTANDARD = "LVCMOS25";
+NET "adc0_spi_dout_o" LOC = "K11";
+NET "adc0_spi_dout_o" IOSTANDARD = "LVCMOS25";
+NET "adc0_spi_sck_o" LOC = "L11";
+NET "adc0_spi_sck_o" IOSTANDARD = "LVCMOS25";
+NET "adc0_spi_cs_adc_n_o" LOC = "J13";
+NET "adc0_spi_cs_adc_n_o" IOSTANDARD = "LVCMOS25";
+NET "adc0_spi_cs_dac1_n_o" LOC = "H11";
+NET "adc0_spi_cs_dac1_n_o" IOSTANDARD = "LVCMOS25";
+NET "adc0_spi_cs_dac2_n_o" LOC = "G11";
+NET "adc0_spi_cs_dac2_n_o" IOSTANDARD = "LVCMOS25";
+NET "adc0_spi_cs_dac3_n_o" LOC = "J12";
+NET "adc0_spi_cs_dac3_n_o" IOSTANDARD = "LVCMOS25";
+NET "adc0_spi_cs_dac4_n_o" LOC = "H12";
+NET "adc0_spi_cs_dac4_n_o" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_dac_clr_n_o" LOC = "H13";
+NET "adc0_gpio_dac_clr_n_o" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_led_acq_o" LOC = "K12";
+NET "adc0_gpio_led_acq_o" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_led_trig_o" LOC = "L12";
+NET "adc0_gpio_led_trig_o" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch1_o[0]" LOC = "L14";
+NET "adc0_gpio_ssr_ch1_o[0]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch1_o[1]" LOC = "K14";
+NET "adc0_gpio_ssr_ch1_o[1]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch1_o[2]" LOC = "L13";
+NET "adc0_gpio_ssr_ch1_o[2]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch1_o[3]" LOC = "E11";
+NET "adc0_gpio_ssr_ch1_o[3]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch1_o[4]" LOC = "G10";
+NET "adc0_gpio_ssr_ch1_o[4]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch1_o[5]" LOC = "F10";
+NET "adc0_gpio_ssr_ch1_o[5]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch1_o[6]" LOC = "F9";
+NET "adc0_gpio_ssr_ch1_o[6]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch2_o[0]" LOC = "F15";
+NET "adc0_gpio_ssr_ch2_o[0]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch2_o[1]" LOC = "F14";
+NET "adc0_gpio_ssr_ch2_o[1]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch2_o[2]" LOC = "F13";
+NET "adc0_gpio_ssr_ch2_o[2]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch2_o[3]" LOC = "E13";
+NET "adc0_gpio_ssr_ch2_o[3]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch2_o[4]" LOC = "G12";
+NET "adc0_gpio_ssr_ch2_o[4]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch2_o[5]" LOC = "M13";
+NET "adc0_gpio_ssr_ch2_o[5]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch2_o[6]" LOC = "F12";
+NET "adc0_gpio_ssr_ch2_o[6]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch3_o[0]" LOC = "F23";
+NET "adc0_gpio_ssr_ch3_o[0]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch3_o[1]" LOC = "E23";
+NET "adc0_gpio_ssr_ch3_o[1]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch3_o[2]" LOC = "F21";
+NET "adc0_gpio_ssr_ch3_o[2]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch3_o[3]" LOC = "E21";
+NET "adc0_gpio_ssr_ch3_o[3]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch3_o[4]" LOC = "G20";
+NET "adc0_gpio_ssr_ch3_o[4]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch3_o[5]" LOC = "F20";
+NET "adc0_gpio_ssr_ch3_o[5]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch3_o[6]" LOC = "E15";
+NET "adc0_gpio_ssr_ch3_o[6]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch4_o[0]" LOC = "J22";
+NET "adc0_gpio_ssr_ch4_o[0]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch4_o[1]" LOC = "H22";
+NET "adc0_gpio_ssr_ch4_o[1]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch4_o[2]" LOC = "E25";
+NET "adc0_gpio_ssr_ch4_o[2]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch4_o[3]" LOC = "D25";
+NET "adc0_gpio_ssr_ch4_o[3]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch4_o[4]" LOC = "D24";
+NET "adc0_gpio_ssr_ch4_o[4]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch4_o[5]" LOC = "B25";
+NET "adc0_gpio_ssr_ch4_o[5]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_ssr_ch4_o[6]" LOC = "C24";
+NET "adc0_gpio_ssr_ch4_o[6]" IOSTANDARD = "LVCMOS25";
+NET "adc0_gpio_si570_oe_o" LOC = "A25";
+NET "adc0_gpio_si570_oe_o" IOSTANDARD = "LVCMOS25";
+NET "adc0_si570_scl_b" LOC = "H14";
+NET "adc0_si570_scl_b" IOSTANDARD = "LVCMOS25";
+NET "adc0_si570_sda_b" LOC = "J14";
+NET "adc0_si570_sda_b" IOSTANDARD = "LVCMOS25";
+NET "adc0_one_wire_b" LOC = "E9";
+NET "adc0_one_wire_b" IOSTANDARD = "LVCMOS25";
+# ucfgen pin assignments for mezzanine fmc-adc-v5 slot 1
+NET "adc1_ext_trigger_n_i" LOC = "AD16";
+NET "adc1_ext_trigger_n_i" IOSTANDARD = "LVDS_25";
+NET "adc1_ext_trigger_p_i" LOC = "AC16";
+NET "adc1_ext_trigger_p_i" IOSTANDARD = "LVDS_25";
+NET "adc1_dco_n_i" LOC = "AK17";
+NET "adc1_dco_n_i" IOSTANDARD = "LVDS_25";
+NET "adc1_dco_p_i" LOC = "AJ17";
+NET "adc1_dco_p_i" IOSTANDARD = "LVDS_25";
+NET "adc1_fr_n_i" LOC = "AH8";
+NET "adc1_fr_n_i" IOSTANDARD = "LVDS_25";
+NET "adc1_fr_p_i" LOC = "AG8";
+NET "adc1_fr_p_i" IOSTANDARD = "LVDS_25";
+NET "adc1_outa_n_i[0]" LOC = "AA15";
+NET "adc1_outa_n_i[0]" IOSTANDARD = "LVDS_25";
+NET "adc1_outa_p_i[0]" LOC = "Y15";
+NET "adc1_outa_p_i[0]" IOSTANDARD = "LVDS_25";
+NET "adc1_outb_n_i[0]" LOC = "AA17";
+NET "adc1_outb_n_i[0]" IOSTANDARD = "LVDS_25";
+NET "adc1_outb_p_i[0]" LOC = "Y17";
+NET "adc1_outb_p_i[0]" IOSTANDARD = "LVDS_25";
+NET "adc1_outa_n_i[1]" LOC = "AC14";
+NET "adc1_outa_n_i[1]" IOSTANDARD = "LVDS_25";
+NET "adc1_outa_p_i[1]" LOC = "AB14";
+NET "adc1_outa_p_i[1]" IOSTANDARD = "LVDS_25";
+NET "adc1_outb_n_i[1]" LOC = "AD15";
+NET "adc1_outb_n_i[1]" IOSTANDARD = "LVDS_25";
+NET "adc1_outb_p_i[1]" LOC = "AC15";
+NET "adc1_outb_p_i[1]" IOSTANDARD = "LVDS_25";
+NET "adc1_outa_n_i[2]" LOC = "AA14";
+NET "adc1_outa_n_i[2]" IOSTANDARD = "LVDS_25";
+NET "adc1_outa_p_i[2]" LOC = "Y14";
+NET "adc1_outa_p_i[2]" IOSTANDARD = "LVDS_25";
+NET "adc1_outb_n_i[2]" LOC = "Y13";
+NET "adc1_outb_n_i[2]" IOSTANDARD = "LVDS_25";
+NET "adc1_outb_p_i[2]" LOC = "W14";
+NET "adc1_outb_p_i[2]" IOSTANDARD = "LVDS_25";
+NET "adc1_outa_n_i[3]" LOC = "AE12";
+NET "adc1_outa_n_i[3]" IOSTANDARD = "LVDS_25";
+NET "adc1_outa_p_i[3]" LOC = "AD12";
+NET "adc1_outa_p_i[3]" IOSTANDARD = "LVDS_25";
+NET "adc1_outb_n_i[3]" LOC = "AF11";
+NET "adc1_outb_n_i[3]" IOSTANDARD = "LVDS_25";
+NET "adc1_outb_p_i[3]" LOC = "AE11";
+NET "adc1_outb_p_i[3]" IOSTANDARD = "LVDS_25";
+NET "adc1_spi_din_i" LOC = "AB17";
+NET "adc1_spi_din_i" IOSTANDARD = "LVCMOS25";
+NET "adc1_spi_dout_o" LOC = "AA21";
+NET "adc1_spi_dout_o" IOSTANDARD = "LVCMOS25";
+NET "adc1_spi_sck_o" LOC = "Y21";
+NET "adc1_spi_sck_o" IOSTANDARD = "LVCMOS25";
+NET "adc1_spi_cs_adc_n_o" LOC = "W20";
+NET "adc1_spi_cs_adc_n_o" IOSTANDARD = "LVCMOS25";
+NET "adc1_spi_cs_dac1_n_o" LOC = "W19";
+NET "adc1_spi_cs_dac1_n_o" IOSTANDARD = "LVCMOS25";
+NET "adc1_spi_cs_dac2_n_o" LOC = "Y19";
+NET "adc1_spi_cs_dac2_n_o" IOSTANDARD = "LVCMOS25";
+NET "adc1_spi_cs_dac3_n_o" LOC = "AA19";
+NET "adc1_spi_cs_dac3_n_o" IOSTANDARD = "LVCMOS25";
+NET "adc1_spi_cs_dac4_n_o" LOC = "AB19";
+NET "adc1_spi_cs_dac4_n_o" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_dac_clr_n_o" LOC = "Y20";
+NET "adc1_gpio_dac_clr_n_o" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_led_acq_o" LOC = "AC22";
+NET "adc1_gpio_led_acq_o" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_led_trig_o" LOC = "AA22";
+NET "adc1_gpio_led_trig_o" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch1_o[0]" LOC = "AC19";
+NET "adc1_gpio_ssr_ch1_o[0]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch1_o[1]" LOC = "AD19";
+NET "adc1_gpio_ssr_ch1_o[1]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch1_o[2]" LOC = "AC20";
+NET "adc1_gpio_ssr_ch1_o[2]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch1_o[3]" LOC = "AD17";
+NET "adc1_gpio_ssr_ch1_o[3]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch1_o[4]" LOC = "AB21";
+NET "adc1_gpio_ssr_ch1_o[4]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch1_o[5]" LOC = "AC21";
+NET "adc1_gpio_ssr_ch1_o[5]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch1_o[6]" LOC = "AC24";
+NET "adc1_gpio_ssr_ch1_o[6]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch2_o[0]" LOC = "AE19";
+NET "adc1_gpio_ssr_ch2_o[0]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch2_o[1]" LOC = "AF23";
+NET "adc1_gpio_ssr_ch2_o[1]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch2_o[2]" LOC = "AE24";
+NET "adc1_gpio_ssr_ch2_o[2]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch2_o[3]" LOC = "AF24";
+NET "adc1_gpio_ssr_ch2_o[3]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch2_o[4]" LOC = "AD22";
+NET "adc1_gpio_ssr_ch2_o[4]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch2_o[5]" LOC = "AB20";
+NET "adc1_gpio_ssr_ch2_o[5]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch2_o[6]" LOC = "AE22";
+NET "adc1_gpio_ssr_ch2_o[6]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch3_o[0]" LOC = "AB12";
+NET "adc1_gpio_ssr_ch3_o[0]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch3_o[1]" LOC = "AC12";
+NET "adc1_gpio_ssr_ch3_o[1]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch3_o[2]" LOC = "AE15";
+NET "adc1_gpio_ssr_ch3_o[2]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch3_o[3]" LOC = "AF15";
+NET "adc1_gpio_ssr_ch3_o[3]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch3_o[4]" LOC = "Y16";
+NET "adc1_gpio_ssr_ch3_o[4]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch3_o[5]" LOC = "AB16";
+NET "adc1_gpio_ssr_ch3_o[5]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch3_o[6]" LOC = "AF19";
+NET "adc1_gpio_ssr_ch3_o[6]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch4_o[0]" LOC = "AC11";
+NET "adc1_gpio_ssr_ch4_o[0]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch4_o[1]" LOC = "AD11";
+NET "adc1_gpio_ssr_ch4_o[1]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch4_o[2]" LOC = "AE13";
+NET "adc1_gpio_ssr_ch4_o[2]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch4_o[3]" LOC = "AF13";
+NET "adc1_gpio_ssr_ch4_o[3]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch4_o[4]" LOC = "AJ15";
+NET "adc1_gpio_ssr_ch4_o[4]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch4_o[5]" LOC = "AD10";
+NET "adc1_gpio_ssr_ch4_o[5]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_ssr_ch4_o[6]" LOC = "AK15";
+NET "adc1_gpio_ssr_ch4_o[6]" IOSTANDARD = "LVCMOS25";
+NET "adc1_gpio_si570_oe_o" LOC = "AE10";
+NET "adc1_gpio_si570_oe_o" IOSTANDARD = "LVCMOS25";
+NET "adc1_si570_scl_b" LOC = "AF21";
+NET "adc1_si570_scl_b" IOSTANDARD = "LVCMOS25";
+NET "adc1_si570_sda_b" LOC = "AE21";
+NET "adc1_si570_sda_b" IOSTANDARD = "LVCMOS25";
+NET "adc1_one_wire_b" LOC = "AD24";
+NET "adc1_one_wire_b" IOSTANDARD = "LVCMOS25";
+# <ucfgen_end>
+
+
+#===============================================================================
+# Timing constraints
+#===============================================================================
+
+# System clock
+
+NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
+TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
+
+# DDR3
+
+#NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK5";
+#TIMESPEC "TS_SYS_CLK5" = PERIOD "SYS_CLK5"  3.0  ns HIGH 50 %;
+
+# ADC
+NET "adc0_dco_n_i" TNM_NET = adc0_dco_n_i;
+TIMESPEC TS_adc0_dco_n_i = PERIOD "adc0_dco_n_i" 2 ns HIGH 50%;
+
+NET "adc1_dco_n_i" TNM_NET = adc1_dco_n_i;
+TIMESPEC TS_adc1_dco_n_i = PERIOD "adc1_dco_n_i" 2 ns HIGH 50%;
+
+#===============================================================================
+# IOBs
+#===============================================================================
+
+#INST "cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/s_out" IOB=FALSE;
+#INST "cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/clgen/clk_out" IOB=FALSE;
+
+
+#===============================================================================
+# Terminations
+#===============================================================================
+
+# DDR3
+
+NET "ddr0_dq_b[*]"   IN_TERM = NONE;
+NET "ddr0_ldqs_p_b"  IN_TERM = NONE;
+NET "ddr0_ldqs_n_b"  IN_TERM = NONE;
+NET "ddr0_udqs_p_b"  IN_TERM = NONE;
+NET "ddr0_udqs_n_b"  IN_TERM = NONE;
+
+NET "ddr1_dq_b[*]"   IN_TERM = NONE;
+NET "ddr1_ldqs_p_b"  IN_TERM = NONE;
+NET "ddr1_ldqs_n_b"  IN_TERM = NONE;
+NET "ddr1_udqs_p_b"  IN_TERM = NONE;
+NET "ddr1_udqs_n_b"  IN_TERM = NONE;
+
+
+#===============================================================================
+# False Path
+#===============================================================================
+
+# Reset
+
+NET "cmp_sync_ddr_rst/sync2" TIG;
+NET "powerup_rst_n" TIG;
+
+
+# DDR3
+
+NET "cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
+NET "cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_pll_lock" TIG;
+NET "cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/hard_done_cal" TIG;
+NET "cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
+
+NET "cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
+NET "cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_pll_lock" TIG;
+NET "cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/hard_done_cal" TIG;
+NET "cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
--- a/hdl/svec/syn/Makefile
+++ b/hdl/svec/syn/Makefile
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+PROJECT := svec_fmc_adc_100Ms.xise
+ISE_CRAP := *.b svec_top_fmc_adc_100Ms_summary.html *.tcl svec_top_fmc_adc_100Ms.bld svec_top_fmc_adc_100Ms.cmd_log *.drc svec_top_fmc_adc_100Ms.lso *.ncd svec_top_fmc_adc_100Ms.ngc svec_top_fmc_adc_100Ms.ngd svec_top_fmc_adc_100Ms.ngr svec_top_fmc_adc_100Ms.pad svec_top_fmc_adc_100Ms.par svec_top_fmc_adc_100Ms.pcf svec_top_fmc_adc_100Ms.prj svec_top_fmc_adc_100Ms.ptwx svec_top_fmc_adc_100Ms.stx svec_top_fmc_adc_100Ms.syr svec_top_fmc_adc_100Ms.twr svec_top_fmc_adc_100Ms.twx svec_top_fmc_adc_100Ms.gise svec_top_fmc_adc_100Ms.unroutes svec_top_fmc_adc_100Ms.ut svec_top_fmc_adc_100Ms.xpi svec_top_fmc_adc_100Ms.xst svec_top_fmc_adc_100Ms_bitgen.xwbt svec_top_fmc_adc_100Ms_envsettings.html svec_top_fmc_adc_100Ms_guide.ncd svec_top_fmc_adc_100Ms_map.map svec_top_fmc_adc_100Ms_map.mrp svec_top_fmc_adc_100Ms_map.ncd svec_top_fmc_adc_100Ms_map.ngm svec_top_fmc_adc_100Ms_map.xrpt svec_top_fmc_adc_100Ms_ngdbuild.xrpt svec_top_fmc_adc_100Ms_pad.csv svec_top_fmc_adc_100Ms_pad.txt svec_top_fmc_adc_100Ms_par.xrpt svec_top_fmc_adc_100Ms_summary.xml svec_top_fmc_adc_100Ms_usage.xml svec_top_fmc_adc_100Ms_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
+
+#target for performing local synthesis
+local:
+		echo "project open $(PROJECT)" > run.tcl
+		echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
+		xtclsh run.tcl
+
+
+#target for cleaing all intermediate stuff
+clean:
+		rm -f $(ISE_CRAP)
+		rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
+    
+#target for cleaning final files
+mrproper:
+		rm -f *.bit *.bin *.mcs
+
--- a/hdl/svec/syn/Manifest.py
+++ b/hdl/svec/syn/Manifest.py
+target = "xilinx"
+action = "synthesis"
+
+syn_device = "xc6slx150t"
+syn_grade = "-3"
+syn_package = "fgg900"
+syn_top = "svec_top_fmc_adc_100Ms"
+syn_project = "svec_fmc_adc_100Ms.xise"
+
+files = [
+    "../svec_top_fmc_adc_100Ms.ucf",
+    "../../ip_cores/adc_sync_fifo.ngc",
+    "../../ip_cores/multishot_dpram.ngc",
+    "../../ip_cores/wb_ddr_fifo.ngc",
+    "../../ip_cores/adc_serdes.vhd",
+    "../../ip_cores/monostable/monostable_rtl.vhd",
+    "../../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd",
+    "../../ip_cores/utils/utils_pkg.vhd"]
+
+modules = { "local" : ["../rtl",
+                       "../../adc/rtl",
+                       "../../ip_cores/timetag_core/rtl"],
+            "git" : ["git://ohwr.org/hdl-core-lib/general-cores.git::sdb_extension",
+                     "git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git::svec_bank4_64b_32b_bank5_64b_32b",
+                     "git://ohwr.org/hdl-core-lib/vme64x-core.git::master"]}
+
+fetchto="../../ip_cores"
--- a/hdl/svec/syn/svec_fmc_adc_100Ms.xise
+++ b/hdl/svec/syn/svec_fmc_adc_100Ms.xise
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+  <properties>
+    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
+    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx150t" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|svec_top_fmc_adc_100Ms" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/svec_top_fmc_adc_100Ms" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="svec_top_fmc_adc_100Ms" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Package" xil_pn:value="fgg900" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="svec_top_fmc_adc_100Ms_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="svec_top_fmc_adc_100Ms_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="svec_top_fmc_adc_100Ms_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="svec_top_fmc_adc_100Ms_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="svec_fmc_adc_100Ms" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-07-05T15:02:55" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="2F47B8ED2DED321859CB2D4E79F0E589" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <libraries>
+    <library xil_pn:name="blk_mem_gen_v4_1"/>
+    <library xil_pn:name="fifo_generator_v6_1"/>
+  </libraries>
+
+  <files>
+    <file xil_pn:name="../svec_top_fmc_adc_100Ms.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/adc_sync_fifo.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/multishot_dpram.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wb_ddr_fifo.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_as.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss_fwft.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="57"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_blk_ramfifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="58"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="59"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="60"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="61"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_as.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="62"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="64"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="67"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="75"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="78"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="79"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <library xil_pn:name="fifo_generator_v6_1"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="191"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="192"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="193"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="194"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="195"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="196"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="197"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="198"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="199"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="200"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="201"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="202"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/ddr3_ctrl_svec_bank4_64b_32b.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="203"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/memc4_infrastructure.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="204"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/memc4_wrapper.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="205"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="206"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="207"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="208"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="209"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="210"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/ddr3_ctrl_svec_bank5_64b_32b.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="211"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/memc5_infrastructure.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="212"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/memc5_wrapper.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="213"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="214"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="215"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="216"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="217"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="218"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/vme64x_pack.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="219"/>
+    </file>
+    <file xil_pn:name="../rtl/svec_top_fmc_adc_100Ms.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="220"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_pack.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="221"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="222"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Access_Decode.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="223"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Am_Match.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="224"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="225"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CSR_pack.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="226"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="227"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="228"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CRAM.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="229"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Funct_Match.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="230"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Init.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="231"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="232"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_SharedComps.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="233"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_swapper.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="234"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Wb_master.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="235"/>
+    </file>
+  </files>
+
+  <bindings/>
+
+  <version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
+
+</project>
--- a/hdl/svec/wb_gen/Makefile
+++ b/hdl/svec/wb_gen/Makefile
+WBGEN2=~/projects/wbgen2/wbgen2
+RTL=../rtl/
+TEX=../../../documentation/manuals/firmware/
+
+carrier_csr:
+	$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
+	$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
+
+irq_controller_regs:
+	$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
+	$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
--- a/hdl/svec/wb_gen/carrier_csr.h
+++ b/hdl/svec/wb_gen/carrier_csr.h
+/*
+  Register definitions for slave core: SVEC carrier control and status registers
+
+  * File           : svec_carrier_csr.h
+  * Author         : auto-generated by wbgen2 from svec_carrier_csr.wb
+  * Created        : Fri Jul  5 10:44:08 2013
+  * Standard       : ANSI C
+
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE svec_carrier_csr.wb
+    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_SVEC_CARRIER_CSR_WB
+#define __WBGEN2_REGDEFS_SVEC_CARRIER_CSR_WB
+
+#include <inttypes.h>
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: Carrier type and PCB version */
+
+/* definitions for field: PCB revision in reg: Carrier type and PCB version */
+#define CARRIER_CSR_CARRIER_PCB_REV_MASK      WBGEN2_GEN_MASK(0, 5)
+#define CARRIER_CSR_CARRIER_PCB_REV_SHIFT     0
+#define CARRIER_CSR_CARRIER_PCB_REV_W(value)  WBGEN2_GEN_WRITE(value, 0, 5)
+#define CARRIER_CSR_CARRIER_PCB_REV_R(reg)    WBGEN2_GEN_READ(reg, 0, 5)
+
+/* definitions for field: Reserved register in reg: Carrier type and PCB version */
+#define CARRIER_CSR_CARRIER_RESERVED_MASK     WBGEN2_GEN_MASK(5, 11)
+#define CARRIER_CSR_CARRIER_RESERVED_SHIFT    5
+#define CARRIER_CSR_CARRIER_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 5, 11)
+#define CARRIER_CSR_CARRIER_RESERVED_R(reg)   WBGEN2_GEN_READ(reg, 5, 11)
+
+/* definitions for field: Carrier type in reg: Carrier type and PCB version */
+#define CARRIER_CSR_CARRIER_TYPE_MASK         WBGEN2_GEN_MASK(16, 16)
+#define CARRIER_CSR_CARRIER_TYPE_SHIFT        16
+#define CARRIER_CSR_CARRIER_TYPE_W(value)     WBGEN2_GEN_WRITE(value, 16, 16)
+#define CARRIER_CSR_CARRIER_TYPE_R(reg)       WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: Status */
+
+/* definitions for field: FMC 1 presence in reg: Status */
+#define CARRIER_CSR_STAT_FMC0_PRES            WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: FMC 2 presence in reg: Status */
+#define CARRIER_CSR_STAT_FMC1_PRES            WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: System clock PLL status in reg: Status */
+#define CARRIER_CSR_STAT_SYS_PLL_LCK          WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: DDR3 bank 4 calibration status in reg: Status */
+#define CARRIER_CSR_STAT_DDR0_CAL_DONE        WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for field: DDR3 bank 5 calibration status in reg: Status */
+#define CARRIER_CSR_STAT_DDR1_CAL_DONE        WBGEN2_GEN_MASK(4, 1)
+
+/* definitions for field: Reserved in reg: Status */
+#define CARRIER_CSR_STAT_RESERVED_MASK        WBGEN2_GEN_MASK(5, 27)
+#define CARRIER_CSR_STAT_RESERVED_SHIFT       5
+#define CARRIER_CSR_STAT_RESERVED_W(value)    WBGEN2_GEN_WRITE(value, 5, 27)
+#define CARRIER_CSR_STAT_RESERVED_R(reg)      WBGEN2_GEN_READ(reg, 5, 27)
+
+/* definitions for register: Control */
+
+/* definitions for field: Front panel LED manual control in reg: Control */
+#define CARRIER_CSR_CTRL_FP_LEDS_MAN_MASK     WBGEN2_GEN_MASK(0, 16)
+#define CARRIER_CSR_CTRL_FP_LEDS_MAN_SHIFT    0
+#define CARRIER_CSR_CTRL_FP_LEDS_MAN_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
+#define CARRIER_CSR_CTRL_FP_LEDS_MAN_R(reg)   WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Reserved in reg: Control */
+#define CARRIER_CSR_CTRL_RESERVED_MASK        WBGEN2_GEN_MASK(16, 16)
+#define CARRIER_CSR_CTRL_RESERVED_SHIFT       16
+#define CARRIER_CSR_CTRL_RESERVED_W(value)    WBGEN2_GEN_WRITE(value, 16, 16)
+#define CARRIER_CSR_CTRL_RESERVED_R(reg)      WBGEN2_GEN_READ(reg, 16, 16)
+
+PACKED struct CARRIER_CSR_WB {
+  /* [0x0]: REG Carrier type and PCB version */
+  uint32_t CARRIER;
+  /* [0x4]: REG Status */
+  uint32_t STAT;
+  /* [0x8]: REG Control */
+  uint32_t CTRL;
+};
+
+#endif
--- a/hdl/svec/wb_gen/carrier_csr.htm
+++ b/hdl/svec/wb_gen/carrier_csr.htm
+<HTML>
+<HEAD>
+<TITLE>carrier_csr</TITLE>
+<STYLE TYPE="text/css" MEDIA="all">
+
+	<!--
+  BODY  { background: white; color: black;
+  			  font-family: Arial,Helvetica; font-size:12; }
+	h1 { font-family: Trebuchet MS,Arial,Helvetica; font-size:30; color:#404040; }
+	h2 { font-family: Trebuchet MS,Arial,Helvetica; font-size:22; color:#404040; }
+	h3 { font-family: Trebuchet MS,Arial,Helvetica; font-size:16; color:#404040; }
+	.td_arrow_left { padding:0px; background: #ffffff; text-align: right; font-size:12;}
+	.td_arrow_right { padding:0px; background: #ffffff; text-align: left; font-size:12;}
+	.td_code { font-family:Courier New,Courier; padding: 3px; }
+	.td_desc { padding: 3px; }
+	.td_sym_center { background: #e0e0f0; padding: 3px; }
+	.td_port_name { font-family:Courier New,Courier; background: #e0e0f0; text-align: right; font-weight:bold;padding: 3px; width:200px; }
+	.td_pblock_left { font-family:Courier New,Courier; background: #e0e0f0; padding: 0px; text-align: left; }
+	.td_pblock_right { font-family:Courier New,Courier; background: #e0e0f0; padding: 0px; text-align: right; }
+	.td_bit { background: #ffffff; color:#404040; font-size:10; width: 70px; font-family:Courier New,Courier; padding: 3px; text-align:center; }
+	.td_field { background: #e0e0f0; padding: 3px; text-align:center; }
+	.td_unused { background: #a0a0a0; padding: 3px; text-align:center;  }
+	th { font-weight:bold; color:#ffffff; background: #202080; padding:3px; }
+	.tr_even { background: #f0eff0; }
+	.tr_odd { background: #e0e0f0; }
+	-->
+</STYLE>
+</HEAD>
+<BODY>
+<h1 class="heading">carrier_csr</h1>
+<h3>SVEC carrier control and status registers</h3>
+<p>Wishbone slave for control and status registers related to the SVEC FMC carrier</p>
+<h3>Contents:</h3>
+<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
+<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
+<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
+<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">Carrier type and PCB version</a></span><br/>
+<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Status</a></span><br/>
+<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">Control</a></span><br/>
+<h3><a name="sect_1_0">1. Memory map summary</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<th >
+H/W Address
+</th>
+<th >
+Type
+</th>
+<th >
+Name
+</th>
+<th >
+VHDL/Verilog prefix
+</th>
+<th >
+C prefix
+</th>
+</tr>
+<tr class="tr_odd">
+<td  class="td_code">
+0x0
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#CARRIER">Carrier type and PCB version</a>
+</td>
+<td  class="td_code">
+carrier_csr_carrier
+</td>
+<td  class="td_code">
+CARRIER
+</td>
+</tr>
+<tr class="tr_even">
+<td  class="td_code">
+0x1
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#STAT">Status</a>
+</td>
+<td  class="td_code">
+carrier_csr_stat
+</td>
+<td  class="td_code">
+STAT
+</td>
+</tr>
+<tr class="tr_odd">
+<td  class="td_code">
+0x2
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#CTRL">Control</a>
+</td>
+<td  class="td_code">
+carrier_csr_ctrl
+</td>
+<td  class="td_code">
+CTRL
+</td>
+</tr>
+</table>
+
+<h3><a name="sect_2_0">2. HDL symbol</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_arrow_left">
+&rarr;
+</td>
+<td  class="td_pblock_left">
+rst_n_i
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+<b>Carrier type and PCB version:</b>
+</td>
+<td  class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+&rarr;
+</td>
+<td  class="td_pblock_left">
+clk_sys_i
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+carrier_csr_carrier_pcb_rev_i[4:0]
+</td>
+<td  class="td_arrow_right">
+&lArr;
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+&rArr;
+</td>
+<td  class="td_pblock_left">
+wb_adr_i[1:0]
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+carrier_csr_carrier_reserved_i[10:0]
+</td>
+<td  class="td_arrow_right">
+&lArr;
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+&rArr;
+</td>
+<td  class="td_pblock_left">
+wb_dat_i[31:0]
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+carrier_csr_carrier_type_i[15:0]
+</td>
+<td  class="td_arrow_right">
+&lArr;
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+&lArr;
+</td>
+<td  class="td_pblock_left">
+wb_dat_o[31:0]
+</td>
+<td  class="td_sym_center">
+&nbsp;
+</td>
+<td  class="td_pblock_right">
+
+</td>
+<td  class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+&rarr;
+</td>
+<td  class="td_pblock_left">
+wb_cyc_i
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+<b>Status:</b>
+</td>
+<td  class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+&rArr;
+</td>
+<td  class="td_pblock_left">
+wb_sel_i[3:0]
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+carrier_csr_stat_fmc0_pres_i
+</td>
+<td  class="td_arrow_right">
+&larr;
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+&rarr;
+</td>
+<td  class="td_pblock_left">
+wb_stb_i
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+carrier_csr_stat_fmc1_pres_i
+</td>
+<td  class="td_arrow_right">
+&larr;
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+&rarr;
+</td>
+<td  class="td_pblock_left">
+wb_we_i
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+carrier_csr_stat_sys_pll_lck_i
+</td>
+<td  class="td_arrow_right">
+&larr;
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+&larr;
+</td>
+<td  class="td_pblock_left">
+wb_ack_o
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+carrier_csr_stat_ddr0_cal_done_i
+</td>
+<td  class="td_arrow_right">
+&larr;
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+&larr;
+</td>
+<td  class="td_pblock_left">
+wb_stall_o
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+carrier_csr_stat_ddr1_cal_done_i
+</td>
+<td  class="td_arrow_right">
+&larr;
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+
+</td>
+<td  class="td_pblock_left">
+
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+carrier_csr_stat_reserved_i[26:0]
+</td>
+<td  class="td_arrow_right">
+&lArr;
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+
+</td>
+<td  class="td_pblock_left">
+
+</td>
+<td  class="td_sym_center">
+&nbsp;
+</td>
+<td  class="td_pblock_right">
+
+</td>
+<td  class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+
+</td>
+<td  class="td_pblock_left">
+
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+<b>Control:</b>
+</td>
+<td  class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+
+</td>
+<td  class="td_pblock_left">
+
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+carrier_csr_ctrl_fp_leds_man_o[15:0]
+</td>
+<td  class="td_arrow_right">
+&rArr;
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+
+</td>
+<td  class="td_pblock_left">
+
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+carrier_csr_ctrl_reserved_o[15:0]
+</td>
+<td  class="td_arrow_right">
+&rArr;
+</td>
+</tr>
+</table>
+
+<h3><a name="sect_3_0">3. Register description</a></h3>
+<a name="CARRIER"></a>
+<h3><a name="sect_3_1">3.1. Carrier type and PCB version</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td  class="td_code">
+carrier_csr_carrier
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td  class="td_code">
+0x0
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td  class="td_code">
+CARRIER
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td  class="td_code">
+0x0
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+31
+</td>
+<td  class="td_bit">
+30
+</td>
+<td  class="td_bit">
+29
+</td>
+<td  class="td_bit">
+28
+</td>
+<td  class="td_bit">
+27
+</td>
+<td  class="td_bit">
+26
+</td>
+<td  class="td_bit">
+25
+</td>
+<td  class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+TYPE[15:8]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+23
+</td>
+<td  class="td_bit">
+22
+</td>
+<td  class="td_bit">
+21
+</td>
+<td  class="td_bit">
+20
+</td>
+<td  class="td_bit">
+19
+</td>
+<td  class="td_bit">
+18
+</td>
+<td  class="td_bit">
+17
+</td>
+<td  class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+TYPE[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+15
+</td>
+<td  class="td_bit">
+14
+</td>
+<td  class="td_bit">
+13
+</td>
+<td  class="td_bit">
+12
+</td>
+<td  class="td_bit">
+11
+</td>
+<td  class="td_bit">
+10
+</td>
+<td  class="td_bit">
+9
+</td>
+<td  class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+RESERVED[10:3]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+7
+</td>
+<td  class="td_bit">
+6
+</td>
+<td  class="td_bit">
+5
+</td>
+<td  class="td_bit">
+4
+</td>
+<td  class="td_bit">
+3
+</td>
+<td  class="td_bit">
+2
+</td>
+<td  class="td_bit">
+1
+</td>
+<td  class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=3  class="td_field">
+RESERVED[2:0]
+</td>
+<td style="border: solid 1px black;" colspan=5  class="td_field">
+PCB_REV[4:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+PCB_REV
+</b>[<i>read-only</i>]: PCB revision
+<br>Binary coded PCB layout revision.
+<li><b>
+RESERVED
+</b>[<i>read-only</i>]: Reserved register
+<br>Ignore on read, write with 0's.
+<li><b>
+TYPE
+</b>[<i>read-only</i>]: Carrier type
+<br>Carrier type identifier<br>1 = SPEC<br>2 = SVEC<br>3 = VFC<br>4 = SPEXI
+</ul>
+<a name="STAT"></a>
+<h3><a name="sect_3_2">3.2. Status</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td  class="td_code">
+carrier_csr_stat
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td  class="td_code">
+0x1
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td  class="td_code">
+STAT
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td  class="td_code">
+0x4
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+31
+</td>
+<td  class="td_bit">
+30
+</td>
+<td  class="td_bit">
+29
+</td>
+<td  class="td_bit">
+28
+</td>
+<td  class="td_bit">
+27
+</td>
+<td  class="td_bit">
+26
+</td>
+<td  class="td_bit">
+25
+</td>
+<td  class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+RESERVED[26:19]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+23
+</td>
+<td  class="td_bit">
+22
+</td>
+<td  class="td_bit">
+21
+</td>
+<td  class="td_bit">
+20
+</td>
+<td  class="td_bit">
+19
+</td>
+<td  class="td_bit">
+18
+</td>
+<td  class="td_bit">
+17
+</td>
+<td  class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+RESERVED[18:11]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+15
+</td>
+<td  class="td_bit">
+14
+</td>
+<td  class="td_bit">
+13
+</td>
+<td  class="td_bit">
+12
+</td>
+<td  class="td_bit">
+11
+</td>
+<td  class="td_bit">
+10
+</td>
+<td  class="td_bit">
+9
+</td>
+<td  class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+RESERVED[10:3]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+7
+</td>
+<td  class="td_bit">
+6
+</td>
+<td  class="td_bit">
+5
+</td>
+<td  class="td_bit">
+4
+</td>
+<td  class="td_bit">
+3
+</td>
+<td  class="td_bit">
+2
+</td>
+<td  class="td_bit">
+1
+</td>
+<td  class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=3  class="td_field">
+RESERVED[2:0]
+</td>
+<td style="border: solid 1px black;" colspan=1  class="td_field">
+DDR1_CAL_DONE
+</td>
+<td style="border: solid 1px black;" colspan=1  class="td_field">
+DDR0_CAL_DONE
+</td>
+<td style="border: solid 1px black;" colspan=1  class="td_field">
+SYS_PLL_LCK
+</td>
+<td style="border: solid 1px black;" colspan=1  class="td_field">
+FMC1_PRES
+</td>
+<td style="border: solid 1px black;" colspan=1  class="td_field">
+FMC0_PRES
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+FMC0_PRES
+</b>[<i>read-only</i>]: FMC 1 presence
+<br>0: FMC slot 1 is populated<br>1: FMC slot 1 is not populated.
+<li><b>
+FMC1_PRES
+</b>[<i>read-only</i>]: FMC 2 presence
+<br>0: FMC slot 2 is populated<br>1: FMC slot 2 is not populated.
+<li><b>
+SYS_PLL_LCK
+</b>[<i>read-only</i>]: System clock PLL status
+<br>0: not locked<br>1: locked.
+<li><b>
+DDR0_CAL_DONE
+</b>[<i>read-only</i>]: DDR3 bank 4 calibration status
+<br>0: not done<br>1: done.
+<li><b>
+DDR1_CAL_DONE
+</b>[<i>read-only</i>]: DDR3 bank 5 calibration status
+<br>0: not done<br>1: done.
+<li><b>
+RESERVED
+</b>[<i>read-only</i>]: Reserved
+<br>Ignore on read, write with 0's.
+</ul>
+<a name="CTRL"></a>
+<h3><a name="sect_3_3">3.3. Control</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td  class="td_code">
+carrier_csr_ctrl
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td  class="td_code">
+0x2
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td  class="td_code">
+CTRL
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td  class="td_code">
+0x8
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+31
+</td>
+<td  class="td_bit">
+30
+</td>
+<td  class="td_bit">
+29
+</td>
+<td  class="td_bit">
+28
+</td>
+<td  class="td_bit">
+27
+</td>
+<td  class="td_bit">
+26
+</td>
+<td  class="td_bit">
+25
+</td>
+<td  class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+RESERVED[15:8]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+23
+</td>
+<td  class="td_bit">
+22
+</td>
+<td  class="td_bit">
+21
+</td>
+<td  class="td_bit">
+20
+</td>
+<td  class="td_bit">
+19
+</td>
+<td  class="td_bit">
+18
+</td>
+<td  class="td_bit">
+17
+</td>
+<td  class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+RESERVED[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+15
+</td>
+<td  class="td_bit">
+14
+</td>
+<td  class="td_bit">
+13
+</td>
+<td  class="td_bit">
+12
+</td>
+<td  class="td_bit">
+11
+</td>
+<td  class="td_bit">
+10
+</td>
+<td  class="td_bit">
+9
+</td>
+<td  class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+FP_LEDS_MAN[15:8]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+7
+</td>
+<td  class="td_bit">
+6
+</td>
+<td  class="td_bit">
+5
+</td>
+<td  class="td_bit">
+4
+</td>
+<td  class="td_bit">
+3
+</td>
+<td  class="td_bit">
+2
+</td>
+<td  class="td_bit">
+1
+</td>
+<td  class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+FP_LEDS_MAN[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+FP_LEDS_MAN
+</b>[<i>read/write</i>]: Front panel LED manual control
+<br>Height front panel LED, two bits per LED.<br>00 = OFF<br>01 = Green<br>10 = Red<br>11 = Orange
+<li><b>
+RESERVED
+</b>[<i>read/write</i>]: Reserved
+<br>Ignore on read, write with 0's
+</ul>
+
+
+
+</BODY>
+</HTML>
--- a/hdl/svec/wb_gen/carrier_csr.wb
+++ b/hdl/svec/wb_gen/carrier_csr.wb
+peripheral {
+  name = "SVEC carrier control and status registers";
+  description = "Wishbone slave for control and status registers related to the SVEC FMC carrier";
+  hdl_entity = "carrier_csr";
+
+  prefix = "carrier_csr";
+
+  reg {
+    name = "Carrier type and PCB version";
+    prefix = "carrier";
+
+    field {
+      name = "PCB revision";
+      description = "Binary coded PCB layout revision.";
+      prefix = "pcb_rev";
+      type = SLV;
+      size = 5;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+
+    field {
+      name = "Reserved register";
+      description = "Ignore on read, write with 0's.";
+      prefix = "reserved";
+      type = SLV;
+      size = 11;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+
+    field {
+      name = "Carrier type";
+      description = "Carrier type identifier\n1 = SPEC\n2 = SVEC\n3 = VFC\n4 = SPEXI";
+      prefix = "type";
+      type = SLV;
+      size = 16;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+  };
+
+  reg {
+    name = "Status";
+    prefix = "stat";
+
+    field {
+      name = "FMC 1 presence";
+      description = "0: FMC slot 1 is populated\n1: FMC slot 1 is not populated.";
+      prefix = "fmc0_pres";
+      type = BIT;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+
+    field {
+      name = "FMC 2 presence";
+      description = "0: FMC slot 2 is populated\n1: FMC slot 2 is not populated.";
+      prefix = "fmc1_pres";
+      type = BIT;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+
+    field {
+      name = "System clock PLL status";
+      description = "0: not locked\n1: locked.";
+      prefix = "sys_pll_lck";
+      type = BIT;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+
+    field {
+      name = "DDR3 bank 4 calibration status";
+      description = "0: not done\n1: done.";
+      prefix = "ddr0_cal_done";
+      type = BIT;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+
+    field {
+      name = "DDR3 bank 5 calibration status";
+      description = "0: not done\n1: done.";
+      prefix = "ddr1_cal_done";
+      type = BIT;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+
+    field {
+      name = "Reserved";
+      description = "Ignore on read, write with 0's.";
+      prefix = "reserved";
+      type = SLV;
+      size = 27;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+  };
+
+  reg {
+    name = "Control";
+    prefix = "ctrl";
+
+    field {
+      name = "Front panel LED manual control";
+      description = "Height front panel LED, two bits per LED.\n00 = OFF\n01 = Green\n10 = Red\n11 = Orange";
+      prefix = "fp_leds_man";
+      type = SLV;
+      size = 16;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+
+    field {
+      name = "Reserved";
+      description = "Ignore on read, write with 0's";
+      prefix = "reserved";
+      type = SLV;
+      size = 16;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+  };
+
+};
--- a/hdl/svec/wb_gen/irq_controller_regs.h
+++ b/hdl/svec/wb_gen/irq_controller_regs.h
+/*
+  Register definitions for slave core: IRQ controller registers
+
+  * File           : svec_irq_controller_regs.h
+  * Author         : auto-generated by wbgen2 from svec_irq_controller_regs.wb
+  * Created        : Fri Jul  5 10:18:32 2013
+  * Standard       : ANSI C
+
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE svec_irq_controller_regs.wb
+    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_SVEC_IRQ_CONTROLLER_REGS_WB
+#define __WBGEN2_REGDEFS_SVEC_IRQ_CONTROLLER_REGS_WB
+
+#include <inttypes.h>
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: Multiple interrupt register */
+
+/* definitions for register: Interrupt sources register  */
+
+/* definitions for register: Interrupt enable mask register */
+
+PACKED struct IRQ_CTRL_WB {
+  /* [0x0]: REG Multiple interrupt register */
+  uint32_t MULTI_IRQ;
+  /* [0x4]: REG Interrupt sources register  */
+  uint32_t SRC;
+  /* [0x8]: REG Interrupt enable mask register */
+  uint32_t EN_MASK;
+};
+
+#endif
--- a/hdl/svec/wb_gen/irq_controller_regs.htm
+++ b/hdl/svec/wb_gen/irq_controller_regs.htm
+<HTML>
+<HEAD>
+<TITLE>irq_controller_regs</TITLE>
+<STYLE TYPE="text/css" MEDIA="all">
+
+	<!--
+  BODY  { background: white; color: black;
+  			  font-family: Arial,Helvetica; font-size:12; }
+	h1 { font-family: Trebuchet MS,Arial,Helvetica; font-size:30; color:#404040; }
+	h2 { font-family: Trebuchet MS,Arial,Helvetica; font-size:22; color:#404040; }
+	h3 { font-family: Trebuchet MS,Arial,Helvetica; font-size:16; color:#404040; }
+	.td_arrow_left { padding:0px; background: #ffffff; text-align: right; font-size:12;}
+	.td_arrow_right { padding:0px; background: #ffffff; text-align: left; font-size:12;}
+	.td_code { font-family:Courier New,Courier; padding: 3px; }
+	.td_desc { padding: 3px; }
+	.td_sym_center { background: #e0e0f0; padding: 3px; }
+	.td_port_name { font-family:Courier New,Courier; background: #e0e0f0; text-align: right; font-weight:bold;padding: 3px; width:200px; }
+	.td_pblock_left { font-family:Courier New,Courier; background: #e0e0f0; padding: 0px; text-align: left; }
+	.td_pblock_right { font-family:Courier New,Courier; background: #e0e0f0; padding: 0px; text-align: right; }
+	.td_bit { background: #ffffff; color:#404040; font-size:10; width: 70px; font-family:Courier New,Courier; padding: 3px; text-align:center; }
+	.td_field { background: #e0e0f0; padding: 3px; text-align:center; }
+	.td_unused { background: #a0a0a0; padding: 3px; text-align:center;  }
+	th { font-weight:bold; color:#ffffff; background: #202080; padding:3px; }
+	.tr_even { background: #f0eff0; }
+	.tr_odd { background: #e0e0f0; }
+	-->
+</STYLE>
+</HEAD>
+<BODY>
+<h1 class="heading">irq_controller_regs</h1>
+<h3>IRQ controller registers</h3>
+<p>Wishbone slave for registers related to IRQ controller</p>
+<h3>Contents:</h3>
+<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
+<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
+<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
+<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">Multiple interrupt register</a></span><br/>
+<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Interrupt sources register </a></span><br/>
+<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">Interrupt enable mask register</a></span><br/>
+<h3><a name="sect_1_0">1. Memory map summary</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<th >
+H/W Address
+</th>
+<th >
+Type
+</th>
+<th >
+Name
+</th>
+<th >
+VHDL/Verilog prefix
+</th>
+<th >
+C prefix
+</th>
+</tr>
+<tr class="tr_odd">
+<td  class="td_code">
+0x0
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#MULTI_IRQ">Multiple interrupt register</a>
+</td>
+<td  class="td_code">
+irq_ctrl_multi_irq
+</td>
+<td  class="td_code">
+MULTI_IRQ
+</td>
+</tr>
+<tr class="tr_even">
+<td  class="td_code">
+0x1
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#SRC">Interrupt sources register </a>
+</td>
+<td  class="td_code">
+irq_ctrl_src
+</td>
+<td  class="td_code">
+SRC
+</td>
+</tr>
+<tr class="tr_odd">
+<td  class="td_code">
+0x2
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#EN_MASK">Interrupt enable mask register</a>
+</td>
+<td  class="td_code">
+irq_ctrl_en_mask
+</td>
+<td  class="td_code">
+EN_MASK
+</td>
+</tr>
+</table>
+
+<h3><a name="sect_2_0">2. HDL symbol</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_arrow_left">
+&rarr;
+</td>
+<td  class="td_pblock_left">
+rst_n_i
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+<b>Multiple interrupt register:</b>
+</td>
+<td  class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+&rarr;
+</td>
+<td  class="td_pblock_left">
+clk_sys_i
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+irq_ctrl_multi_irq_o[31:0]
+</td>
+<td  class="td_arrow_right">
+&rArr;
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+&rArr;
+</td>
+<td  class="td_pblock_left">
+wb_adr_i[1:0]
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+irq_ctrl_multi_irq_i[31:0]
+</td>
+<td  class="td_arrow_right">
+&lArr;
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+&rArr;
+</td>
+<td  class="td_pblock_left">
+wb_dat_i[31:0]
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+irq_ctrl_multi_irq_load_o
+</td>
+<td  class="td_arrow_right">
+&rarr;
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+&lArr;
+</td>
+<td  class="td_pblock_left">
+wb_dat_o[31:0]
+</td>
+<td  class="td_sym_center">
+&nbsp;
+</td>
+<td  class="td_pblock_right">
+
+</td>
+<td  class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+&rarr;
+</td>
+<td  class="td_pblock_left">
+wb_cyc_i
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+<b>Interrupt sources register :</b>
+</td>
+<td  class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+&rArr;
+</td>
+<td  class="td_pblock_left">
+wb_sel_i[3:0]
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+irq_ctrl_src_o[31:0]
+</td>
+<td  class="td_arrow_right">
+&rArr;
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+&rarr;
+</td>
+<td  class="td_pblock_left">
+wb_stb_i
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+irq_ctrl_src_i[31:0]
+</td>
+<td  class="td_arrow_right">
+&lArr;
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+&rarr;
+</td>
+<td  class="td_pblock_left">
+wb_we_i
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+irq_ctrl_src_load_o
+</td>
+<td  class="td_arrow_right">
+&rarr;
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+&larr;
+</td>
+<td  class="td_pblock_left">
+wb_ack_o
+</td>
+<td  class="td_sym_center">
+&nbsp;
+</td>
+<td  class="td_pblock_right">
+
+</td>
+<td  class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+&larr;
+</td>
+<td  class="td_pblock_left">
+wb_stall_o
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+<b>Interrupt enable mask register:</b>
+</td>
+<td  class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+
+</td>
+<td  class="td_pblock_left">
+
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+irq_ctrl_en_mask_o[31:0]
+</td>
+<td  class="td_arrow_right">
+&rArr;
+</td>
+</tr>
+</table>
+
+<h3><a name="sect_3_0">3. Register description</a></h3>
+<a name="MULTI_IRQ"></a>
+<h3><a name="sect_3_1">3.1. Multiple interrupt register</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td  class="td_code">
+irq_ctrl_multi_irq
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td  class="td_code">
+0x0
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td  class="td_code">
+MULTI_IRQ
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td  class="td_code">
+0x0
+</td>
+</tr>
+</table>
+<p>
+Multiple interrupts occurs before irq source is read.<br>Write '1' to clear a bit.<br><br>Bit 0: FMC slot 1 trigger.<br>Bit 1: FMC slot 1 acquisition end.<br>Bit 2: FMC slot 2 trigger.<br>Bit 3: FMC slot 2 acquisition end.
+</p>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+31
+</td>
+<td  class="td_bit">
+30
+</td>
+<td  class="td_bit">
+29
+</td>
+<td  class="td_bit">
+28
+</td>
+<td  class="td_bit">
+27
+</td>
+<td  class="td_bit">
+26
+</td>
+<td  class="td_bit">
+25
+</td>
+<td  class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+MULTI_IRQ[31:24]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+23
+</td>
+<td  class="td_bit">
+22
+</td>
+<td  class="td_bit">
+21
+</td>
+<td  class="td_bit">
+20
+</td>
+<td  class="td_bit">
+19
+</td>
+<td  class="td_bit">
+18
+</td>
+<td  class="td_bit">
+17
+</td>
+<td  class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+MULTI_IRQ[23:16]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+15
+</td>
+<td  class="td_bit">
+14
+</td>
+<td  class="td_bit">
+13
+</td>
+<td  class="td_bit">
+12
+</td>
+<td  class="td_bit">
+11
+</td>
+<td  class="td_bit">
+10
+</td>
+<td  class="td_bit">
+9
+</td>
+<td  class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+MULTI_IRQ[15:8]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+7
+</td>
+<td  class="td_bit">
+6
+</td>
+<td  class="td_bit">
+5
+</td>
+<td  class="td_bit">
+4
+</td>
+<td  class="td_bit">
+3
+</td>
+<td  class="td_bit">
+2
+</td>
+<td  class="td_bit">
+1
+</td>
+<td  class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+MULTI_IRQ[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+MULTI_IRQ
+</b>[<i>read/write</i>]: Multiple interrupt
+</ul>
+<a name="SRC"></a>
+<h3><a name="sect_3_2">3.2. Interrupt sources register </a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td  class="td_code">
+irq_ctrl_src
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td  class="td_code">
+0x1
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td  class="td_code">
+SRC
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td  class="td_code">
+0x4
+</td>
+</tr>
+</table>
+<p>
+Indicates the interrupt source.<br>Write '1' to clear a bit.<br><br>Bit 0: FMC slot 1 trigger.<br>Bit 1: FMC slot 1 acquisition end.<br>Bit 2: FMC slot 2 trigger.<br>Bit 3: FMC slot 2 acquisition end.
+</p>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+31
+</td>
+<td  class="td_bit">
+30
+</td>
+<td  class="td_bit">
+29
+</td>
+<td  class="td_bit">
+28
+</td>
+<td  class="td_bit">
+27
+</td>
+<td  class="td_bit">
+26
+</td>
+<td  class="td_bit">
+25
+</td>
+<td  class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+SRC[31:24]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+23
+</td>
+<td  class="td_bit">
+22
+</td>
+<td  class="td_bit">
+21
+</td>
+<td  class="td_bit">
+20
+</td>
+<td  class="td_bit">
+19
+</td>
+<td  class="td_bit">
+18
+</td>
+<td  class="td_bit">
+17
+</td>
+<td  class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+SRC[23:16]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+15
+</td>
+<td  class="td_bit">
+14
+</td>
+<td  class="td_bit">
+13
+</td>
+<td  class="td_bit">
+12
+</td>
+<td  class="td_bit">
+11
+</td>
+<td  class="td_bit">
+10
+</td>
+<td  class="td_bit">
+9
+</td>
+<td  class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+SRC[15:8]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+7
+</td>
+<td  class="td_bit">
+6
+</td>
+<td  class="td_bit">
+5
+</td>
+<td  class="td_bit">
+4
+</td>
+<td  class="td_bit">
+3
+</td>
+<td  class="td_bit">
+2
+</td>
+<td  class="td_bit">
+1
+</td>
+<td  class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+SRC[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+SRC
+</b>[<i>read/write</i>]: Interrupt sources
+</ul>
+<a name="EN_MASK"></a>
+<h3><a name="sect_3_3">3.3. Interrupt enable mask register</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td  class="td_code">
+irq_ctrl_en_mask
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td  class="td_code">
+0x2
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td  class="td_code">
+EN_MASK
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td  class="td_code">
+0x8
+</td>
+</tr>
+</table>
+<p>
+Bit mask to independently enable interrupt sources.<br><br>Bit 0: FMC slot 1 trigger.<br>Bit 1: FMC slot 1 acquisition end.<br>Bit 2: FMC slot 2 trigger.<br>Bit 3: FMC slot 2 acquisition end.
+</p>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+31
+</td>
+<td  class="td_bit">
+30
+</td>
+<td  class="td_bit">
+29
+</td>
+<td  class="td_bit">
+28
+</td>
+<td  class="td_bit">
+27
+</td>
+<td  class="td_bit">
+26
+</td>
+<td  class="td_bit">
+25
+</td>
+<td  class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+EN_MASK[31:24]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+23
+</td>
+<td  class="td_bit">
+22
+</td>
+<td  class="td_bit">
+21
+</td>
+<td  class="td_bit">
+20
+</td>
+<td  class="td_bit">
+19
+</td>
+<td  class="td_bit">
+18
+</td>
+<td  class="td_bit">
+17
+</td>
+<td  class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+EN_MASK[23:16]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+15
+</td>
+<td  class="td_bit">
+14
+</td>
+<td  class="td_bit">
+13
+</td>
+<td  class="td_bit">
+12
+</td>
+<td  class="td_bit">
+11
+</td>
+<td  class="td_bit">
+10
+</td>
+<td  class="td_bit">
+9
+</td>
+<td  class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+EN_MASK[15:8]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td  class="td_bit">
+7
+</td>
+<td  class="td_bit">
+6
+</td>
+<td  class="td_bit">
+5
+</td>
+<td  class="td_bit">
+4
+</td>
+<td  class="td_bit">
+3
+</td>
+<td  class="td_bit">
+2
+</td>
+<td  class="td_bit">
+1
+</td>
+<td  class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+EN_MASK[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+EN_MASK
+</b>[<i>read/write</i>]: Interrupt enable mask
+</ul>
+
+
+
+</BODY>
+</HTML>
--- a/hdl/svec/wb_gen/irq_controller_regs.wb
+++ b/hdl/svec/wb_gen/irq_controller_regs.wb
+peripheral {
+  name = "IRQ controller registers";
+  description = "Wishbone slave for registers related to IRQ controller";
+  hdl_entity = "irq_controller_regs";
+
+  prefix = "irq_ctrl";
+
+  reg {
+    name = "Multiple interrupt register";
+    description = "Multiple interrupts occurs before irq source is read.\nWrite '1' to clear a bit.\n\nBit 0: FMC slot 1 trigger.\nBit 1: FMC slot 1 acquisition end.\nBit 2: FMC slot 2 trigger.\nBit 3: FMC slot 2 acquisition end.";
+    prefix = "multi_irq";
+
+    field {
+      name = "Multiple interrupt";
+      type = SLV;
+      size = 32;
+      load = LOAD_EXT;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+    };
+  };
+
+  reg {
+    name = "Interrupt sources register ";
+    description = "Indicates the interrupt source.\nWrite '1' to clear a bit.\n\nBit 0: FMC slot 1 trigger.\nBit 1: FMC slot 1 acquisition end.\nBit 2: FMC slot 2 trigger.\nBit 3: FMC slot 2 acquisition end.";
+    prefix = "src";
+
+    field {
+      name = "Interrupt sources";
+      type = SLV;
+      load = LOAD_EXT;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_WRITE;
+    };
+  };
+
+  reg {
+    name = "Interrupt enable mask register";
+    description = "Bit mask to independently enable interrupt sources.\n\nBit 0: FMC slot 1 trigger.\nBit 1: FMC slot 1 acquisition end.\nBit 2: FMC slot 2 trigger.\nBit 3: FMC slot 2 acquisition end.";
+    prefix = "en_mask";
+
+    field {
+      name = "Interrupt enable mask";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+  };
+
+};