@@ -757,7 +760,7 @@ The four channels data and the trigger signal are synchronised to the system clo
The configuration signals coming from registers in the system clock domain are synchronised to the sampling clock within the Wishbone slave (@command{wbgen2} feature).
The hardware trigger source can be either internal (based on an adc input channel) or external (dedicated trigger input).
For both internal and external hardware triggers, the polarity can be selected between positive and negative slope (resp. rising and falling edge). By default the polatity is set to positive slope.
The external trigger input is synchronised to the sampling clock. The external trigger pulse must be at least one sampling clock cycle wide.
For the internal trigger source, the adc input channel and the threshold should be configured.
For both internal and external hardware triggers, the polarity can be selected between positive and negative slope (resp. rising and falling edge).
By default the polatity is set to positive slope.
The external trigger input is synchronised to the sampling clock.
The external trigger pulse must be at least one sampling clock cycle wide.
To use the internal trigger source, the adc input channel and the threshold should be configured.
By default, the channel 1 is selected and the threshold is set to 0.
Note that the threshold is 16-bit signed (two's complement).
The @ref{fig:trig_hw_int} sketches the internal hardware trigger threshold behaviour.
In addition, a glitch filter can be applied to the threshold detection.
The glitch filter is useful to trigger on noisy signal.
In order to help setting the glitch filter, an internal trigger test mode can be activated.
When the test mode is enabled, the data from channels 2 to 4 are replaced as follow:
@float
@multitable @columnfractions .12 .50
@item Channel 2 @tab Input signal over threshold
@item Channel 3 @tab Input signal over threshold filtered
@item Channel 4 @tab Trigger
@end multitable
@sp 1
@end float
The software trigger source concists in a pulse generated when a write cycle is detected on the @i{Software trigger} register.
The @ref{fig:trig_unit} shows the different trigger configurations.
For futher information on the trigger configuration registers @pxref{ADC Core Registers}.
@@ -962,8 +984,13 @@ The fixed point format is as follow:
@caption{ADC gain register format.}
@end float
@b{Note:} On FPGA start-up, the gain registers are set to 0x8000 (1.000) and the offset registers to 0x0000.
This means a unit gain and no offset.
After the offset and gain corrections are applied, the signal is saturated to 16-bit signed values (min=-32678, max=32767).
Also an additional block allows the user to set a programmable saturation value.
The saturation register takes a 15-bit unsigned value, or in other words a positive 16-bit signed value.
@b{Note:} On FPGA start-up, the gain, offset and saturation registers are set to 0x0.
Therefore, the driver has to initialise those registers.
@b{Note:} After gain and offset correction, the two LSB of the data words can be different from zero.
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@@ -994,8 +1021,6 @@ gain = DAC gain calibration value from EEPROM (16-bit fixed point)
@node Acquisition
@chapter Acquisition
@c TODO : Add description of trigger time-tag insertion
This chapter describes the two modes of acquisition, single-shot and multi-shot.
It also explains how the software is expected to control the fmc-adc acquisitions.
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@@ -1114,6 +1139,7 @@ The acquisition state machine is also represented.
The multi-shot acquisition process is almost identical to the single-shot one, except that once the acquisition is started it will go around the state machine as many time as the number of configured shots.
It means that if the board is configured for N shots, it will generate N trigger interrupts (if enabled) and then another interrupt at the end of the acquisition.
A counter, accessible via a register, shows the remaining number of shots (@pxref{ADC Core Registers}).
Unlike the single-mode acquisition, in multi-shot, the DDR memory is not used as a circular buffer.
Instead, two dual port RAM (dpram) are implemented inside the FPGA.
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@@ -1124,7 +1150,7 @@ Even shots uses dpram0 and odd shots dpram1.
The trigger time-tag requires two 64-bit word to be stored at the end of the samples.
It means that the total number of samples (pre-trigger + trigger + post-trigger) for a shot cannot exceed 2048-2=2046.
When a shot is finished, the correcponding dpram samples are written to the DDR memory.
When a shot is finished, the corresponding dpram samples are written to the DDR memory.
Only the pre-trigger samples, the post-trigger samples and the trigger time-tag are written.
The first shot is written starting at address @code{0x0}.
Then the second shot is written right after the trigger time-tag of the first shot.
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@@ -1135,16 +1161,15 @@ The @ref{fig:mem_multi_shot} shows the shots organisation in the DDR memory.
@caption{DDR memory usage in multi-shot mode acquisition.}
@end float
@b{Note:} The number of samples per shot stored in memory is equal to: number of pre-trigger samples + number of post-trigger samples + 1 (trigger sample).
@b{Note:} The number of samples per shot stored in memory is equal to: number of pre-trigger samples + number of post-trigger samples + 1 (trigger sample) + 2 (time-tag).
@b{Note:} In multi-shot mode, the start of an acquisition is prohibited if the number of sample per shot is bigger or equal to the dpram size.
