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FMC ADC 100M 14b 4cha - Gateware
Commit 2f92c67d authored by Matthieu Cattin's avatar Matthieu Cattin
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Merging sdb enabled design to master.

parents e73d48b6 9a65c3a9
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.gitignore 0 → 100644
View file @ 2f92c67d
hdl/spec/ip_cores/ddr3-sp6-core/
hdl/spec/ip_cores/general-cores/
hdl/spec/ip_cores/gn4124-core/
hdl/spec/sim/modelsim.ini
hdl/spec/sim/work/
hdl/spec/syn/_ngo/
hdl/spec/syn/_xmsgs/
hdl/spec/syn/par_usage_statistics.html
hdl/spec/syn/run.tcl
hdl/spec/syn/*.gise
hdl/spec/syn/*.bgn
hdl/spec/syn/*.bld
hdl/spec/syn/*.cmd_log
hdl/spec/syn/*.drc
hdl/spec/syn/*.lso
hdl/spec/syn/*.ncd
hdl/spec/syn/*.ngc
hdl/spec/syn/*.ngd
hdl/spec/syn/*.ngr
hdl/spec/syn/*.pad
hdl/spec/syn/*.pcf
hdl/spec/syn/*.prj
hdl/spec/syn/*.ptwx
hdl/spec/syn/*.stx
hdl/spec/syn/*.twx
hdl/spec/syn/*.unroutes
hdl/spec/syn/*.ut
hdl/spec/syn/*.xpi
hdl/spec/syn/*.xst
hdl/spec/syn/*_bitgen.xwbt
hdl/spec/syn/*_guide.ncd
hdl/spec/syn/*_map.map
hdl/spec/syn/*_map.ncd
hdl/spec/syn/*_map.ngm
hdl/spec/syn/*_map.xrpt
hdl/spec/syn/*_ngdbuild.xrpt
hdl/spec/syn/*_pad.csv
hdl/spec/syn/*_pad.txt
hdl/spec/syn/*_par.xrpt
hdl/spec/syn/*_summary.xml
hdl/spec/syn/*_usage.xml
hdl/spec/syn/*_xst.xrpt
hdl/spec/syn/webtalk.log
hdl/spec/syn/webtalk_pn.xml
hdl/spec/syn/xlnx_auto_0_xdb/
hdl/spec/syn/xst/
\ No newline at end of file
documentation/user_guides/fmcadc100m14b4cha_users_guide.tex
View file @ 2f92c67d
......@@ -69,6 +69,8 @@ Here's an overview of the fmcadc100m14b4cha board...
\subsection{Trigger}
Software and/or hardware trigger. Internal or external hardware trigger, polarity selection.
Optional additional delay on the final trigger (in sampling clock ticks).
\begin{figure}[h!]
\includegraphics[width=\textwidth]{figures/trigger_unit.pdf}
......@@ -101,6 +103,7 @@ V\subscript{out} = V\subscript{in} - (gain\subscript{dac} \cdot V\subscript{dac}
\subsection{Time-stamping}
%===============================================================================
\section{Acquisition}
......@@ -137,6 +140,7 @@ V\subscript{out} = V\subscript{in} - (gain\subscript{dac} \cdot V\subscript{dac}
%===============================================================================
\newpage
\section{Calibration}
The calibration is done once during the prodoction tests.
......@@ -145,9 +149,33 @@ The calibration process gives four values per channel and per input range:
ADC gain correction, ADC offset correction, DAC gain correction and DAC offset correction.
The temperature during the calibration process is also measured.
All the calibration values are stored in the FmcAdc100m14b4cha EEPROM.
More precisely they are stored in the "Internal Use Area" as defined in the IPMI standard\footnote{Platform Management FRU Information Storage Definition v1.0}.
Tables \ref{tab:adc_calibr_data_eeprom} and \ref{tab:dac_calibr_data_eeprom} shows the calibration data types and the arrangement in the EEPROM.
The first column "Byte offset" represents the offset within the "Internal Use Area".
The EEPROM holds a sdbfs\footnote{http://www.ohwr.org/attachments/download/1594/sdbfs-2012-09-19.pdf} file system.
In addition to the calibration values, the EEPROM also contains mandatory IPMI\footnote{Platform Management FRU Information Storage Definition v1.0}
records described in the FMC Standard VITA 57.1 (see table \ref{tab:eeprom_sdbfs} for mapping).
\begin{table}[ht]
\centering
\begin{tabularx}{\textwidth}{| l | l | l | X |}
\hline
\textbf{Byte offset} & \textbf{File name} & \textbf{File Type} & \textbf{Description} \\
\hline
0x0 & ipmi.sdb & binary & IPMI records \\
\hline
0x100 & calibration.sdb & binary & Calibration values \\
\hline
0x1000 & . & binary & Directory \\
& & & vendor = 0xCE42 \\
& & & device = 0xC5BE045E \\
\hline
\end{tabularx}
\caption{EEPROM sdbfs}
\label{tab:eeprom_sdbfs}
\end{table}
Note that the vendor value 0xCE42 corresponds to CERN. While the device value 0xC5BE045E corresponds to the first 32-bit of the md5 sum of "fmc-adc-100m14b4cha".
Tables \ref{tab:adc_calibr_data_eeprom} and \ref{tab:dac_calibr_data_eeprom} shows the calibration data types and the arrangement in the binary file.
The first column "Byte offset" represents the offset within the binary file.
\begin{table}[ht]
\centering
......@@ -253,6 +281,13 @@ Below is the pseudo-code to calculate the DAC corrected value, applying gain and
\begin{verbatim}
c_val = ((((val-0x8000+offset) << 15) * gain) >> 30)+0x8000
\end{verbatim}
where:
\begin{verbatim}
c_val = corrected value to write to DAC
val = value from user
offset = DAC offset calibration value from EEPROM
gain = DAC gain calibration value from EEPROM
\end{verbatim}
......
hdl/adc/rtl/Manifest.py
View file @ 2f92c67d
files = ["fmc_adc_100Ms_core.vhd",
"fmc_adc_100Ms_core_pkg.vhd",
"fmc_adc_100Ms_csr.vhd",
"offset_gain_s.vhd"]
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ 2f92c67d
......@@ -7,6 +7,7 @@
-- unit name: fmc_adc_100Ms_core (fmc_adc_100Ms_core.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
-- Theodor Stana (t.stana@cern.ch)
--
-- date: 28-02-2011
--
......@@ -16,6 +17,9 @@
--
-- dependencies:
--
-- references:
-- [1] Xilinx UG175. FIFO Generator v6.2, July 23, 2010
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
......@@ -42,8 +46,14 @@ use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.genram_pkg.all;
entity fmc_adc_100Ms_core is
generic(
g_multishot_ram_size : natural := 2048
);
port (
-- Clock, reset
sys_clk_i : in std_logic;
......@@ -241,45 +251,6 @@ architecture rtl of fmc_adc_100Ms_core is
);
end component offset_gain_s;
component adc_sync_fifo
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(64 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(64 downto 0);
full : out std_logic;
empty : out std_logic;
valid : out std_logic
);
end component adc_sync_fifo;
component wb_ddr_fifo
port (
rst : in std_logic;
clk : in std_logic;
din : in std_logic_vector(64 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(64 downto 0);
full : out std_logic;
empty : out std_logic;
valid : out std_logic);
end component wb_ddr_fifo;
component multishot_dpram
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(12 downto 0);
dina : in std_logic_vector(63 downto 0);
clkb : in std_logic;
addrb : in std_logic_vector(12 downto 0);
doutb : out std_logic_vector(63 downto 0));
end component multishot_dpram;
component monostable
generic(
g_INPUT_POLARITY : std_logic := '1'; --! trigger_i polarity
......@@ -300,6 +271,7 @@ architecture rtl of fmc_adc_100Ms_core is
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_dpram_depth : integer := f_log2_size(g_multishot_ram_size);
------------------------------------------------------------------------------
-- Types declaration
......@@ -413,26 +385,24 @@ architecture rtl of fmc_adc_100Ms_core is
signal multishot_buffer_sel : std_logic;
-- Multi-shot mode
constant c_DPRAM_DEPTH : integer := 13;
signal dpram_addra_cnt : unsigned(c_DPRAM_DEPTH-1 downto 0);
signal dpram_addra_trig : unsigned(c_DPRAM_DEPTH-1 downto 0);
signal dpram_addra_post_done : unsigned(c_DPRAM_DEPTH-1 downto 0);
signal dpram_addrb_cnt : unsigned(c_DPRAM_DEPTH-1 downto 0);
signal dpram_addra_cnt : unsigned(c_dpram_depth-1 downto 0);
signal dpram_addra_trig : unsigned(c_dpram_depth-1 downto 0);
signal dpram_addra_post_done : unsigned(c_dpram_depth-1 downto 0);
signal dpram_addrb_cnt : unsigned(c_dpram_depth-1 downto 0);
signal dpram_dout : std_logic_vector(63 downto 0);
signal dpram_valid : std_logic;
signal dpram_valid_t : std_logic;
signal dpram0_dina : std_logic_vector(63 downto 0);
signal dpram0_addra : std_logic_vector(c_DPRAM_DEPTH-1 downto 0);
signal dpram0_addra : std_logic_vector(c_dpram_depth-1 downto 0);
signal dpram0_wea : std_logic;
signal dpram0_addrb : std_logic_vector(c_DPRAM_DEPTH-1 downto 0);
signal dpram0_addrb : std_logic_vector(c_dpram_depth-1 downto 0);
signal dpram0_doutb : std_logic_vector(63 downto 0);
signal dpram1_dina : std_logic_vector(63 downto 0);
signal dpram1_addra : std_logic_vector(c_DPRAM_DEPTH-1 downto 0);
signal dpram1_addra : std_logic_vector(c_dpram_depth-1 downto 0);
signal dpram1_wea : std_logic;
signal dpram1_addrb : std_logic_vector(c_DPRAM_DEPTH-1 downto 0);
signal dpram1_addrb : std_logic_vector(c_dpram_depth-1 downto 0);
signal dpram1_doutb : std_logic_vector(63 downto 0);
-- Wishbone to DDR flowcontrol FIFO
......@@ -906,20 +876,57 @@ begin
------------------------------------------------------------------------------
-- Synchronisation FIFO to system clock domain
------------------------------------------------------------------------------
cmp_adc_sync_fifo : adc_sync_fifo
cmp_adc_sync_fifo : generic_async_fifo
generic map (
g_data_width => 65,
g_size => 16,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
g_with_rd_almost_empty => false,
g_with_rd_almost_full => false,
g_with_rd_count => false,
g_with_wr_empty => false,
g_with_wr_full => true,
g_with_wr_almost_empty => false,
g_with_wr_almost_full => false,
g_with_wr_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => 0
)
port map(
rst => fs_rst, -- must be at least 3 wr_clk and rd_clk cycles
wr_clk => fs_clk,
rd_clk => sys_clk_i,
din => sync_fifo_din,
wr_en => sync_fifo_wr,
rd_en => sync_fifo_rd,
dout => sync_fifo_dout,
full => sync_fifo_full,
empty => sync_fifo_empty,
valid => sync_fifo_valid
rst_n_i => fs_rst_n,
clk_wr_i => fs_clk,
d_i => sync_fifo_din,
we_i => sync_fifo_wr,
wr_empty_o => open, -- sync_fifo_empty,
wr_full_o => sync_fifo_full,
wr_almost_empty_o => open,
wr_almost_full_o => open,
wr_count_o => open,
clk_rd_i => sys_clk_i,
q_o => sync_fifo_dout,
rd_i => sync_fifo_rd,
rd_empty_o => sync_fifo_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open
);
-- One clock cycle delay for the FIFO's VALID signal. Since the General Cores
-- package does not offer the possibility to use the FWFT feature of the FIFOs,
-- we simulate the valid flag here according to Figure 4-7 in ref. [1].
p_sync_fifo_valid : process (sys_clk_i) is
begin
if rising_edge(sys_clk_i) then
sync_fifo_valid <= sync_fifo_rd;
if (sync_fifo_empty = '1') then
sync_fifo_valid <= '0';
end if;
end if;
end process;
sync_fifo_din <= trig_align & data_calibr_out;
-- FOR DEBUG: FR instead of CH1 and SerDes Synced instead of CH2
--sync_fifo_din <= trig_align & serdes_out_data(63 downto 32) &
......@@ -944,7 +951,7 @@ begin
single_shot <= '0';
elsif rising_edge(sys_clk_i) then
if acq_start = '1' then
shots_cnt <= unsigned(shots_value);
shots_cnt <= unsigned(shots_value);
elsif shots_decr = '1' then
shots_cnt <= shots_cnt - 1;
end if;
......@@ -957,7 +964,7 @@ begin
end process p_shots_cnt;
multishot_buffer_sel <= std_logic(shots_cnt(0));
shots_done <= '1' when shots_cnt = to_unsigned(1, shots_cnt'length) else '0';
shots_done <= '1' when shots_cnt = to_unsigned(1, shots_cnt'length) else '0';
------------------------------------------------------------------------------
-- Pre-trigger counter
......@@ -983,13 +990,13 @@ begin
p_pre_trig_cnt : process (sys_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
pre_trig_cnt <= to_unsigned(1, pre_trig_cnt'length);
pre_trig_cnt <= to_unsigned(1, pre_trig_cnt'length);
elsif rising_edge(sys_clk_i) then
if (acq_start = '1' or pre_trig_done = '1') then
if unsigned(pre_trig_value) = to_unsigned(0, pre_trig_value'length) then
pre_trig_cnt <= (others => '0');
pre_trig_cnt <= (others => '0');
else
pre_trig_cnt <= unsigned(pre_trig_value) - 1;
pre_trig_cnt <= unsigned(pre_trig_value) - 1;
end if;
elsif (acq_in_pre_trig = '1' and sync_fifo_valid = '1') then
pre_trig_cnt <= pre_trig_cnt - 1;
......@@ -1025,13 +1032,13 @@ begin
p_post_trig_cnt : process (sys_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
post_trig_cnt <= to_unsigned(1, post_trig_cnt'length);
post_trig_cnt <= to_unsigned(1, post_trig_cnt'length);
elsif rising_edge(sys_clk_i) then
if (acq_start = '1' or post_trig_done = '1') then
if unsigned(post_trig_value) = to_unsigned(0, post_trig_value'length) then
post_trig_cnt <= (others => '0');
post_trig_cnt <= (others => '0');
else
post_trig_cnt <= unsigned(post_trig_value) - 1;
post_trig_cnt <= unsigned(post_trig_value) - 1;
end if;
elsif (acq_in_post_trig = '1' and sync_fifo_valid = '1') then
post_trig_cnt <= post_trig_cnt - 1;
......@@ -1048,7 +1055,7 @@ begin
p_samples_cnt : process (sys_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
samples_cnt <= (others => '0');
samples_cnt <= (others => '0');
elsif rising_edge(sys_clk_i) then
if (acq_start = '1') then
samples_cnt <= (others => '0');
......@@ -1242,26 +1249,56 @@ begin
dpram1_wea <= (samples_wr_en and sync_fifo_valid) when multishot_buffer_sel = '1' else '0';
-- DPRAMs
cmp_multishot_dpram0 : multishot_dpram
port map(
clka => sys_clk_i,
wea(0) => dpram0_wea,
addra => dpram0_addra,
dina => dpram0_dina,
clkb => sys_clk_i,
addrb => dpram0_addrb,
doutb => dpram0_doutb
cmp_multishot_dpram0 : generic_dpram
generic map
(
g_data_width => 64,
g_size => g_multishot_ram_size,
g_with_byte_enable => false,
g_addr_conflict_resolution => "read_first",
g_dual_clock => true
-- default values for the rest of the generics are okay
)
port map
(
rst_n_i => sys_rst_n_i,
clka_i => sys_clk_i,
bwea_i => open,
wea_i => dpram0_wea,
aa_i => dpram0_addra,
da_i => dpram0_dina,
qa_o => open,
clkb_i => sys_clk_i,
bweb_i => open,
ab_i => dpram0_addrb,
-- db_i => (others => '0'),
qb_o => dpram0_doutb
);
cmp_multishot_dpram1 : multishot_dpram
port map(
clka => sys_clk_i,
wea(0) => dpram1_wea,
addra => dpram1_addra,
dina => dpram1_dina,
clkb => sys_clk_i,
addrb => dpram1_addrb,
doutb => dpram1_doutb
cmp_multishot_dpram1 : generic_dpram
generic map
(
g_data_width => 64,
g_size => g_multishot_ram_size,
g_with_byte_enable => false,
g_addr_conflict_resolution => "read_first",
g_dual_clock => false
-- default values for the rest of the generics are okay
)
port map
(
rst_n_i => sys_rst_n_i,
clka_i => sys_clk_i,
bwea_i => open,
wea_i => dpram1_wea,
aa_i => dpram1_addra,
da_i => dpram1_dina,
qa_o => open,
clkb_i => sys_clk_i,
bweb_i => open,
ab_i => dpram1_addrb,
-- db_i => (others => '0'),
qb_o => dpram1_doutb
);
-- DPRAM output address counter
......@@ -1273,7 +1310,7 @@ begin
dpram_valid <= '0';
elsif rising_edge(sys_clk_i) then
if post_trig_done = '1' then
dpram_addrb_cnt <= dpram_addra_trig - unsigned(pre_trig_value(c_DPRAM_DEPTH-1 downto 0)) + 1;
dpram_addrb_cnt <= dpram_addra_trig - unsigned(pre_trig_value(c_dpram_depth-1 downto 0)) + 1;
dpram_valid_t <= '1';
elsif (dpram_addrb_cnt = dpram_addra_post_done) then
dpram_valid_t <= '0';
......@@ -1292,19 +1329,46 @@ begin
------------------------------------------------------------------------------
-- Flow control FIFO for data to DDR
------------------------------------------------------------------------------
cmp_wb_ddr_fifo : wb_ddr_fifo
cmp_wb_ddr_fifo : generic_sync_fifo
generic map (
g_data_width => 65,
g_size => 64,
g_show_ahead => false,
g_with_empty => true,
g_with_full => true,
g_with_almost_empty => false,
g_with_almost_full => false,
g_with_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => 0
)
port map(
rst => sys_rst, -- must be at least 3 wr_clk and rd_clk cycles
clk => sys_clk_i,
din => wb_ddr_fifo_din,
wr_en => wb_ddr_fifo_wr,
rd_en => wb_ddr_fifo_rd,
dout => wb_ddr_fifo_dout,
full => wb_ddr_fifo_full,
empty => wb_ddr_fifo_empty,
valid => wb_ddr_fifo_valid
rst_n_i => sys_rst_n_i,
clk_i => sys_clk_i,
d_i => wb_ddr_fifo_din,
we_i => wb_ddr_fifo_wr,
q_o => wb_ddr_fifo_dout,
rd_i => wb_ddr_fifo_rd,
empty_o => wb_ddr_fifo_empty,
full_o => wb_ddr_fifo_full,
almost_empty_o => open,
almost_full_o => open,
count_o => open
);
-- One clock cycle delay for the FIFO's VALID signal. Since the General Cores
-- package does not offer the possibility to use the FWFT feature of the FIFOs,
-- we simulate the valid flag here according to Figure 4-7 in ref. [1].
p_wb_ddr_fifo_valid : process (sys_clk_i) is
begin
if rising_edge(sys_clk_i) then
wb_ddr_fifo_valid <= wb_ddr_fifo_rd;
if (wb_ddr_fifo_empty = '1') then
wb_ddr_fifo_valid <= '0';
end if;
end if;
end process;
p_wb_ddr_fifo_input : process (sys_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
......
hdl/adc/rtl/fmc_adc_100Ms_core_pkg.vhd 0 → 100644
View file @ 2f92c67d
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity for Simple PCIe FMC Carrier
-- http://www.ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: fmc_adc_100Ms_core_pkg (fmc_adc_100Ms_core_pkg.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 16-11-2012
--
-- version: 1.0
--
-- description: Package for FMC ADC 100Ms/s core
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package fmc_adc_100Ms_core_pkg is
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component fmc_adc_100Ms_core
generic(
g_multishot_ram_size : natural := 2048
);
port (
-- Clock, reset
sys_clk_i : in std_logic;
sys_rst_n_i : in std_logic;
-- CSR wishbone interface
wb_csr_adr_i : in std_logic_vector(4 downto 0);
wb_csr_dat_i : in std_logic_vector(31 downto 0);
wb_csr_dat_o : out std_logic_vector(31 downto 0);
wb_csr_cyc_i : in std_logic;
wb_csr_sel_i : in std_logic_vector(3 downto 0);
wb_csr_stb_i : in std_logic;
wb_csr_we_i : in std_logic;
wb_csr_ack_o : out std_logic;
-- DDR wishbone interface
wb_ddr_clk_i : in std_logic;
wb_ddr_adr_o : out std_logic_vector(31 downto 0);
wb_ddr_dat_o : out std_logic_vector(63 downto 0);
wb_ddr_sel_o : out std_logic_vector(7 downto 0);
wb_ddr_stb_o : out std_logic;
wb_ddr_we_o : out std_logic;
wb_ddr_cyc_o : out std_logic;
wb_ddr_ack_i : in std_logic;
wb_ddr_stall_i : in std_logic;
-- Events output pulses
trigger_p_o : out std_logic;
acq_start_p_o : out std_logic;
acq_stop_p_o : out std_logic;
acq_end_p_o : out std_logic;
-- FMC interface
ext_trigger_p_i : in std_logic; -- External trigger
ext_trigger_n_i : in std_logic;
adc_dco_p_i : in std_logic; -- ADC data clock
adc_dco_n_i : in std_logic;
adc_fr_p_i : in std_logic; -- ADC frame start
adc_fr_n_i : in std_logic;
adc_outa_p_i : in std_logic_vector(3 downto 0); -- ADC serial data (odd bits)
adc_outa_n_i : in std_logic_vector(3 downto 0);
adc_outb_p_i : in std_logic_vector(3 downto 0); -- ADC serial data (even bits)
adc_outb_n_i : in std_logic_vector(3 downto 0);
gpio_dac_clr_n_o : out std_logic; -- offset DACs clear (active low)
gpio_led_acq_o : out std_logic; -- Mezzanine front panel power LED (PWR)
gpio_led_trig_o : out std_logic; -- Mezzanine front panel trigger LED (TRIG)
gpio_ssr_ch1_o : out std_logic_vector(6 downto 0); -- Channel 1 solid state relays control
gpio_ssr_ch2_o : out std_logic_vector(6 downto 0); -- Channel 2 solid state relays control
gpio_ssr_ch3_o : out std_logic_vector(6 downto 0); -- Channel 3 solid state relays control
gpio_ssr_ch4_o : out std_logic_vector(6 downto 0); -- Channel 4 solid state relays control
gpio_si570_oe_o : out std_logic -- Si570 (programmable oscillator) output enable
);
end component fmc_adc_100Ms_core;
end fmc_adc_100Ms_core_pkg;
package body fmc_adc_100Ms_core_pkg is
end fmc_adc_100Ms_core_pkg;
hdl/spec/chipscope/gn4124_dma_wb_sdb_hang.cdc 0 → 100644
View file @ 2f92c67d
#ChipScope Core Inserter Project File Version 3.0
#Fri Mar 01 10:34:52 CET 2013
Project.device.designInputFile=/home/mcattin/projects/svn_to_git/fmc-adc-100m14b4cha_git/hdl/spec/syn/spec_top_fmc_adc_100Ms.ngc
Project.device.designOutputFile=/home/mcattin/projects/svn_to_git/fmc-adc-100m14b4cha_git/hdl/spec/syn/spec_top_fmc_adc_100Ms.ngc
Project.device.deviceFamily=18
Project.device.enableRPMs=true
Project.device.outputDirectory=/home/mcattin/projects/svn_to_git/fmc-adc-100m14b4cha_git/hdl/spec/syn/_ngo
Project.device.useSRL16=true
Project.filter.dimension=19
Project.filter<0>=*_stall_*
Project.filter<10>=cmp_gn**
Project.filter<11>=*irq*
Project.filter<12>=cmp_gn4124_core/cmp_dma_contr*
Project.filter<13>=cmp_gn4124_core/*dma*
Project.filter<14>=cmp_gn4124_core/*arb*
Project.filter<15>=cmp_gn4124_core/cmp_p2l_decode32*
Project.filter<16>=cmp_gn4124_core/*tx*
Project.filter<17>=cmp_gn4124_core/*rdy*
Project.filter<18>=cmp_gn4124_core/*rx*err*
Project.filter<1>=*_cmd_*
Project.filter<2>=*cmp_ddr_ctrl/p1_*
Project.filter<3>=*sys*clk*
Project.filter<4>=*clk*
Project.filter<5>=**
Project.filter<6>=*wb_dma_*
Project.filter<7>=cmp_gn4124_core/cmp_dma_controller*reg*
Project.filter<8>=cmp_gn4124_core/cmp_dma_controller**
Project.filter<9>=cmp_gn4124_core/**
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=sys_clk_125
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=wb_dma_adr<25>
Project.unit<0>.dataChannel<100>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<23>
Project.unit<0>.dataChannel<101>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<24>
Project.unit<0>.dataChannel<102>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<25>
Project.unit<0>.dataChannel<103>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<26>
Project.unit<0>.dataChannel<104>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<27>
Project.unit<0>.dataChannel<105>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_instr
Project.unit<0>.dataChannel<10>=wb_dma_adr<15>
Project.unit<0>.dataChannel<11>=wb_dma_adr<14>
Project.unit<0>.dataChannel<12>=wb_dma_adr<13>
Project.unit<0>.dataChannel<13>=wb_dma_adr<12>
Project.unit<0>.dataChannel<14>=wb_dma_adr<11>
Project.unit<0>.dataChannel<15>=wb_dma_adr<10>
Project.unit<0>.dataChannel<16>=wb_dma_adr<9>
Project.unit<0>.dataChannel<17>=wb_dma_adr<8>
Project.unit<0>.dataChannel<18>=wb_dma_adr<7>
Project.unit<0>.dataChannel<19>=wb_dma_adr<6>
Project.unit<0>.dataChannel<1>=wb_dma_adr<24>
Project.unit<0>.dataChannel<20>=wb_dma_adr<5>
Project.unit<0>.dataChannel<21>=wb_dma_adr<4>
Project.unit<0>.dataChannel<22>=wb_dma_adr<3>
Project.unit<0>.dataChannel<23>=wb_dma_adr<2>
Project.unit<0>.dataChannel<24>=wb_dma_adr<1>
Project.unit<0>.dataChannel<25>=wb_dma_adr<0>
Project.unit<0>.dataChannel<26>=wb_dma_dat_o<31>
Project.unit<0>.dataChannel<27>=wb_dma_dat_o<30>
Project.unit<0>.dataChannel<28>=wb_dma_dat_o<29>
Project.unit<0>.dataChannel<29>=wb_dma_dat_o<28>
Project.unit<0>.dataChannel<2>=wb_dma_adr<23>
Project.unit<0>.dataChannel<30>=wb_dma_dat_o<27>
Project.unit<0>.dataChannel<31>=wb_dma_dat_o<26>
Project.unit<0>.dataChannel<32>=wb_dma_dat_o<25>
Project.unit<0>.dataChannel<33>=wb_dma_dat_o<24>
Project.unit<0>.dataChannel<34>=wb_dma_dat_o<23>
Project.unit<0>.dataChannel<35>=wb_dma_dat_o<22>
Project.unit<0>.dataChannel<36>=wb_dma_dat_o<21>
Project.unit<0>.dataChannel<37>=wb_dma_dat_o<20>
Project.unit<0>.dataChannel<38>=wb_dma_dat_o<19>
Project.unit<0>.dataChannel<39>=wb_dma_dat_o<18>
Project.unit<0>.dataChannel<3>=wb_dma_adr<22>
Project.unit<0>.dataChannel<40>=wb_dma_dat_o<17>
Project.unit<0>.dataChannel<41>=wb_dma_dat_o<16>
Project.unit<0>.dataChannel<42>=wb_dma_dat_o<15>
Project.unit<0>.dataChannel<43>=wb_dma_dat_o<14>
Project.unit<0>.dataChannel<44>=wb_dma_dat_o<13>
Project.unit<0>.dataChannel<45>=wb_dma_dat_o<12>
Project.unit<0>.dataChannel<46>=wb_dma_dat_o<11>
Project.unit<0>.dataChannel<47>=wb_dma_dat_o<10>
Project.unit<0>.dataChannel<48>=wb_dma_dat_o<9>
Project.unit<0>.dataChannel<49>=wb_dma_dat_o<8>
Project.unit<0>.dataChannel<4>=wb_dma_adr<21>
Project.unit<0>.dataChannel<50>=wb_dma_dat_o<7>
Project.unit<0>.dataChannel<51>=wb_dma_dat_o<6>
Project.unit<0>.dataChannel<52>=wb_dma_dat_o<5>
Project.unit<0>.dataChannel<53>=wb_dma_dat_o<4>
Project.unit<0>.dataChannel<54>=wb_dma_dat_o<3>
Project.unit<0>.dataChannel<55>=wb_dma_dat_o<2>
Project.unit<0>.dataChannel<56>=wb_dma_dat_o<1>
Project.unit<0>.dataChannel<57>=wb_dma_dat_o<0>
Project.unit<0>.dataChannel<58>=wb_dma_stb
Project.unit<0>.dataChannel<59>=wb_dma_we
Project.unit<0>.dataChannel<5>=wb_dma_adr<20>
Project.unit<0>.dataChannel<60>=wb_dma_cyc
Project.unit<0>.dataChannel<61>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_stall_o
Project.unit<0>.dataChannel<62>=cmp_ddr_ctrl/p1_rd_full
Project.unit<0>.dataChannel<63>=cmp_ddr_ctrl/p1_wr_full
Project.unit<0>.dataChannel<64>=cmp_ddr_ctrl/p1_cmd_full
Project.unit<0>.dataChannel<65>=cmp_ddr_ctrl/p1_rd_empty
Project.unit<0>.dataChannel<66>=cmp_ddr_ctrl/p1_rd_en
Project.unit<0>.dataChannel<67>=cmp_ddr_ctrl/p1_rd_count<1>
Project.unit<0>.dataChannel<68>=cmp_ddr_ctrl/p1_rd_count<2>
Project.unit<0>.dataChannel<69>=cmp_ddr_ctrl/p1_rd_count<3>
Project.unit<0>.dataChannel<6>=wb_dma_adr<19>
Project.unit<0>.dataChannel<70>=cmp_ddr_ctrl/p1_rd_count<4>
Project.unit<0>.dataChannel<71>=cmp_ddr_ctrl/p1_rd_count<5>
Project.unit<0>.dataChannel<72>=cmp_ddr_ctrl/p1_rd_count<6>
Project.unit<0>.dataChannel<73>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_en
Project.unit<0>.dataChannel<74>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_bl<0>
Project.unit<0>.dataChannel<75>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_bl<1>
Project.unit<0>.dataChannel<76>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_bl<2>
Project.unit<0>.dataChannel<77>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_bl<3>
Project.unit<0>.dataChannel<78>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_bl<4>
Project.unit<0>.dataChannel<79>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<2>
Project.unit<0>.dataChannel<7>=wb_dma_adr<18>
Project.unit<0>.dataChannel<80>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<3>
Project.unit<0>.dataChannel<81>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<4>
Project.unit<0>.dataChannel<82>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<5>
Project.unit<0>.dataChannel<83>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<6>
Project.unit<0>.dataChannel<84>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<7>
Project.unit<0>.dataChannel<85>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<8>
Project.unit<0>.dataChannel<86>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<9>
Project.unit<0>.dataChannel<87>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<10>
Project.unit<0>.dataChannel<88>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<11>
Project.unit<0>.dataChannel<89>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<12>
Project.unit<0>.dataChannel<8>=wb_dma_adr<17>
Project.unit<0>.dataChannel<90>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<13>
Project.unit<0>.dataChannel<91>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<14>
Project.unit<0>.dataChannel<92>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<15>
Project.unit<0>.dataChannel<93>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<16>
Project.unit<0>.dataChannel<94>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<17>
Project.unit<0>.dataChannel<95>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<18>
Project.unit<0>.dataChannel<96>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<19>
Project.unit<0>.dataChannel<97>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<20>
Project.unit<0>.dataChannel<98>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<21>
Project.unit<0>.dataChannel<99>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<22>
Project.unit<0>.dataChannel<9>=wb_dma_adr<16>
Project.unit<0>.dataDepth=4096
Project.unit<0>.dataEqualsTrigger=true
Project.unit<0>.dataPortWidth=106
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=wb_dma_adr<25>
Project.unit<0>.triggerChannel<0><100>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<23>
Project.unit<0>.triggerChannel<0><101>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<24>
Project.unit<0>.triggerChannel<0><102>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<25>
Project.unit<0>.triggerChannel<0><103>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<26>
Project.unit<0>.triggerChannel<0><104>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<27>
Project.unit<0>.triggerChannel<0><105>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_instr
Project.unit<0>.triggerChannel<0><10>=wb_dma_adr<15>
Project.unit<0>.triggerChannel<0><11>=wb_dma_adr<14>
Project.unit<0>.triggerChannel<0><12>=wb_dma_adr<13>
Project.unit<0>.triggerChannel<0><13>=wb_dma_adr<12>
Project.unit<0>.triggerChannel<0><14>=wb_dma_adr<11>
Project.unit<0>.triggerChannel<0><15>=wb_dma_adr<10>
Project.unit<0>.triggerChannel<0><16>=wb_dma_adr<9>
Project.unit<0>.triggerChannel<0><17>=wb_dma_adr<8>
Project.unit<0>.triggerChannel<0><18>=wb_dma_adr<7>
Project.unit<0>.triggerChannel<0><19>=wb_dma_adr<6>
Project.unit<0>.triggerChannel<0><1>=wb_dma_adr<24>
Project.unit<0>.triggerChannel<0><20>=wb_dma_adr<5>
Project.unit<0>.triggerChannel<0><21>=wb_dma_adr<4>
Project.unit<0>.triggerChannel<0><22>=wb_dma_adr<3>
Project.unit<0>.triggerChannel<0><23>=wb_dma_adr<2>
Project.unit<0>.triggerChannel<0><24>=wb_dma_adr<1>
Project.unit<0>.triggerChannel<0><25>=wb_dma_adr<0>
Project.unit<0>.triggerChannel<0><26>=wb_dma_dat_o<31>
Project.unit<0>.triggerChannel<0><27>=wb_dma_dat_o<30>
Project.unit<0>.triggerChannel<0><28>=wb_dma_dat_o<29>
Project.unit<0>.triggerChannel<0><29>=wb_dma_dat_o<28>
Project.unit<0>.triggerChannel<0><2>=wb_dma_adr<23>
Project.unit<0>.triggerChannel<0><30>=wb_dma_dat_o<27>
Project.unit<0>.triggerChannel<0><31>=wb_dma_dat_o<26>
Project.unit<0>.triggerChannel<0><32>=wb_dma_dat_o<25>
Project.unit<0>.triggerChannel<0><33>=wb_dma_dat_o<24>
Project.unit<0>.triggerChannel<0><34>=wb_dma_dat_o<23>
Project.unit<0>.triggerChannel<0><35>=wb_dma_dat_o<22>
Project.unit<0>.triggerChannel<0><36>=wb_dma_dat_o<21>
Project.unit<0>.triggerChannel<0><37>=wb_dma_dat_o<20>
Project.unit<0>.triggerChannel<0><38>=wb_dma_dat_o<19>
Project.unit<0>.triggerChannel<0><39>=wb_dma_dat_o<18>
Project.unit<0>.triggerChannel<0><3>=wb_dma_adr<22>
Project.unit<0>.triggerChannel<0><40>=wb_dma_dat_o<17>
Project.unit<0>.triggerChannel<0><41>=wb_dma_dat_o<16>
Project.unit<0>.triggerChannel<0><42>=wb_dma_dat_o<15>
Project.unit<0>.triggerChannel<0><43>=wb_dma_dat_o<14>
Project.unit<0>.triggerChannel<0><44>=wb_dma_dat_o<13>
Project.unit<0>.triggerChannel<0><45>=wb_dma_dat_o<12>
Project.unit<0>.triggerChannel<0><46>=wb_dma_dat_o<11>
Project.unit<0>.triggerChannel<0><47>=wb_dma_dat_o<10>
Project.unit<0>.triggerChannel<0><48>=wb_dma_dat_o<9>
Project.unit<0>.triggerChannel<0><49>=wb_dma_dat_o<8>
Project.unit<0>.triggerChannel<0><4>=wb_dma_adr<21>
Project.unit<0>.triggerChannel<0><50>=wb_dma_dat_o<7>
Project.unit<0>.triggerChannel<0><51>=wb_dma_dat_o<6>
Project.unit<0>.triggerChannel<0><52>=wb_dma_dat_o<5>
Project.unit<0>.triggerChannel<0><53>=wb_dma_dat_o<4>
Project.unit<0>.triggerChannel<0><54>=wb_dma_dat_o<3>
Project.unit<0>.triggerChannel<0><55>=wb_dma_dat_o<2>
Project.unit<0>.triggerChannel<0><56>=wb_dma_dat_o<1>
Project.unit<0>.triggerChannel<0><57>=wb_dma_dat_o<0>
Project.unit<0>.triggerChannel<0><58>=wb_dma_stb
Project.unit<0>.triggerChannel<0><59>=wb_dma_we
Project.unit<0>.triggerChannel<0><5>=wb_dma_adr<20>
Project.unit<0>.triggerChannel<0><60>=wb_dma_cyc
Project.unit<0>.triggerChannel<0><61>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_stall_o
Project.unit<0>.triggerChannel<0><62>=cmp_ddr_ctrl/p1_rd_full
Project.unit<0>.triggerChannel<0><63>=cmp_ddr_ctrl/p1_wr_full
Project.unit<0>.triggerChannel<0><64>=cmp_ddr_ctrl/p1_cmd_full
Project.unit<0>.triggerChannel<0><65>=cmp_ddr_ctrl/p1_rd_empty
Project.unit<0>.triggerChannel<0><66>=cmp_ddr_ctrl/p1_rd_en
Project.unit<0>.triggerChannel<0><67>=cmp_ddr_ctrl/p1_rd_count<1>
Project.unit<0>.triggerChannel<0><68>=cmp_ddr_ctrl/p1_rd_count<2>
Project.unit<0>.triggerChannel<0><69>=cmp_ddr_ctrl/p1_rd_count<3>
Project.unit<0>.triggerChannel<0><6>=wb_dma_adr<19>
Project.unit<0>.triggerChannel<0><70>=cmp_ddr_ctrl/p1_rd_count<4>
Project.unit<0>.triggerChannel<0><71>=cmp_ddr_ctrl/p1_rd_count<5>
Project.unit<0>.triggerChannel<0><72>=cmp_ddr_ctrl/p1_rd_count<6>
Project.unit<0>.triggerChannel<0><73>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_en
Project.unit<0>.triggerChannel<0><74>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_bl<0>
Project.unit<0>.triggerChannel<0><75>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_bl<1>
Project.unit<0>.triggerChannel<0><76>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_bl<2>
Project.unit<0>.triggerChannel<0><77>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_bl<3>
Project.unit<0>.triggerChannel<0><78>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_bl<4>
Project.unit<0>.triggerChannel<0><79>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<2>
Project.unit<0>.triggerChannel<0><7>=wb_dma_adr<18>
Project.unit<0>.triggerChannel<0><80>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<3>
Project.unit<0>.triggerChannel<0><81>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<4>
Project.unit<0>.triggerChannel<0><82>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<5>
Project.unit<0>.triggerChannel<0><83>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<6>
Project.unit<0>.triggerChannel<0><84>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<7>
Project.unit<0>.triggerChannel<0><85>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<8>
Project.unit<0>.triggerChannel<0><86>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<9>
Project.unit<0>.triggerChannel<0><87>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<10>
Project.unit<0>.triggerChannel<0><88>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<11>
Project.unit<0>.triggerChannel<0><89>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<12>
Project.unit<0>.triggerChannel<0><8>=wb_dma_adr<17>
Project.unit<0>.triggerChannel<0><90>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<13>
Project.unit<0>.triggerChannel<0><91>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<14>
Project.unit<0>.triggerChannel<0><92>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<15>
Project.unit<0>.triggerChannel<0><93>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<16>
Project.unit<0>.triggerChannel<0><94>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<17>
Project.unit<0>.triggerChannel<0><95>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<18>
Project.unit<0>.triggerChannel<0><96>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<19>
Project.unit<0>.triggerChannel<0><97>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<20>
Project.unit<0>.triggerChannel<0><98>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<21>
Project.unit<0>.triggerChannel<0><99>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr<22>
Project.unit<0>.triggerChannel<0><9>=wb_dma_adr<16>
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=2
Project.unit<0>.triggerMatchCountWidth<0><0>=3
Project.unit<0>.triggerMatchCountWidth<0><1>=3
Project.unit<0>.triggerMatchType<0><0>=5
Project.unit<0>.triggerMatchType<0><1>=5
Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortWidth<0>=106
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro
hdl/spec/chipscope/gn4124_local_bus_sdb_hang.cdc 0 → 100644
View file @ 2f92c67d
#ChipScope Core Inserter Project File Version 3.0
#Tue Mar 05 10:23:57 CET 2013
Project.device.designInputFile=/home/mcattin/projects/svn_to_git/fmc-adc-100m14b4cha_git/hdl/spec/syn/spec_top_fmc_adc_100Ms.ngc
Project.device.designOutputFile=/home/mcattin/projects/svn_to_git/fmc-adc-100m14b4cha_git/hdl/spec/syn/spec_top_fmc_adc_100Ms.ngc
Project.device.deviceFamily=18
Project.device.enableRPMs=true
Project.device.outputDirectory=/home/mcattin/projects/svn_to_git/fmc-adc-100m14b4cha_git/hdl/spec/syn/_ngo
Project.device.useSRL16=true
Project.filter.dimension=19
Project.filter<0>=*l2p_last_*
Project.filter<10>=*cmp_l2p_*dma_adr*
Project.filter<11>=*cmp_l2p_*wb*cnt*
Project.filter<12>=*cmp_l2p_*wb*cnt
Project.filter<13>=*clk*
Project.filter<14>=*cmp_l2p_dma*l2p_dma_adr*
Project.filter<15>=*cmp_l2p_dma*l2p_dma_s*
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Project.unit<0>.triggerChannel<0><3>=cmp_gn4124_core/p_rd_d_rdy<1>
Project.unit<0>.triggerChannel<0><40>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<2>
Project.unit<0>.triggerChannel<0><41>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<3>
Project.unit<0>.triggerChannel<0><42>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<4>
Project.unit<0>.triggerChannel<0><43>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<5>
Project.unit<0>.triggerChannel<0><44>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<6>
Project.unit<0>.triggerChannel<0><45>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<7>
Project.unit<0>.triggerChannel<0><46>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<8>
Project.unit<0>.triggerChannel<0><47>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<9>
Project.unit<0>.triggerChannel<0><48>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<10>
Project.unit<0>.triggerChannel<0><49>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_last_packet
Project.unit<0>.triggerChannel<0><4>=cmp_gn4124_core/l_wr_rdy<0>
Project.unit<0>.triggerChannel<0><50>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_header<0>
Project.unit<0>.triggerChannel<0><51>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_header<1>
Project.unit<0>.triggerChannel<0><52>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_header<2>
Project.unit<0>.triggerChannel<0><53>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_header<3>
Project.unit<0>.triggerChannel<0><54>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_header<4>
Project.unit<0>.triggerChannel<0><55>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_header<5>
Project.unit<0>.triggerChannel<0><56>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_header<6>
Project.unit<0>.triggerChannel<0><57>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_header<7>
Project.unit<0>.triggerChannel<0><58>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_header<8>
Project.unit<0>.triggerChannel<0><59>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_header<9>
Project.unit<0>.triggerChannel<0><5>=cmp_gn4124_core/l_wr_rdy<1>
Project.unit<0>.triggerChannel<0><60>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<0>
Project.unit<0>.triggerChannel<0><61>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<1>
Project.unit<0>.triggerChannel<0><62>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<2>
Project.unit<0>.triggerChannel<0><63>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<3>
Project.unit<0>.triggerChannel<0><64>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<4>
Project.unit<0>.triggerChannel<0><65>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<5>
Project.unit<0>.triggerChannel<0><66>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<6>
Project.unit<0>.triggerChannel<0><67>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<7>
Project.unit<0>.triggerChannel<0><68>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<8>
Project.unit<0>.triggerChannel<0><69>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<9>
Project.unit<0>.triggerChannel<0><6>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ldm_gnt
Project.unit<0>.triggerChannel<0><70>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<10>
Project.unit<0>.triggerChannel<0><71>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<11>
Project.unit<0>.triggerChannel<0><72>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<12>
Project.unit<0>.triggerChannel<0><73>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<13>
Project.unit<0>.triggerChannel<0><74>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<14>
Project.unit<0>.triggerChannel<0><75>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<15>
Project.unit<0>.triggerChannel<0><76>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<16>
Project.unit<0>.triggerChannel<0><77>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<17>
Project.unit<0>.triggerChannel<0><78>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<18>
Project.unit<0>.triggerChannel<0><79>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<19>
Project.unit<0>.triggerChannel<0><7>=cmp_gn4124_core/cmp_l2p_arbiter/arb_pdm_gnt
Project.unit<0>.triggerChannel<0><80>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<20>
Project.unit<0>.triggerChannel<0><81>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<21>
Project.unit<0>.triggerChannel<0><82>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<22>
Project.unit<0>.triggerChannel<0><83>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<23>
Project.unit<0>.triggerChannel<0><84>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<24>
Project.unit<0>.triggerChannel<0><85>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<25>
Project.unit<0>.triggerChannel<0><86>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<26>
Project.unit<0>.triggerChannel<0><87>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<27>
Project.unit<0>.triggerChannel<0><88>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<28>
Project.unit<0>.triggerChannel<0><89>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<29>
Project.unit<0>.triggerChannel<0><8>=cmp_gn4124_core/cmp_l2p_arbiter/arb_wbm_gnt
Project.unit<0>.triggerChannel<0><90>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<30>
Project.unit<0>.triggerChannel<0><91>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<31>
Project.unit<0>.triggerChannel<0><92>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_req_o
Project.unit<0>.triggerChannel<0><93>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_dframe_o
Project.unit<0>.triggerChannel<0><94>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_valid_o
Project.unit<0>.triggerChannel<0><95>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<0>
Project.unit<0>.triggerChannel<0><96>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<1>
Project.unit<0>.triggerChannel<0><97>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<2>
Project.unit<0>.triggerChannel<0><98>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<3>
Project.unit<0>.triggerChannel<0><99>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<4>
Project.unit<0>.triggerChannel<0><9>=cmp_gn4124_core/tx_error
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchCountWidth<0><1>=0
Project.unit<0>.triggerMatchType<0><0>=5
Project.unit<0>.triggerMatchType<0><1>=5
Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortWidth<0>=127
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro
Project.unit<1>.clockChannel=sys_clk_125
Project.unit<1>.clockEdge=Rising
Project.unit<1>.dataDepth=2048
Project.unit<1>.dataEqualsTrigger=true
Project.unit<1>.dataPortWidth=90
Project.unit<1>.enableGaps=false
Project.unit<1>.enableStorageQualification=true
Project.unit<1>.enableTimestamps=false
Project.unit<1>.timestampDepth=0
Project.unit<1>.timestampWidth=0
Project.unit<1>.triggerChannel<0><0>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<0>
Project.unit<1>.triggerChannel<0><100>=
Project.unit<1>.triggerChannel<0><101>=
Project.unit<1>.triggerChannel<0><102>=
Project.unit<1>.triggerChannel<0><103>=
Project.unit<1>.triggerChannel<0><104>=
Project.unit<1>.triggerChannel<0><105>=
Project.unit<1>.triggerChannel<0><106>=
Project.unit<1>.triggerChannel<0><107>=
Project.unit<1>.triggerChannel<0><108>=
Project.unit<1>.triggerChannel<0><109>=
Project.unit<1>.triggerChannel<0><10>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<10>
Project.unit<1>.triggerChannel<0><110>=
Project.unit<1>.triggerChannel<0><111>=
Project.unit<1>.triggerChannel<0><112>=
Project.unit<1>.triggerChannel<0><113>=
Project.unit<1>.triggerChannel<0><114>=
Project.unit<1>.triggerChannel<0><115>=
Project.unit<1>.triggerChannel<0><116>=
Project.unit<1>.triggerChannel<0><117>=
Project.unit<1>.triggerChannel<0><118>=
Project.unit<1>.triggerChannel<0><119>=
Project.unit<1>.triggerChannel<0><11>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<11>
Project.unit<1>.triggerChannel<0><120>=
Project.unit<1>.triggerChannel<0><121>=
Project.unit<1>.triggerChannel<0><122>=
Project.unit<1>.triggerChannel<0><123>=
Project.unit<1>.triggerChannel<0><124>=
Project.unit<1>.triggerChannel<0><125>=
Project.unit<1>.triggerChannel<0><126>=
Project.unit<1>.triggerChannel<0><127>=
Project.unit<1>.triggerChannel<0><128>=
Project.unit<1>.triggerChannel<0><129>=
Project.unit<1>.triggerChannel<0><12>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<0>
Project.unit<1>.triggerChannel<0><130>=
Project.unit<1>.triggerChannel<0><131>=
Project.unit<1>.triggerChannel<0><132>=
Project.unit<1>.triggerChannel<0><133>=
Project.unit<1>.triggerChannel<0><134>=
Project.unit<1>.triggerChannel<0><135>=
Project.unit<1>.triggerChannel<0><136>=
Project.unit<1>.triggerChannel<0><137>=
Project.unit<1>.triggerChannel<0><138>=
Project.unit<1>.triggerChannel<0><139>=
Project.unit<1>.triggerChannel<0><13>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<1>
Project.unit<1>.triggerChannel<0><140>=
Project.unit<1>.triggerChannel<0><141>=
Project.unit<1>.triggerChannel<0><142>=
Project.unit<1>.triggerChannel<0><143>=
Project.unit<1>.triggerChannel<0><144>=
Project.unit<1>.triggerChannel<0><145>=
Project.unit<1>.triggerChannel<0><146>=
Project.unit<1>.triggerChannel<0><147>=
Project.unit<1>.triggerChannel<0><148>=
Project.unit<1>.triggerChannel<0><149>=
Project.unit<1>.triggerChannel<0><14>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<2>
Project.unit<1>.triggerChannel<0><15>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<3>
Project.unit<1>.triggerChannel<0><16>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<4>
Project.unit<1>.triggerChannel<0><17>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<5>
Project.unit<1>.triggerChannel<0><18>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<6>
Project.unit<1>.triggerChannel<0><19>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<7>
Project.unit<1>.triggerChannel<0><1>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<1>
Project.unit<1>.triggerChannel<0><20>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<8>
Project.unit<1>.triggerChannel<0><21>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<9>
Project.unit<1>.triggerChannel<0><22>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<10>
Project.unit<1>.triggerChannel<0><23>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<11>
Project.unit<1>.triggerChannel<0><24>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<0>
Project.unit<1>.triggerChannel<0><25>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<1>
Project.unit<1>.triggerChannel<0><26>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<2>
Project.unit<1>.triggerChannel<0><27>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<3>
Project.unit<1>.triggerChannel<0><28>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<4>
Project.unit<1>.triggerChannel<0><29>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<5>
Project.unit<1>.triggerChannel<0><2>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<2>
Project.unit<1>.triggerChannel<0><30>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<6>
Project.unit<1>.triggerChannel<0><31>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<7>
Project.unit<1>.triggerChannel<0><32>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<8>
Project.unit<1>.triggerChannel<0><33>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<9>
Project.unit<1>.triggerChannel<0><34>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<10>
Project.unit<1>.triggerChannel<0><35>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<11>
Project.unit<1>.triggerChannel<0><36>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<12>
Project.unit<1>.triggerChannel<0><37>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<13>
Project.unit<1>.triggerChannel<0><38>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<14>
Project.unit<1>.triggerChannel<0><39>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<15>
Project.unit<1>.triggerChannel<0><3>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<3>
Project.unit<1>.triggerChannel<0><40>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<16>
Project.unit<1>.triggerChannel<0><41>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<17>
Project.unit<1>.triggerChannel<0><42>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<18>
Project.unit<1>.triggerChannel<0><43>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<19>
Project.unit<1>.triggerChannel<0><44>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<20>
Project.unit<1>.triggerChannel<0><45>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<21>
Project.unit<1>.triggerChannel<0><46>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<22>
Project.unit<1>.triggerChannel<0><47>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<23>
Project.unit<1>.triggerChannel<0><48>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<24>
Project.unit<1>.triggerChannel<0><49>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<25>
Project.unit<1>.triggerChannel<0><4>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<4>
Project.unit<1>.triggerChannel<0><50>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_cyc_t
Project.unit<1>.triggerChannel<0><51>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_rd
Project.unit<1>.triggerChannel<0><52>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_valid
Project.unit<1>.triggerChannel<0><53>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_wr
Project.unit<1>.triggerChannel<0><54>=cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/almost_full_int
Project.unit<1>.triggerChannel<0><55>=cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/full_int
Project.unit<1>.triggerChannel<0><56>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<31>
Project.unit<1>.triggerChannel<0><57>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<30>
Project.unit<1>.triggerChannel<0><58>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<29>
Project.unit<1>.triggerChannel<0><59>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<28>
Project.unit<1>.triggerChannel<0><5>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<5>
Project.unit<1>.triggerChannel<0><60>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<27>
Project.unit<1>.triggerChannel<0><61>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<26>
Project.unit<1>.triggerChannel<0><62>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<25>
Project.unit<1>.triggerChannel<0><63>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<24>
Project.unit<1>.triggerChannel<0><64>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<23>
Project.unit<1>.triggerChannel<0><65>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<22>
Project.unit<1>.triggerChannel<0><66>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<21>
Project.unit<1>.triggerChannel<0><67>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<20>
Project.unit<1>.triggerChannel<0><68>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<19>
Project.unit<1>.triggerChannel<0><69>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<18>
Project.unit<1>.triggerChannel<0><6>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<6>
Project.unit<1>.triggerChannel<0><70>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<17>
Project.unit<1>.triggerChannel<0><71>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<16>
Project.unit<1>.triggerChannel<0><72>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<15>
Project.unit<1>.triggerChannel<0><73>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<14>
Project.unit<1>.triggerChannel<0><74>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<13>
Project.unit<1>.triggerChannel<0><75>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<12>
Project.unit<1>.triggerChannel<0><76>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<11>
Project.unit<1>.triggerChannel<0><77>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<10>
Project.unit<1>.triggerChannel<0><78>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<9>
Project.unit<1>.triggerChannel<0><79>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<8>
Project.unit<1>.triggerChannel<0><7>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<7>
Project.unit<1>.triggerChannel<0><80>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<7>
Project.unit<1>.triggerChannel<0><81>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<6>
Project.unit<1>.triggerChannel<0><82>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<5>
Project.unit<1>.triggerChannel<0><83>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<4>
Project.unit<1>.triggerChannel<0><84>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<3>
Project.unit<1>.triggerChannel<0><85>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<2>
Project.unit<1>.triggerChannel<0><86>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<1>
Project.unit<1>.triggerChannel<0><87>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<0>
Project.unit<1>.triggerChannel<0><88>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_ack_o
Project.unit<1>.triggerChannel<0><89>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_stall_o
Project.unit<1>.triggerChannel<0><8>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<8>
Project.unit<1>.triggerChannel<0><90>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_last_packet
Project.unit<1>.triggerChannel<0><91>=
Project.unit<1>.triggerChannel<0><92>=
Project.unit<1>.triggerChannel<0><93>=
Project.unit<1>.triggerChannel<0><94>=
Project.unit<1>.triggerChannel<0><95>=
Project.unit<1>.triggerChannel<0><96>=
Project.unit<1>.triggerChannel<0><97>=
Project.unit<1>.triggerChannel<0><98>=
Project.unit<1>.triggerChannel<0><99>=
Project.unit<1>.triggerChannel<0><9>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<9>
Project.unit<1>.triggerConditionCountWidth=0
Project.unit<1>.triggerMatchCount<0>=1
Project.unit<1>.triggerMatchCountWidth<0><0>=0
Project.unit<1>.triggerMatchType<0><0>=1
Project.unit<1>.triggerPortCount=1
Project.unit<1>.triggerPortIsData<0>=true
Project.unit<1>.triggerPortWidth<0>=91
Project.unit<1>.triggerSequencerLevels=16
Project.unit<1>.triggerSequencerType=1
Project.unit<1>.type=ilapro
hdl/spec/chipscope/gn4124_local_bus_sdb_hang.cpj 0 → 100644
View file @ 2f92c67d
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hdl/spec/chipscope/gn4124_sdb_hang.cdc 0 → 100644
View file @ 2f92c67d
#ChipScope Core Inserter Project File Version 3.0
#Fri Feb 01 12:23:53 CET 2013
Project.device.designInputFile=/home/mcattin/projects/svn_to_git/fmc-adc-100m14b4cha_git/hdl/spec/syn/spec_top_fmc_adc_100Ms.ngc
Project.device.designOutputFile=/home/mcattin/projects/svn_to_git/fmc-adc-100m14b4cha_git/hdl/spec/syn/spec_top_fmc_adc_100Ms.ngc
Project.device.deviceFamily=18
Project.device.enableRPMs=true
Project.device.outputDirectory=/home/mcattin/projects/svn_to_git/fmc-adc-100m14b4cha_git/hdl/spec/syn/_ngo
Project.device.useSRL16=true
Project.filter.dimension=19
Project.filter<0>=cmp_gn4124_core/cmp_dma_controller*reg*
Project.filter<10>=cmp_gn4124_core/*rdy*
Project.filter<11>=cmp_gn4124_core/*rx*err*
Project.filter<12>=cmp_gn4124_core/*err*
Project.filter<13>=cmp_gn4124_core/*error*
Project.filter<14>=cmp_gn4124_core/cmp_p2l_decode32/*
Project.filter<15>=cmp_gn4124_core/cmp_p2l*
Project.filter<16>=cmp_gn4124_core/cmp_p2l_decoder32/*
Project.filter<17>=cmp_gn4124_core/*p2l_*
Project.filter<18>=cmp_gn4124_core/p2l_*
Project.filter<1>=cmp_gn4124_core/cmp_dma_controller**
Project.filter<2>=cmp_gn4124_core/**
Project.filter<3>=cmp_gn**
Project.filter<4>=*irq*
Project.filter<5>=cmp_gn4124_core/cmp_dma_contr*
Project.filter<6>=cmp_gn4124_core/*dma*
Project.filter<7>=cmp_gn4124_core/*arb*
Project.filter<8>=cmp_gn4124_core/cmp_p2l_decode32*
Project.filter<9>=cmp_gn4124_core/*tx*
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=cmp_gn4124_core/sys_clk
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataDepth=2048
Project.unit<0>.dataEqualsTrigger=true
Project.unit<0>.dataPortWidth=248
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<31>
Project.unit<0>.triggerChannel<0><100>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<21>
Project.unit<0>.triggerChannel<0><101>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<20>
Project.unit<0>.triggerChannel<0><102>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<19>
Project.unit<0>.triggerChannel<0><103>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<18>
Project.unit<0>.triggerChannel<0><104>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<17>
Project.unit<0>.triggerChannel<0><105>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<16>
Project.unit<0>.triggerChannel<0><106>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<15>
Project.unit<0>.triggerChannel<0><107>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<14>
Project.unit<0>.triggerChannel<0><108>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<13>
Project.unit<0>.triggerChannel<0><109>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<12>
Project.unit<0>.triggerChannel<0><10>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<21>
Project.unit<0>.triggerChannel<0><110>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<11>
Project.unit<0>.triggerChannel<0><111>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<10>
Project.unit<0>.triggerChannel<0><112>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<9>
Project.unit<0>.triggerChannel<0><113>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<8>
Project.unit<0>.triggerChannel<0><114>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<7>
Project.unit<0>.triggerChannel<0><115>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<6>
Project.unit<0>.triggerChannel<0><116>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<5>
Project.unit<0>.triggerChannel<0><117>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<4>
Project.unit<0>.triggerChannel<0><118>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<3>
Project.unit<0>.triggerChannel<0><119>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<2>
Project.unit<0>.triggerChannel<0><11>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<20>
Project.unit<0>.triggerChannel<0><120>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<1>
Project.unit<0>.triggerChannel<0><121>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<0>
Project.unit<0>.triggerChannel<0><122>=cmp_irq_controller/irq_p_o
Project.unit<0>.triggerChannel<0><123>=acq_end_irq_p
Project.unit<0>.triggerChannel<0><124>=dma_irq<1>
Project.unit<0>.triggerChannel<0><125>=dma_irq<0>
Project.unit<0>.triggerChannel<0><126>=cmp_gn4124_core/cmp_dma_controller/dma_ctrl_reg<3>
Project.unit<0>.triggerChannel<0><127>=cmp_gn4124_core/cmp_dma_controller/dma_ctrl_reg<2>
Project.unit<0>.triggerChannel<0><128>=cmp_gn4124_core/cmp_dma_controller/dma_ctrl_reg<1>
Project.unit<0>.triggerChannel<0><129>=cmp_gn4124_core/cmp_dma_controller/dma_ctrl_reg<0>
Project.unit<0>.triggerChannel<0><12>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<19>
Project.unit<0>.triggerChannel<0><130>=cmp_gn4124_core/cmp_dma_controller/dma_stat_reg<2>
Project.unit<0>.triggerChannel<0><131>=cmp_gn4124_core/cmp_dma_controller/dma_stat_reg<1>
Project.unit<0>.triggerChannel<0><132>=cmp_gn4124_core/cmp_dma_controller/dma_stat_reg<0>
Project.unit<0>.triggerChannel<0><133>=cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg<1>
Project.unit<0>.triggerChannel<0><134>=cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg<0>
Project.unit<0>.triggerChannel<0><135>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<31>
Project.unit<0>.triggerChannel<0><136>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<30>
Project.unit<0>.triggerChannel<0><137>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<29>
Project.unit<0>.triggerChannel<0><138>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<28>
Project.unit<0>.triggerChannel<0><139>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<27>
Project.unit<0>.triggerChannel<0><13>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<18>
Project.unit<0>.triggerChannel<0><140>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<26>
Project.unit<0>.triggerChannel<0><141>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<25>
Project.unit<0>.triggerChannel<0><142>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<24>
Project.unit<0>.triggerChannel<0><143>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<23>
Project.unit<0>.triggerChannel<0><144>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<22>
Project.unit<0>.triggerChannel<0><145>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<21>
Project.unit<0>.triggerChannel<0><146>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<20>
Project.unit<0>.triggerChannel<0><147>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<19>
Project.unit<0>.triggerChannel<0><148>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<18>
Project.unit<0>.triggerChannel<0><149>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<17>
Project.unit<0>.triggerChannel<0><14>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<17>
Project.unit<0>.triggerChannel<0><150>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<16>
Project.unit<0>.triggerChannel<0><151>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<15>
Project.unit<0>.triggerChannel<0><152>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<14>
Project.unit<0>.triggerChannel<0><153>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<13>
Project.unit<0>.triggerChannel<0><154>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<12>
Project.unit<0>.triggerChannel<0><155>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<11>
Project.unit<0>.triggerChannel<0><156>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<10>
Project.unit<0>.triggerChannel<0><157>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<9>
Project.unit<0>.triggerChannel<0><158>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<8>
Project.unit<0>.triggerChannel<0><159>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<7>
Project.unit<0>.triggerChannel<0><15>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<16>
Project.unit<0>.triggerChannel<0><160>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<6>
Project.unit<0>.triggerChannel<0><161>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<5>
Project.unit<0>.triggerChannel<0><162>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<4>
Project.unit<0>.triggerChannel<0><163>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<3>
Project.unit<0>.triggerChannel<0><164>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<2>
Project.unit<0>.triggerChannel<0><165>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<1>
Project.unit<0>.triggerChannel<0><166>=cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg<0>
Project.unit<0>.triggerChannel<0><167>=cmp_gn4124_core/cmp_dma_controller/dma_len_reg<16>
Project.unit<0>.triggerChannel<0><168>=cmp_gn4124_core/cmp_dma_controller/dma_len_reg<15>
Project.unit<0>.triggerChannel<0><169>=cmp_gn4124_core/cmp_dma_controller/dma_len_reg<14>
Project.unit<0>.triggerChannel<0><16>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<15>
Project.unit<0>.triggerChannel<0><170>=cmp_gn4124_core/cmp_dma_controller/dma_len_reg<13>
Project.unit<0>.triggerChannel<0><171>=cmp_gn4124_core/cmp_dma_controller/dma_len_reg<12>
Project.unit<0>.triggerChannel<0><172>=cmp_gn4124_core/cmp_dma_controller/dma_len_reg<11>
Project.unit<0>.triggerChannel<0><173>=cmp_gn4124_core/cmp_dma_controller/dma_len_reg<10>
Project.unit<0>.triggerChannel<0><174>=cmp_gn4124_core/cmp_dma_controller/dma_len_reg<9>
Project.unit<0>.triggerChannel<0><175>=cmp_gn4124_core/cmp_dma_controller/dma_len_reg<8>
Project.unit<0>.triggerChannel<0><176>=cmp_gn4124_core/cmp_dma_controller/dma_len_reg<7>
Project.unit<0>.triggerChannel<0><177>=cmp_gn4124_core/cmp_dma_controller/dma_len_reg<6>
Project.unit<0>.triggerChannel<0><178>=cmp_gn4124_core/cmp_dma_controller/dma_len_reg<5>
Project.unit<0>.triggerChannel<0><179>=cmp_gn4124_core/cmp_dma_controller/dma_len_reg<4>
Project.unit<0>.triggerChannel<0><17>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<14>
Project.unit<0>.triggerChannel<0><180>=cmp_gn4124_core/cmp_dma_controller/dma_len_reg<3>
Project.unit<0>.triggerChannel<0><181>=cmp_gn4124_core/cmp_dma_controller/dma_len_reg<2>
Project.unit<0>.triggerChannel<0><182>=cmp_gn4124_core/cmp_dma_controller/dma_len_reg<1>
Project.unit<0>.triggerChannel<0><183>=cmp_gn4124_core/cmp_dma_controller/dma_len_reg<0>
Project.unit<0>.triggerChannel<0><184>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<31>
Project.unit<0>.triggerChannel<0><185>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<30>
Project.unit<0>.triggerChannel<0><186>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<29>
Project.unit<0>.triggerChannel<0><187>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<28>
Project.unit<0>.triggerChannel<0><188>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<27>
Project.unit<0>.triggerChannel<0><189>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<26>
Project.unit<0>.triggerChannel<0><18>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<13>
Project.unit<0>.triggerChannel<0><190>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<25>
Project.unit<0>.triggerChannel<0><191>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<24>
Project.unit<0>.triggerChannel<0><192>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<23>
Project.unit<0>.triggerChannel<0><193>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<22>
Project.unit<0>.triggerChannel<0><194>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<21>
Project.unit<0>.triggerChannel<0><195>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<20>
Project.unit<0>.triggerChannel<0><196>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<19>
Project.unit<0>.triggerChannel<0><197>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<18>
Project.unit<0>.triggerChannel<0><198>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<17>
Project.unit<0>.triggerChannel<0><199>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<16>
Project.unit<0>.triggerChannel<0><19>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<12>
Project.unit<0>.triggerChannel<0><1>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<30>
Project.unit<0>.triggerChannel<0><200>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<15>
Project.unit<0>.triggerChannel<0><201>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<14>
Project.unit<0>.triggerChannel<0><202>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<13>
Project.unit<0>.triggerChannel<0><203>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<12>
Project.unit<0>.triggerChannel<0><204>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<11>
Project.unit<0>.triggerChannel<0><205>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<10>
Project.unit<0>.triggerChannel<0><206>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<9>
Project.unit<0>.triggerChannel<0><207>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<8>
Project.unit<0>.triggerChannel<0><208>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<7>
Project.unit<0>.triggerChannel<0><209>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<6>
Project.unit<0>.triggerChannel<0><20>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<11>
Project.unit<0>.triggerChannel<0><210>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<5>
Project.unit<0>.triggerChannel<0><211>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<4>
Project.unit<0>.triggerChannel<0><212>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<3>
Project.unit<0>.triggerChannel<0><213>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<2>
Project.unit<0>.triggerChannel<0><214>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<1>
Project.unit<0>.triggerChannel<0><215>=cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg<0>
Project.unit<0>.triggerChannel<0><216>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<31>
Project.unit<0>.triggerChannel<0><217>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<30>
Project.unit<0>.triggerChannel<0><218>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<29>
Project.unit<0>.triggerChannel<0><219>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<28>
Project.unit<0>.triggerChannel<0><21>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<10>
Project.unit<0>.triggerChannel<0><220>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<27>
Project.unit<0>.triggerChannel<0><221>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<26>
Project.unit<0>.triggerChannel<0><222>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<25>
Project.unit<0>.triggerChannel<0><223>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<24>
Project.unit<0>.triggerChannel<0><224>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<23>
Project.unit<0>.triggerChannel<0><225>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<22>
Project.unit<0>.triggerChannel<0><226>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<21>
Project.unit<0>.triggerChannel<0><227>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<20>
Project.unit<0>.triggerChannel<0><228>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<19>
Project.unit<0>.triggerChannel<0><229>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<18>
Project.unit<0>.triggerChannel<0><22>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<9>
Project.unit<0>.triggerChannel<0><230>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<17>
Project.unit<0>.triggerChannel<0><231>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<16>
Project.unit<0>.triggerChannel<0><232>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<15>
Project.unit<0>.triggerChannel<0><233>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<14>
Project.unit<0>.triggerChannel<0><234>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<13>
Project.unit<0>.triggerChannel<0><235>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<12>
Project.unit<0>.triggerChannel<0><236>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<11>
Project.unit<0>.triggerChannel<0><237>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<10>
Project.unit<0>.triggerChannel<0><238>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<9>
Project.unit<0>.triggerChannel<0><239>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<8>
Project.unit<0>.triggerChannel<0><23>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<8>
Project.unit<0>.triggerChannel<0><240>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<7>
Project.unit<0>.triggerChannel<0><241>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<6>
Project.unit<0>.triggerChannel<0><242>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<5>
Project.unit<0>.triggerChannel<0><243>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<4>
Project.unit<0>.triggerChannel<0><244>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<3>
Project.unit<0>.triggerChannel<0><245>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<2>
Project.unit<0>.triggerChannel<0><246>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<1>
Project.unit<0>.triggerChannel<0><247>=cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg<0>
Project.unit<0>.triggerChannel<0><248>=
Project.unit<0>.triggerChannel<0><249>=
Project.unit<0>.triggerChannel<0><24>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<7>
Project.unit<0>.triggerChannel<0><250>=
Project.unit<0>.triggerChannel<0><251>=
Project.unit<0>.triggerChannel<0><252>=
Project.unit<0>.triggerChannel<0><253>=
Project.unit<0>.triggerChannel<0><254>=
Project.unit<0>.triggerChannel<0><255>=
Project.unit<0>.triggerChannel<0><25>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<6>
Project.unit<0>.triggerChannel<0><26>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<5>
Project.unit<0>.triggerChannel<0><27>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<4>
Project.unit<0>.triggerChannel<0><28>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<3>
Project.unit<0>.triggerChannel<0><29>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<2>
Project.unit<0>.triggerChannel<0><2>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<29>
Project.unit<0>.triggerChannel<0><30>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<1>
Project.unit<0>.triggerChannel<0><31>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<0>
Project.unit<0>.triggerChannel<0><32>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<31>
Project.unit<0>.triggerChannel<0><33>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<30>
Project.unit<0>.triggerChannel<0><34>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<29>
Project.unit<0>.triggerChannel<0><35>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<28>
Project.unit<0>.triggerChannel<0><36>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<27>
Project.unit<0>.triggerChannel<0><37>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<26>
Project.unit<0>.triggerChannel<0><38>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<25>
Project.unit<0>.triggerChannel<0><39>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<24>
Project.unit<0>.triggerChannel<0><3>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<28>
Project.unit<0>.triggerChannel<0><40>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<23>
Project.unit<0>.triggerChannel<0><41>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<22>
Project.unit<0>.triggerChannel<0><42>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<21>
Project.unit<0>.triggerChannel<0><43>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<20>
Project.unit<0>.triggerChannel<0><44>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<19>
Project.unit<0>.triggerChannel<0><45>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<18>
Project.unit<0>.triggerChannel<0><46>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<17>
Project.unit<0>.triggerChannel<0><47>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<16>
Project.unit<0>.triggerChannel<0><48>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<15>
Project.unit<0>.triggerChannel<0><49>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<14>
Project.unit<0>.triggerChannel<0><4>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<27>
Project.unit<0>.triggerChannel<0><50>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<13>
Project.unit<0>.triggerChannel<0><51>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<12>
Project.unit<0>.triggerChannel<0><52>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<11>
Project.unit<0>.triggerChannel<0><53>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<10>
Project.unit<0>.triggerChannel<0><54>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<9>
Project.unit<0>.triggerChannel<0><55>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<8>
Project.unit<0>.triggerChannel<0><56>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<7>
Project.unit<0>.triggerChannel<0><57>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<6>
Project.unit<0>.triggerChannel<0><58>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<5>
Project.unit<0>.triggerChannel<0><59>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<4>
Project.unit<0>.triggerChannel<0><5>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<26>
Project.unit<0>.triggerChannel<0><60>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<3>
Project.unit<0>.triggerChannel<0><61>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<2>
Project.unit<0>.triggerChannel<0><62>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<0>
Project.unit<0>.triggerChannel<0><63>=cmp_gn4124_core/cmp_p2l_decode32/des_p2l_valid_d
Project.unit<0>.triggerChannel<0><64>=cmp_gn4124_core/cmp_p2l_decode32/des_p2l_dframe_d
Project.unit<0>.triggerChannel<0><65>=cmp_gn4124_core/cmp_p2l_decode32/target_mwr
Project.unit<0>.triggerChannel<0><66>=cmp_gn4124_core/cmp_p2l_decode32/target_mrd
Project.unit<0>.triggerChannel<0><67>=cmp_gn4124_core/cmp_p2l_decode32/master_cpln
Project.unit<0>.triggerChannel<0><68>=cmp_gn4124_core/cmp_p2l_decode32/master_cpld
Project.unit<0>.triggerChannel<0><69>=cmp_gn4124_core/cmp_p2l_decode32/p2l_packet_start
Project.unit<0>.triggerChannel<0><6>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<25>
Project.unit<0>.triggerChannel<0><70>=cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_strobe
Project.unit<0>.triggerChannel<0><71>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d_valid
Project.unit<0>.triggerChannel<0><72>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d_last
Project.unit<0>.triggerChannel<0><73>=cmp_gn4124_core/cmp_p2l_decode32/p2l_data_cycle
Project.unit<0>.triggerChannel<0><74>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_start
Project.unit<0>.triggerChannel<0><75>=cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_cycle
Project.unit<0>.triggerChannel<0><76>=cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_cid<1>
Project.unit<0>.triggerChannel<0><77>=cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_cid<0>
Project.unit<0>.triggerChannel<0><78>=cmp_gn4124_core/dma_ctrl_error
Project.unit<0>.triggerChannel<0><79>=cmp_gn4124_core/cmp_p2l_dma_master/rx_error_o
Project.unit<0>.triggerChannel<0><7>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<24>
Project.unit<0>.triggerChannel<0><80>=cmp_gn4124_core/p_rd_d_rdy<1>
Project.unit<0>.triggerChannel<0><81>=cmp_gn4124_core/p_rd_d_rdy<0>
Project.unit<0>.triggerChannel<0><82>=cmp_gn4124_core/l_wr_rdy<1>
Project.unit<0>.triggerChannel<0><83>=cmp_gn4124_core/l_wr_rdy<0>
Project.unit<0>.triggerChannel<0><84>=cmp_gn4124_core/l2p_rdy
Project.unit<0>.triggerChannel<0><85>=cmp_gn4124_core/cmp_l2p_arbiter/arb_wbm_gnt
Project.unit<0>.triggerChannel<0><86>=cmp_gn4124_core/cmp_l2p_arbiter/arb_pdm_gnt
Project.unit<0>.triggerChannel<0><87>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ldm_gnt
Project.unit<0>.triggerChannel<0><88>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_valid_o
Project.unit<0>.triggerChannel<0><89>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_dframe_o
Project.unit<0>.triggerChannel<0><8>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<23>
Project.unit<0>.triggerChannel<0><90>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<31>
Project.unit<0>.triggerChannel<0><91>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<30>
Project.unit<0>.triggerChannel<0><92>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<29>
Project.unit<0>.triggerChannel<0><93>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<28>
Project.unit<0>.triggerChannel<0><94>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<27>
Project.unit<0>.triggerChannel<0><95>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<26>
Project.unit<0>.triggerChannel<0><96>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<25>
Project.unit<0>.triggerChannel<0><97>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<24>
Project.unit<0>.triggerChannel<0><98>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<23>
Project.unit<0>.triggerChannel<0><99>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<22>
Project.unit<0>.triggerChannel<0><9>=cmp_gn4124_core/cmp_p2l_decode32/p2l_d<22>
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=2
Project.unit<0>.triggerMatchCount<1>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchCountWidth<0><1>=0
Project.unit<0>.triggerMatchCountWidth<0><2>=0
Project.unit<0>.triggerMatchCountWidth<1><0>=0
Project.unit<0>.triggerMatchType<0><0>=5
Project.unit<0>.triggerMatchType<0><1>=5
Project.unit<0>.triggerMatchType<0><2>=5
Project.unit<0>.triggerMatchType<1><0>=1
Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortIsData<1>=true
Project.unit<0>.triggerPortWidth<0>=248
Project.unit<0>.triggerPortWidth<1>=8
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro
hdl/spec/rtl/Manifest.py
View file @ 2f92c67d
......@@ -4,13 +4,13 @@ files = [
"utc_core_regs.vhd",
"utc_core.vhd",
"irq_controller_regs.vhd",
"irq_controller.vhd"];
"irq_controller.vhd",
"sdb_meta_pkg.vhd"];
modules = {
"local" : "../../adc/rtl",
"svn" : [ "http://svn.ohwr.org/ddr3-sp6-core/trunk/hdl",
"http://svn.ohwr.org/gn4124-core/trunk/hdl/gn4124core/rtl",
"http://svn.ohwr.org/gn4124-core/trunk/hdl/common/rtl"],
"git" : "git://ohwr.org/hdl-core-lib/general-cores.git"}
"git" : ["git://ohwr.org/hdl-core-lib/general-cores.git::sdb_extension",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git::spec_bank3_64b_32b",
"git://ohwr.org/hdl-core-lib/gn4124-core.git::master"]}
fetchto="../ip_cores"
hdl/spec/rtl/carrier_csr.vhd
View file @ 2f92c67d
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Wed Nov 23 09:30:44 2011
-- Created : Mon Mar 11 17:11:09 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -18,7 +18,7 @@ entity carrier_csr is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -32,10 +32,6 @@ entity carrier_csr is
carrier_csr_carrier_reserved_i : in std_logic_vector(11 downto 0);
-- Port for std_logic_vector field: 'Carrier type' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_type_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Bitstream type' in reg: 'Bitstream type'
carrier_csr_bitstream_type_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Bitstream date' in reg: 'Bitstream date'
carrier_csr_bitstream_date_i : in std_logic_vector(31 downto 0);
-- Port for BIT field: 'FMC presence' in reg: 'Status'
carrier_csr_stat_fmc_pres_i : in std_logic;
-- Port for BIT field: 'GN4142 core P2L PLL status' in reg: 'Status'
......@@ -67,7 +63,7 @@ signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
......@@ -107,8 +103,8 @@ begin
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
else
rddata_reg(3 downto 0) <= carrier_csr_carrier_pcb_rev_i;
......@@ -117,22 +113,12 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= carrier_csr_bitstream_type_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= carrier_csr_bitstream_date_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
when "01" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
else
rddata_reg(0) <= carrier_csr_stat_fmc_pres_i;
rddata_reg(1) <= carrier_csr_stat_p2l_pll_lck_i;
......@@ -142,10 +128,13 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
when "10" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
carrier_csr_ctrl_led_green_int <= wrdata_reg(0);
rddata_reg(1) <= 'X';
carrier_csr_ctrl_led_red_int <= wrdata_reg(1);
rddata_reg(2) <= 'X';
carrier_csr_ctrl_dac_clr_n_int <= wrdata_reg(2);
carrier_csr_ctrl_reserved_int <= wrdata_reg(31 downto 3);
else
......@@ -172,8 +161,6 @@ begin
-- PCB revision
-- Reserved register
-- Carrier type
-- Bitstream type
-- Bitstream date
-- FMC presence
-- GN4142 core P2L PLL status
-- System clock PLL status
......
hdl/spec/rtl/sdb_meta_pkg.vhd 0 → 100644
View file @ 2f92c67d
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package sdb_meta_pkg is
------------------------------------------------------------------------------
-- Meta-information sdb records
------------------------------------------------------------------------------
-- Top module repository url
constant c_REPO_URL : t_sdb_repo_url := (
-- url (string, 63 char)
repo_url => "git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha.git ");
-- Synthesis informations
constant c_SYNTHESIS : t_sdb_synthesis := (
-- Top module name (string, 16 char)
syn_module_name => "spec_top_fmc_adc",
-- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="%H" | cut -c1-31
syn_commit_id => "150b83db8fa9e0ff9050166b7695ee9a",
-- Synthesis tool name (string, 8 char)
syn_tool_name => "ISE ",
-- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version => x"00000133",
-- Synthesis date (bcd encoded, 32-bit)
syn_date => x"20130307",
-- Synthesised by (string, 15 char)
syn_username => "mcattin ");
-- Integration record
constant c_INTEGRATION : t_sdb_integration := (
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"47c786a2", -- echo "spec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version => x"00010000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20130307", -- yyyymmdd
name => "spec_fmcadc100m14b "));
end sdb_meta_pkg;
package body sdb_meta_pkg is
end sdb_meta_pkg;
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ 2f92c67d
......@@ -46,6 +46,8 @@ use work.gn4124_core_pkg.all;
use work.ddr3_ctrl_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.fmc_adc_100Ms_core_pkg.all;
use work.sdb_meta_pkg.all;
entity spec_top_fmc_adc_100Ms is
......@@ -140,14 +142,14 @@ entity spec_top_fmc_adc_100Ms is
spi_cs_dac3_n_o : out std_logic; -- SPI channel 3 offset DAC chip select (active low)
spi_cs_dac4_n_o : out std_logic; -- SPI channel 4 offset DAC chip select (active low)
gpio_dac_clr_n_o : out std_logic; -- offset DACs clear (active low)
gpio_led_power_o : out std_logic; -- Mezzanine front panel power LED (PWR)
gpio_led_trigger_o : out std_logic; -- Mezzanine front panel trigger LED (TRIG)
gpio_ssr_ch1_o : out std_logic_vector(6 downto 0); -- Channel 1 solid state relays control
gpio_ssr_ch2_o : out std_logic_vector(6 downto 0); -- Channel 2 solid state relays control
gpio_ssr_ch3_o : out std_logic_vector(6 downto 0); -- Channel 3 solid state relays control
gpio_ssr_ch4_o : out std_logic_vector(6 downto 0); -- Channel 4 solid state relays control
gpio_si570_oe_o : out std_logic; -- Si570 (programmable oscillator) output enable
gpio_dac_clr_n_o : out std_logic; -- offset DACs clear (active low)
gpio_led_acq_o : out std_logic; -- Mezzanine front panel power LED (PWR)
gpio_led_trig_o : out std_logic; -- Mezzanine front panel trigger LED (TRIG)
gpio_ssr_ch1_o : out std_logic_vector(6 downto 0); -- Channel 1 solid state relays control
gpio_ssr_ch2_o : out std_logic_vector(6 downto 0); -- Channel 2 solid state relays control
gpio_ssr_ch3_o : out std_logic_vector(6 downto 0); -- Channel 3 solid state relays control
gpio_ssr_ch4_o : out std_logic_vector(6 downto 0); -- Channel 4 solid state relays control
gpio_si570_oe_o : out std_logic; -- Si570 (programmable oscillator) output enable
si570_scl_b : inout std_logic; -- I2C bus clock (Si570)
si570_sda_b : inout std_logic; -- I2C bus data (Si570)
......@@ -167,50 +169,11 @@ architecture rtl of spec_top_fmc_adc_100Ms is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component wb_addr_decoder
generic
(
g_WINDOW_SIZE : integer := 18; -- Number of bits to address periph on the board (32-bit word address)
g_WB_SLAVES_NB : integer := 2
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- wishbone master interface
wbm_adr_i : in std_logic_vector(31 downto 0); -- Address
wbm_dat_i : in std_logic_vector(31 downto 0); -- Data out
wbm_sel_i : in std_logic_vector(3 downto 0); -- Byte select
wbm_stb_i : in std_logic; -- Strobe
wbm_we_i : in std_logic; -- Write
wbm_cyc_i : in std_logic; -- Cycle
wbm_dat_o : out std_logic_vector(31 downto 0); -- Data in
wbm_ack_o : out std_logic; -- Acknowledge
wbm_stall_o : out std_logic; -- Stall
---------------------------------------------------------
-- wishbone slaves interface
wb_adr_o : out std_logic_vector(31 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Acknowledge
wb_stall_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Stall
);
end component wb_addr_decoder;
component carrier_csr
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -221,8 +184,6 @@ architecture rtl of spec_top_fmc_adc_100Ms is
carrier_csr_carrier_pcb_rev_i : in std_logic_vector(3 downto 0);
carrier_csr_carrier_reserved_i : in std_logic_vector(11 downto 0);
carrier_csr_carrier_type_i : in std_logic_vector(15 downto 0);
carrier_csr_bitstream_type_i : in std_logic_vector(31 downto 0);
carrier_csr_bitstream_date_i : in std_logic_vector(31 downto 0);
carrier_csr_stat_fmc_pres_i : in std_logic;
carrier_csr_stat_p2l_pll_lck_i : in std_logic;
carrier_csr_stat_sys_pll_lck_i : in std_logic;
......@@ -271,97 +232,194 @@ architecture rtl of spec_top_fmc_adc_100Ms is
);
end component irq_controller;
component fmc_adc_100Ms_core
port (
-- Clock, reset
sys_clk_i : in std_logic;
sys_rst_n_i : in std_logic;
-- CSR wishbone interface
wb_csr_adr_i : in std_logic_vector(4 downto 0);
wb_csr_dat_i : in std_logic_vector(31 downto 0);
wb_csr_dat_o : out std_logic_vector(31 downto 0);
wb_csr_cyc_i : in std_logic;
wb_csr_sel_i : in std_logic_vector(3 downto 0);
wb_csr_stb_i : in std_logic;
wb_csr_we_i : in std_logic;
wb_csr_ack_o : out std_logic;
-- DDR wishbone interface
wb_ddr_clk_i : in std_logic;
wb_ddr_adr_o : out std_logic_vector(31 downto 0);
wb_ddr_dat_o : out std_logic_vector(63 downto 0);
wb_ddr_sel_o : out std_logic_vector(7 downto 0);
wb_ddr_stb_o : out std_logic;
wb_ddr_we_o : out std_logic;
wb_ddr_cyc_o : out std_logic;
wb_ddr_ack_i : in std_logic;
wb_ddr_stall_i : in std_logic;
-- Events output pulses
trigger_p_o : out std_logic;
acq_start_p_o : out std_logic;
acq_stop_p_o : out std_logic;
acq_end_p_o : out std_logic;
-- FMC interface
ext_trigger_p_i : in std_logic; -- External trigger
ext_trigger_n_i : in std_logic;
adc_dco_p_i : in std_logic; -- ADC data clock
adc_dco_n_i : in std_logic;
adc_fr_p_i : in std_logic; -- ADC frame start
adc_fr_n_i : in std_logic;
adc_outa_p_i : in std_logic_vector(3 downto 0); -- ADC serial data (odd bits)
adc_outa_n_i : in std_logic_vector(3 downto 0);
adc_outb_p_i : in std_logic_vector(3 downto 0); -- ADC serial data (even bits)
adc_outb_n_i : in std_logic_vector(3 downto 0);
------------------------------------------------------------------------------
-- SDB crossbar constants declaration
--
-- WARNING: All address in sdb and crossbar are BYTE addresses!
------------------------------------------------------------------------------
gpio_dac_clr_n_o : out std_logic; -- offset DACs clear (active low)
gpio_led_acq_o : out std_logic; -- Mezzanine front panel power LED (PWR)
gpio_led_trig_o : out std_logic; -- Mezzanine front panel trigger LED (TRIG)
gpio_ssr_ch1_o : out std_logic_vector(6 downto 0); -- Channel 1 solid state relays control
gpio_ssr_ch2_o : out std_logic_vector(6 downto 0); -- Channel 2 solid state relays control
gpio_ssr_ch3_o : out std_logic_vector(6 downto 0); -- Channel 3 solid state relays control
gpio_ssr_ch4_o : out std_logic_vector(6 downto 0); -- Channel 4 solid state relays control
gpio_si570_oe_o : out std_logic -- Si570 (programmable oscillator) output enable
-- Meta-information sdb records
constant c_SDB_INFO : t_sdb_record_array(2 downto 0) := (
0 => f_sdb_embed_repo_url(c_REPO_URL),
1 => f_sdb_embed_synthesis(c_SYNTHESIS),
2 => f_sdb_embed_integration(c_INTEGRATION)
);
-- Number of master port(s) on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 10;
-- Number of slave port(s) on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1;
-- Wishbone master(s)
constant c_MASTER_GENNUM : integer := 0;
-- Wishbone slave(s)
constant c_SLAVE_DMA : integer := 0; -- DMA controller in the Gennum core
constant c_SLAVE_ONEWIRE : integer := 1; -- Carrier onewire interface
constant c_SLAVE_SPEC_CSR : integer := 2; -- SPEC control and status registers
constant c_SLAVE_UTC : integer := 3; -- UTC core for time-tagging
constant c_SLAVE_INT : integer := 4; -- Interrupt controller
constant c_SLAVE_FMC_SYS_I2C : integer := 5; -- Mezzanine system I2C interface (EEPROM)
constant c_SLAVE_FMC_SPI : integer := 6; -- Mezzanine SPI interface
constant c_SLAVE_FMC_I2C : integer := 7; -- Mezzanine I2C controller
constant c_SLAVE_FMC_ADC : integer := 8; -- Mezzanine ADC core
constant c_SLAVE_FMC_ONEWIRE : integer := 9; -- Mezzanine onewire interface
-- Devices sdb description
constant c_DMA_SDB_DEVICE : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000003F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000601",
version => x"00000001",
date => x"20121116",
name => "WB-DMA.Control ")));
constant c_ONEWIRE_SDB_DEVICE : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"0000000000000007",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000602",
version => x"00000001",
date => x"20121116",
name => "WB-Onewire.Control ")));
constant c_SPEC_CSR_SDB_DEVICE : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000603",
version => x"00000001",
date => x"20121116",
name => "WB-SPEC-CSR ")));
constant c_UTC_SDB_DEVICE : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000007F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000604",
version => x"00000001",
date => x"20121116",
name => "WB-UTC-Core ")));
constant c_INT_SDB_DEVICE : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000000F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000605",
version => x"00000001",
date => x"20121116",
name => "WB-Int.Control ")));
constant c_I2C_SDB_DEVICE : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000606",
version => x"00000001",
date => x"20121116",
name => "WB-I2C.Control ")));
constant c_SPI_SDB_DEVICE : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000607",
version => x"00000001",
date => x"20121116",
name => "WB-SPI.Control ")));
constant c_ADC_SDB_DEVICE : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000007F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000608",
version => x"00000001",
date => x"20121116",
name => "WB-FMC-ADC-Core ")));
-- sdb header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- Wishbone crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS-1 downto 0) :=
(
c_SLAVE_DMA => f_sdb_embed_device(c_DMA_SDB_DEVICE, x"00001000"),
c_SLAVE_ONEWIRE => f_sdb_embed_device(c_ONEWIRE_SDB_DEVICE, x"00001200"),
c_SLAVE_SPEC_CSR => f_sdb_embed_device(c_SPEC_CSR_SDB_DEVICE, x"00001300"),
c_SLAVE_UTC => f_sdb_embed_device(c_UTC_SDB_DEVICE, x"00001400"),
c_SLAVE_INT => f_sdb_embed_device(c_INT_SDB_DEVICE, x"00001500"),
c_SLAVE_FMC_SYS_I2C => f_sdb_embed_device(c_I2C_SDB_DEVICE, x"00001600"),
c_SLAVE_FMC_SPI => f_sdb_embed_device(c_SPI_SDB_DEVICE, x"00001700"),
c_SLAVE_FMC_I2C => f_sdb_embed_device(c_I2C_SDB_DEVICE, x"00001800"),
c_SLAVE_FMC_ADC => f_sdb_embed_device(c_ADC_SDB_DEVICE, x"00001900"),
c_SLAVE_FMC_ONEWIRE => f_sdb_embed_device(c_ONEWIRE_SDB_DEVICE, x"00001A00")
);
end component fmc_adc_100Ms_core;
component test_dpram
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(9 downto 0);
dina : in std_logic_vector(31 downto 0);
clkb : in std_logic;
addrb : in std_logic_vector(9 downto 0);
doutb : out std_logic_vector(31 downto 0));
end component test_dpram;
------------------------------------------------------------------------------
-- Constants declaration
-- Other constants declaration
------------------------------------------------------------------------------
-- SPEC carrier CSR constants
constant c_CARRIER_TYPE : std_logic_vector(15 downto 0) := X"0001";
constant c_BITSTREAM_TYPE : std_logic_vector(31 downto 0) := X"00000001";
constant c_BITSTREAM_DATE : std_logic_vector(31 downto 0) := X"4D6BBE3E"; -- UTC time
constant c_BAR0_APERTURE : integer := 18; -- nb of bits for 32-bit word address (= byte aperture - 2)
constant c_CSR_WB_SLAVES_NB : integer := 11;
constant c_CSR_WB_DMA_CONFIG : integer := 0;
constant c_CSR_WB_CARRIER_SPI : integer := 1;
constant c_CSR_WB_CARRIER_ONE_WIRE : integer := 2;
constant c_CSR_WB_CARRIER_CSR : integer := 3;
constant c_CSR_WB_UTC_CORE : integer := 4;
constant c_CSR_WB_IRQ_CTRL : integer := 5;
constant c_CSR_WB_FMC_SYS_I2C : integer := 6;
constant c_CSR_WB_FMC_SPI : integer := 7;
constant c_CSR_WB_FMC_I2C : integer := 8;
constant c_CSR_WB_FMC_ADC_CORE : integer := 9;
constant c_CSR_WB_FMC_ONE_WIRE : integer := 10;
constant c_FMC_ONE_WIRE_NB : integer := 1;
------------------------------------------------------------------------------
-- Signals declaration
......@@ -380,7 +438,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal ddr_clk : std_logic;
signal ddr_clk_buf : std_logic;
-- LCLK from GN4124 used as system clock
-- LCLK from GN4124
signal l_clk : std_logic;
-- Reset
......@@ -388,29 +446,21 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal sys_rst : std_logic;
signal sys_rst_n : std_logic;
-- CSR wishbone bus (master)
signal wbm_adr : std_logic_vector(31 downto 0);
signal wbm_dat_i : std_logic_vector(31 downto 0);
signal wbm_dat_o : std_logic_vector(31 downto 0);
signal wbm_sel : std_logic_vector(3 downto 0);
signal wbm_cyc : std_logic;
signal wbm_stb : std_logic;
signal wbm_we : std_logic;
signal wbm_ack : std_logic;
signal wbm_stall : std_logic;
-- CSR wishbone bus (slaves)
signal wb_adr : std_logic_vector(31 downto 0);
signal wb_dat_i : std_logic_vector((32*c_CSR_WB_SLAVES_NB)-1 downto 0);
signal wb_dat_o : std_logic_vector(31 downto 0);
signal wb_sel : std_logic_vector(3 downto 0);
signal wb_cyc : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
signal wb_stb : std_logic;
signal wb_we : std_logic;
signal wb_ack : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
signal wb_stall : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
-- GN4124 DMA to DDR wishbone bus
-- Wishbone buse(s) from crossbar master port(s)
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
-- Wishbone buse(s) to crossbar slave port(s)
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
-- Wishbone address from GN4124 core (32-bit word address)
signal gn_wb_adr : std_logic_vector(31 downto 0);
-- Wishbone address from to DMA controller (32-bit word address)
signal dma_ctrl_wb_adr : std_logic_vector(31 downto 0);
-- GN4124 core DMA port to DDR wishbone bus
signal wb_dma_adr : std_logic_vector(31 downto 0);
signal wb_dma_dat_i : std_logic_vector(31 downto 0);
signal wb_dma_dat_o : std_logic_vector(31 downto 0);
......@@ -436,7 +486,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal dma_irq_p : std_logic_vector(1 downto 0);
signal irq_sources : std_logic_vector(31 downto 0);
signal irq_to_gn4124 : std_logic;
signal irq_sources_2_led : std_logic_vector(1 downto 0);
signal irq_sources_2_led : std_logic_vector(31 downto 0);
signal ddr_wr_fifo_empty : std_logic;
signal ddr_wr_fifo_empty_d : std_logic;
signal ddr_wr_fifo_empty_p : std_logic;
......@@ -483,14 +533,14 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal spi_ss_t : std_logic_vector(7 downto 0);
-- Mezzanine 1-wire
signal mezz_owr_pwren : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
signal mezz_owr_en : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
signal mezz_owr_i : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
signal mezz_owr_pwren : std_logic_vector(0 downto 0);
signal mezz_owr_en : std_logic_vector(0 downto 0);
signal mezz_owr_i : std_logic_vector(0 downto 0);
-- Carrier 1-wire
signal carrier_owr_pwren : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
signal carrier_owr_en : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
signal carrier_owr_i : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
signal carrier_owr_pwren : std_logic_vector(0 downto 0);
signal carrier_owr_en : std_logic_vector(0 downto 0);
signal carrier_owr_i : std_logic_vector(0 downto 0);
-- UTC core
signal trigger_p : std_logic;
......@@ -498,10 +548,13 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal acq_stop_p : std_logic;
signal acq_end_p : std_logic;
-- Tests
signal test_dpram_we : std_logic;
signal led_cnt : unsigned(26 downto 0);
signal led_pps : std_logic;
-- led pwm
signal led_pwm_update_cnt : unsigned(9 downto 0);
signal led_pwm_update : std_logic;
signal led_pwm_val : unsigned(16 downto 0);
signal led_pwm_val_down : std_logic;
signal led_pwm_cnt : unsigned(16 downto 0);
signal led_pwm : std_logic;
begin
......@@ -585,13 +638,12 @@ begin
sys_rst_n <= L_RST_N and sys_clk_pll_locked;
sys_rst <= not(sys_rst_n);
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
port map(
rst_n_a_i => L_RST_N,
rst_n_a_i => sys_rst_n,
status_o => gn4124_status,
-- P2L Direction Source Sync DDR related signals
p2l_clk_p_i => P2L_CLKp,
......@@ -623,26 +675,26 @@ begin
irq_p_o => GPIO(0),
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i => sys_clk_125,
dma_reg_adr_i => wb_adr,
dma_reg_dat_i => wb_dat_o,
dma_reg_sel_i => wb_sel,
dma_reg_stb_i => wb_stb,
dma_reg_we_i => wb_we,
dma_reg_cyc_i => wb_cyc(c_CSR_WB_DMA_CONFIG),
dma_reg_dat_o => wb_dat_i(c_CSR_WB_DMA_CONFIG * 32 + 31 downto c_CSR_WB_DMA_CONFIG * 32),
dma_reg_ack_o => wb_ack(c_CSR_WB_DMA_CONFIG),
dma_reg_stall_o => wb_stall(c_CSR_WB_DMA_CONFIG),
dma_reg_adr_i => dma_ctrl_wb_adr,
dma_reg_dat_i => cnx_master_out(c_SLAVE_DMA).dat,
dma_reg_sel_i => cnx_master_out(c_SLAVE_DMA).sel,
dma_reg_stb_i => cnx_master_out(c_SLAVE_DMA).stb,
dma_reg_we_i => cnx_master_out(c_SLAVE_DMA).we,
dma_reg_cyc_i => cnx_master_out(c_SLAVE_DMA).cyc,
dma_reg_dat_o => cnx_master_in(c_SLAVE_DMA).dat,
dma_reg_ack_o => cnx_master_in(c_SLAVE_DMA).ack,
dma_reg_stall_o => cnx_master_in(c_SLAVE_DMA).stall,
-- CSR wishbone interface (master pipelined)
csr_clk_i => sys_clk_125,
csr_adr_o => wbm_adr,
csr_dat_o => wbm_dat_o,
csr_sel_o => wbm_sel,
csr_stb_o => wbm_stb,
csr_we_o => wbm_we,
csr_cyc_o => wbm_cyc,
csr_dat_i => wbm_dat_i,
csr_ack_i => wbm_ack,
csr_stall_i => wbm_stall,
csr_adr_o => gn_wb_adr,
csr_dat_o => cnx_slave_in(c_MASTER_GENNUM).dat,
csr_sel_o => cnx_slave_in(c_MASTER_GENNUM).sel,
csr_stb_o => cnx_slave_in(c_MASTER_GENNUM).stb,
csr_we_o => cnx_slave_in(c_MASTER_GENNUM).we,
csr_cyc_o => cnx_slave_in(c_MASTER_GENNUM).cyc,
csr_dat_i => cnx_slave_out(c_MASTER_GENNUM).dat,
csr_ack_i => cnx_slave_out(c_MASTER_GENNUM).ack,
csr_stall_i => cnx_slave_out(c_MASTER_GENNUM).stall,
-- DMA wishbone interface (pipelined)
dma_clk_i => sys_clk_125,
dma_adr_o => wb_dma_adr,
......@@ -658,50 +710,38 @@ begin
p2l_pll_locked <= gn4124_status(0);
-- Convert 32-bit word address into byte address for crossbar
cnx_slave_in(c_MASTER_GENNUM).adr <= gn_wb_adr(29 downto 0) & "00";
-- Convert 32-bit byte address into word address for DMA controller
dma_ctrl_wb_adr <= "00" & cnx_master_out(c_SLAVE_DMA).adr(31 downto 2);
-- Unused wishbone signals
cnx_master_in(c_SLAVE_DMA).err <= '0';
cnx_master_in(c_SLAVE_DMA).rty <= '0';
cnx_master_in(c_SLAVE_DMA).int <= '0';
------------------------------------------------------------------------------
-- CSR wishbone address decoder
-- 0x00000 -> DMA configuration
-- 0x10000 -> Carrier SPI master
-- 0x20000 -> Carrier 1-wire master
-- 0x30000 -> Carrier CSR
-- 0x40000 -> UTC core
-- 0x50000 -> Interrupt controller
-- 0x60000 -> Mezzanine system managment I2C master
-- 0x70000 -> Mezzanine SPI master
-- 0x80000 -> Mezzanine I2C master
-- 0x90000 -> Mezzanine ADC core
-- 0xA0000 -> Mezzanine 1-wire master
-- CSR wishbone crossbar
------------------------------------------------------------------------------
cmp_csr_wb_addr_decoder : wb_addr_decoder
cmp_sdb_crossbar : xwb_sdb_crossbar
generic map (
g_WINDOW_SIZE => c_BAR0_APERTURE,
g_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB
)
g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_use_info => true,
g_info => c_SDB_INFO,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map (
-- GN4124 core clock and reset
clk_i => sys_clk_125,
rst_n_i => L_RST_N,
-- wishbone master interface
wbm_adr_i => wbm_adr,
wbm_dat_i => wbm_dat_o,
wbm_sel_i => wbm_sel,
wbm_stb_i => wbm_stb,
wbm_we_i => wbm_we,
wbm_cyc_i => wbm_cyc,
wbm_dat_o => wbm_dat_i,
wbm_ack_o => wbm_ack,
wbm_stall_o => wbm_stall,
-- wishbone slaves interface
wb_adr_o => wb_adr,
wb_dat_o => wb_dat_o,
wb_sel_o => wb_sel,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_cyc_o => wb_cyc,
wb_dat_i => wb_dat_i,
wb_ack_i => wb_ack,
wb_stall_i => wb_stall
);
clk_sys_i => sys_clk_125,
rst_n_i => sys_rst_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
------------------------------------------------------------------------------
-- Carrier SPI master
......@@ -713,10 +753,10 @@ begin
-- Carrier 1-wire master
-- DS18B20 (thermometer + unique ID)
------------------------------------------------------------------------------
cmp_carrier_onewire : wb_onewire_master
cmp_carrier_onewire : xwb_onewire_master
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => WORD,
g_address_granularity => BYTE,
g_num_ports => 1,
g_ow_btp_normal => "5.0",
g_ow_btp_overdrive => "1.0"
......@@ -725,15 +765,9 @@ begin
clk_sys_i => sys_clk_125,
rst_n_i => sys_rst_n,
wb_cyc_i => wb_cyc(c_CSR_WB_CARRIER_ONE_WIRE),
wb_sel_i => wb_sel,
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_adr_i => wb_adr(2 downto 0),
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(c_CSR_WB_CARRIER_ONE_WIRE * 32 + 31 downto 32 * c_CSR_WB_CARRIER_ONE_WIRE),
wb_ack_o => wb_ack(c_CSR_WB_CARRIER_ONE_WIRE),
wb_int_o => open,
slave_i => cnx_master_out(c_SLAVE_ONEWIRE),
slave_o => cnx_master_in(c_SLAVE_ONEWIRE),
desc_o => open,
owr_pwren_o => carrier_owr_pwren,
owr_en_o => carrier_owr_en,
......@@ -743,10 +777,6 @@ begin
carrier_one_wire_b <= '0' when carrier_owr_en(0) = '1' else 'Z';
carrier_owr_i(0) <= carrier_one_wire_b;
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_CARRIER_ONE_WIRE) <= '0';
------------------------------------------------------------------------------
-- Carrier CSR
-- Carrier type and PCB version
......@@ -758,19 +788,17 @@ begin
port map(
rst_n_i => sys_rst_n,
wb_clk_i => sys_clk_125,
wb_addr_i => wb_adr(2 downto 0),
wb_data_i => wb_dat_o,
wb_data_o => wb_dat_i(c_CSR_WB_CARRIER_CSR * 32 + 31 downto c_CSR_WB_CARRIER_CSR * 32),
wb_cyc_i => wb_cyc(c_CSR_WB_CARRIER_CSR),
wb_sel_i => wb_sel,
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(c_CSR_WB_CARRIER_CSR),
wb_addr_i => cnx_master_out(c_SLAVE_SPEC_CSR).adr(3 downto 2), -- cnx_master_out.adr is byte address
wb_data_i => cnx_master_out(c_SLAVE_SPEC_CSR).dat,
wb_data_o => cnx_master_in(c_SLAVE_SPEC_CSR).dat,
wb_cyc_i => cnx_master_out(c_SLAVE_SPEC_CSR).cyc,
wb_sel_i => cnx_master_out(c_SLAVE_SPEC_CSR).sel,
wb_stb_i => cnx_master_out(c_SLAVE_SPEC_CSR).stb,
wb_we_i => cnx_master_out(c_SLAVE_SPEC_CSR).we,
wb_ack_o => cnx_master_in(c_SLAVE_SPEC_CSR).ack,
carrier_csr_carrier_pcb_rev_i => pcb_ver_i,
carrier_csr_carrier_reserved_i => X"000",
carrier_csr_carrier_type_i => c_CARRIER_TYPE,
carrier_csr_bitstream_type_i => c_BITSTREAM_TYPE,
carrier_csr_bitstream_date_i => c_BITSTREAM_DATE,
carrier_csr_stat_fmc_pres_i => prsnt_m2c_n_i,
carrier_csr_stat_p2l_pll_lck_i => p2l_pll_locked,
carrier_csr_stat_sys_pll_lck_i => sys_clk_pll_locked,
......@@ -782,22 +810,15 @@ begin
carrier_csr_ctrl_reserved_o => open
);
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_CARRIER_CSR) <= '0';
gen_irq_led : for I in 0 to 1 generate
cmp_irq_led : gc_extend_pulse
generic map (
g_width => 5000000)
port map (
clk_i => sys_clk_125,
rst_n_i => sys_rst_n,
pulse_i => irq_sources(I),
extended_o => irq_sources_2_led(I));
end generate gen_irq_led;
-- Unused wishbone signals
cnx_master_in(c_SLAVE_SPEC_CSR).err <= '0';
cnx_master_in(c_SLAVE_SPEC_CSR).rty <= '0';
cnx_master_in(c_SLAVE_SPEC_CSR).stall <= '0';
cnx_master_in(c_SLAVE_SPEC_CSR).int <= '0';
led_red_o <= led_red or irq_sources_2_led(0);
led_green_o <= led_green or irq_sources_2_led(1);
-- SPEC front panel leds
led_red_o <= led_red;
led_green_o <= led_green;
------------------------------------------------------------------------------
-- UTC core
......@@ -812,18 +833,21 @@ begin
acq_stop_p_i => acq_stop_p,
acq_end_p_i => acq_end_p,
wb_adr_i => wb_adr(4 downto 0),
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(c_CSR_WB_UTC_CORE * 32 + 31 downto c_CSR_WB_UTC_CORE * 32),
wb_cyc_i => wb_cyc(c_CSR_WB_UTC_CORE),
wb_sel_i => wb_sel,
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(c_CSR_WB_UTC_CORE)
wb_adr_i => cnx_master_out(c_SLAVE_UTC).adr(6 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_SLAVE_UTC).dat,
wb_dat_o => cnx_master_in(c_SLAVE_UTC).dat,
wb_cyc_i => cnx_master_out(c_SLAVE_UTC).cyc,
wb_sel_i => cnx_master_out(c_SLAVE_UTC).sel,
wb_stb_i => cnx_master_out(c_SLAVE_UTC).stb,
wb_we_i => cnx_master_out(c_SLAVE_UTC).we,
wb_ack_o => cnx_master_in(c_SLAVE_UTC).ack
);
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_UTC_CORE) <= '0';
-- Unused wishbone signals
cnx_master_in(c_SLAVE_UTC).err <= '0';
cnx_master_in(c_SLAVE_UTC).rty <= '0';
cnx_master_in(c_SLAVE_UTC).stall <= '0';
cnx_master_in(c_SLAVE_UTC).int <= '0';
------------------------------------------------------------------------------
-- Interrupt controller
......@@ -837,18 +861,21 @@ begin
irq_p_o => irq_to_gn4124,
wb_adr_i => wb_adr(1 downto 0),
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(c_CSR_WB_IRQ_CTRL * 32 + 31 downto c_CSR_WB_IRQ_CTRL * 32),
wb_cyc_i => wb_cyc(c_CSR_WB_IRQ_CTRL),
wb_sel_i => wb_sel,
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(c_CSR_WB_IRQ_CTRL)
wb_adr_i => cnx_master_out(c_SLAVE_INT).adr(3 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_SLAVE_INT).dat,
wb_dat_o => cnx_master_in(c_SLAVE_INT).dat,
wb_cyc_i => cnx_master_out(c_SLAVE_INT).cyc,
wb_sel_i => cnx_master_out(c_SLAVE_INT).sel,
wb_stb_i => cnx_master_out(c_SLAVE_INT).stb,
wb_we_i => cnx_master_out(c_SLAVE_INT).we,
wb_ack_o => cnx_master_in(c_SLAVE_INT).ack
);
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_IRQ_CTRL) <= '0';
-- Unused wishbone signals
cnx_master_in(c_SLAVE_INT).err <= '0';
cnx_master_in(c_SLAVE_INT).rty <= '0';
cnx_master_in(c_SLAVE_INT).stall <= '0';
cnx_master_in(c_SLAVE_INT).int <= '0';
-- IRQ sources
-- 0 -> End of DMA transfer
......@@ -886,31 +913,38 @@ begin
acq_end_irq_p <= ddr_wr_fifo_empty_p and acq_end;
-- just forward irq pulses for test
--irq_to_gn4124 <= dma_irq(1) or dma_irq(0);
-- IRQ leds
gen_irq_led : for I in 0 to irq_sources'length-1 generate
cmp_irq_led : gc_extend_pulse
generic map (
g_width => 5000000)
port map (
clk_i => sys_clk_125,
rst_n_i => sys_rst_n,
pulse_i => irq_sources(I),
extended_o => irq_sources_2_led(I));
end generate gen_irq_led;
aux_leds_o(1) <= not(irq_sources_2_led(2));
aux_leds_o(2) <= not(irq_sources_2_led(3));
aux_leds_o(3) <= not(irq_sources_2_led(0));
------------------------------------------------------------------------------
-- Mezzanine system managment I2C master
-- Access to mezzanine EEPROM
------------------------------------------------------------------------------
cmp_fmc_sys_i2c : wb_i2c_master
cmp_fmc_sys_i2c : xwb_i2c_master
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => WORD
g_address_granularity => BYTE
)
port map (
clk_sys_i => sys_clk_125,
rst_n_i => sys_rst_n,
wb_adr_i => wb_adr(4 downto 0),
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(c_CSR_WB_FMC_SYS_I2C * 32 + 31 downto 32 * c_CSR_WB_FMC_SYS_I2C),
wb_we_i => wb_we,
wb_stb_i => wb_stb,
wb_sel_i => wb_sel,
wb_cyc_i => wb_cyc(c_CSR_WB_FMC_SYS_I2C),
wb_ack_o => wb_ack(c_CSR_WB_FMC_SYS_I2C),
wb_int_o => open,
slave_i => cnx_master_out(c_SLAVE_FMC_SYS_I2C),
slave_o => cnx_master_in(c_SLAVE_FMC_SYS_I2C),
desc_o => open,
scl_pad_i => sys_scl_in,
scl_pad_o => sys_scl_out,
......@@ -920,9 +954,6 @@ begin
sda_padoen_o => sys_sda_oe_n
);
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_FMC_SYS_I2C) <= '0';
-- Tri-state buffer for SDA and SCL
sys_scl_b <= sys_scl_out when sys_scl_oe_n = '0' else 'Z';
sys_scl_in <= sys_scl_b;
......@@ -935,25 +966,18 @@ begin
-- Offset DACs control
-- ADC control
------------------------------------------------------------------------------
cmp_fmc_spi : wb_spi
cmp_fmc_spi : xwb_spi
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => WORD
g_address_granularity => BYTE
)
port map (
clk_sys_i => sys_clk_125,
rst_n_i => sys_rst_n,
wb_adr_i => wb_adr(4 downto 0),
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(c_CSR_WB_FMC_SPI * 32 + 31 downto c_CSR_WB_FMC_SPI * 32),
wb_sel_i => wb_sel,
wb_stb_i => wb_stb,
wb_cyc_i => wb_cyc(c_CSR_WB_FMC_SPI),
wb_we_i => wb_we,
wb_ack_o => wb_ack(c_CSR_WB_FMC_SPI),
wb_err_o => open,
wb_int_o => open,
slave_i => cnx_master_out(c_SLAVE_FMC_SPI),
slave_o => cnx_master_in(c_SLAVE_FMC_SPI),
desc_o => open,
pad_cs_o => spi_ss_t,
pad_sclk_o => spi_sck_o,
......@@ -961,9 +985,6 @@ begin
pad_miso_i => spi_din_t(spi_din_t'left)
);
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_FMC_SPI) <= '0';
-- Assign slave select lines
spi_cs_adc_n_o <= spi_ss_t(0);
spi_cs_dac1_n_o <= spi_ss_t(1);
......@@ -989,24 +1010,18 @@ begin
--
-- Note: I2C registers are 8-bit wide, but accessed as 32-bit registers
------------------------------------------------------------------------------
cmp_fmc_i2c : wb_i2c_master
cmp_fmc_i2c : xwb_i2c_master
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => WORD
g_address_granularity => BYTE
)
port map (
clk_sys_i => sys_clk_125,
rst_n_i => sys_rst_n,
wb_adr_i => wb_adr(4 downto 0),
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(c_CSR_WB_FMC_I2C * 32 + 31 downto 32 * c_CSR_WB_FMC_I2C),
wb_we_i => wb_we,
wb_stb_i => wb_stb,
wb_sel_i => wb_sel,
wb_cyc_i => wb_cyc(c_CSR_WB_FMC_I2C),
wb_ack_o => wb_ack(c_CSR_WB_FMC_I2C),
wb_int_o => open,
slave_i => cnx_master_out(c_SLAVE_FMC_I2C),
slave_o => cnx_master_in(c_SLAVE_FMC_I2C),
desc_o => open,
scl_pad_i => si570_scl_in,
scl_pad_o => si570_scl_out,
......@@ -1016,9 +1031,6 @@ begin
sda_padoen_o => si570_sda_oe_n
);
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_FMC_I2C) <= '0';
-- Tri-state buffer for SDA and SCL
si570_scl_b <= si570_scl_out when si570_scl_oe_n = '0' else 'Z';
si570_scl_in <= si570_scl_b;
......@@ -1034,18 +1046,21 @@ begin
-- ADC core control and status
------------------------------------------------------------------------------
cmp_fmc_adc_100Ms_core : fmc_adc_100Ms_core
generic map (
g_multishot_ram_size => 2048
)
port map(
sys_clk_i => sys_clk_125,
sys_rst_n_i => sys_rst_n,
wb_csr_adr_i => wb_adr(4 downto 0),
wb_csr_dat_i => wb_dat_o,
wb_csr_dat_o => wb_dat_i(c_CSR_WB_FMC_ADC_CORE * 32 + 31 downto c_CSR_WB_FMC_ADC_CORE * 32),
wb_csr_cyc_i => wb_cyc(c_CSR_WB_FMC_ADC_CORE),
wb_csr_sel_i => wb_sel,
wb_csr_stb_i => wb_stb,
wb_csr_we_i => wb_we,
wb_csr_ack_o => wb_ack(c_CSR_WB_FMC_ADC_CORE),
wb_csr_adr_i => cnx_master_out(c_SLAVE_FMC_ADC).adr(6 downto 2), -- cnx_master_out.adr is byte address
wb_csr_dat_i => cnx_master_out(c_SLAVE_FMC_ADC).dat,
wb_csr_dat_o => cnx_master_in(c_SLAVE_FMC_ADC).dat,
wb_csr_cyc_i => cnx_master_out(c_SLAVE_FMC_ADC).cyc,
wb_csr_sel_i => cnx_master_out(c_SLAVE_FMC_ADC).sel,
wb_csr_stb_i => cnx_master_out(c_SLAVE_FMC_ADC).stb,
wb_csr_we_i => cnx_master_out(c_SLAVE_FMC_ADC).we,
wb_csr_ack_o => cnx_master_in(c_SLAVE_FMC_ADC).ack,
wb_ddr_clk_i => sys_clk_125,
wb_ddr_adr_o => wb_ddr_adr,
......@@ -1075,8 +1090,8 @@ begin
adc_outb_n_i => adc_outb_n_i,
gpio_dac_clr_n_o => gpio_dac_clr_n_o,
gpio_led_acq_o => gpio_led_power_o,
gpio_led_trig_o => gpio_led_trigger_o,
gpio_led_acq_o => gpio_led_acq_o,
gpio_led_trig_o => gpio_led_trig_o,
gpio_ssr_ch1_o => gpio_ssr_ch1_o,
gpio_ssr_ch2_o => gpio_ssr_ch2_o,
gpio_ssr_ch3_o => gpio_ssr_ch3_o,
......@@ -1084,34 +1099,31 @@ begin
gpio_si570_oe_o => gpio_si570_oe_o
);
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_FMC_ADC_CORE) <= '0';
-- Unused wishbone signals
cnx_master_in(c_SLAVE_FMC_ADC).err <= '0';
cnx_master_in(c_SLAVE_FMC_ADC).rty <= '0';
cnx_master_in(c_SLAVE_FMC_ADC).stall <= '0';
cnx_master_in(c_SLAVE_FMC_ADC).int <= '0';
------------------------------------------------------------------------------
-- Mezzanine 1-wire master
-- DS18B20 (thermometer + unique ID)
------------------------------------------------------------------------------
cmp_fmc_onewire : wb_onewire_master
cmp_fmc_onewire : xwb_onewire_master
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => WORD,
g_num_ports => 1,
g_ow_btp_normal => "5.0",
g_ow_btp_overdrive => "1.0"
g_address_granularity => BYTE,
g_num_ports => 1,
g_ow_btp_normal => "5.0",
g_ow_btp_overdrive => "1.0"
)
port map(
clk_sys_i => sys_clk_125,
rst_n_i => sys_rst_n,
wb_cyc_i => wb_cyc(c_CSR_WB_FMC_ONE_WIRE),
wb_sel_i => wb_sel,
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_adr_i => wb_adr(2 downto 0),
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(c_CSR_WB_FMC_ONE_WIRE * 32 + 31 downto 32 * c_CSR_WB_FMC_ONE_WIRE),
wb_ack_o => wb_ack(c_CSR_WB_FMC_ONE_WIRE),
wb_int_o => open,
slave_i => cnx_master_out(c_SLAVE_FMC_ONEWIRE),
slave_o => cnx_master_in(c_SLAVE_FMC_ONEWIRE),
desc_o => open,
owr_pwren_o => mezz_owr_pwren,
owr_en_o => mezz_owr_en,
......@@ -1121,9 +1133,6 @@ begin
mezz_one_wire_b <= '0' when mezz_owr_en(0) = '1' else 'Z';
mezz_owr_i(0) <= mezz_one_wire_b;
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_FMC_ONE_WIRE) <= '0';
------------------------------------------------------------------------------
-- DMA wishbone bus slaves
-- -> DDR3 controller
......@@ -1166,28 +1175,6 @@ begin
ddr3_rzq_b => DDR3_RZQ,
ddr3_zio_b => DDR3_ZIO,
--wb0_clk_i => '0',
--wb0_sel_i => "0000",
--wb0_cyc_i => '0',
--wb0_stb_i => '0',
--wb0_we_i => '0',
--wb0_addr_i => X"0000000",
--wb0_data_i => X"00000000",
--wb0_data_o => open,
--wb0_ack_o => open,
--wb0_stall_o => open,
--wb1_clk_i => '0',
--wb1_sel_i => "0000",
--wb1_cyc_i => '0',
--wb1_stb_i => '0',
--wb1_we_i => '0',
--wb1_addr_i => X"0000000",
--wb1_data_i => X"00000000",
--wb1_data_o => open,
--wb1_ack_o => open,
--wb1_stall_o => open);
wb0_clk_i => sys_clk_125,
wb0_sel_i => wb_ddr_sel,
wb0_cyc_i => wb_ddr_cyc,
......@@ -1240,83 +1227,76 @@ begin
ddr3_calib_done <= ddr3_status(0);
--wb_ddr_stall <= '0';
--test_dpram_we <= wb_ddr_we and wb_ddr_stb and wb_ddr_cyc;
--p_test_dpram_wr_ack : process (sys_clk_250)
--begin
-- if rising_edge(sys_clk_250) then
-- if sys_rst_n = '0' then
-- wb_ddr_ack <= '0';
-- elsif wb_ddr_cyc = '1' and wb_ddr_stb = '1' then
-- wb_ddr_ack <= '1';
-- else
-- wb_ddr_ack <= '0';
-- end if;
-- end if;
--end process p_test_dpram_wr_ack;
--cmp_test_dpram : test_dpram
-- port map(
-- clka => sys_clk_250,
-- wea(0) => test_dpram_we, --: in std_logic_vector(0 downto 0);
-- addra => wb_ddr_adr(9 downto 0), --: in std_logic_vector(9 downto 0);
-- dina => wb_ddr_dat_o, --: in std_logic_vector(31 downto 0);
-- clkb => sys_clk_125,
-- addrb => wb_dma_adr(9 downto 0), --: in std_logic_vector(9 downto 0);
-- doutb => wb_dma_dat_i); --: out std_logic_vector(31 downto 0));
--p_test_dpram_rd_ack : process (sys_clk_125)
--begin
-- if rising_edge(sys_clk_125) then
-- if sys_rst_n = '0' then
-- wb_dma_ack <= '0';
-- elsif wb_dma_cyc = '1' and wb_dma_stb = '1' then
-- wb_dma_ack <= '1';
-- else
-- wb_dma_ack <= '0';
-- end if;
-- end if;
--end process p_test_dpram_rd_ack;
--wb_dma_stall <= '0';
------------------------------------------------------------------------------
-- Assign unused outputs
------------------------------------------------------------------------------
GPIO(1) <= '0';
GPIO(1) <= '0'; -- connection to GN4124
------------------------------------------------------------------------------
-- Blink auxiliary LEDs
-- FPGA programmed led (heart beat)
------------------------------------------------------------------------------
p_led_cnt : process (sys_clk_125)
p_led_pwn_update_cnt : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if (sys_rst_n = '0') then
led_cnt <= (others => '0');
led_pps <= '0';
elsif (led_cnt = X"773593F") then
led_cnt <= (others => '0');
led_pps <= not(led_pps);
led_pwm_update_cnt <= (others => '0');
led_pwm_update <= '0';
elsif (led_pwm_update_cnt = to_unsigned(954, 10)) then
led_pwm_update_cnt <= (others => '0');
led_pwm_update <= '1';
else
led_cnt <= led_cnt + 1;
led_pwm_update_cnt <= led_pwm_update_cnt + 1;
led_pwm_update <= '0';
end if;
end if;
end process p_led_cnt;
end process p_led_pwn_update_cnt;
p_led_blink : process (sys_clk_125)
p_led_pwn_val : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if sys_rst_n = '0' then
aux_leds_o <= X"5";
elsif led_pps = '1' then
aux_leds_o <= X"A";
if (sys_rst_n = '0') then
led_pwm_val <= (others => '0');
led_pwm_val_down <= '0';
elsif (led_pwm_update = '1') then
if led_pwm_val_down = '1' then
if led_pwm_val = X"100" then
led_pwm_val_down <= '0';
end if;
led_pwm_val <= led_pwm_val - 1;
else
if led_pwm_val = X"1FFFE" then
led_pwm_val_down <= '1';
end if;
led_pwm_val <= led_pwm_val + 1;
end if;
end if;
end if;
end process p_led_pwn_val;
p_led_pwn_cnt : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if (sys_rst_n = '0') then
led_pwm_cnt <= (others => '0');
else
aux_leds_o <= X"5";
led_pwm_cnt <= led_pwm_cnt + 1;
end if;
end if;
end process p_led_pwn_cnt;
p_led_pwn : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if (sys_rst_n = '0') then
led_pwm <= '0';
elsif (led_pwm_cnt = 0) then
led_pwm <= '1';
elsif (led_pwm_cnt = led_pwm_val) then
led_pwm <= '0';
end if;
end if;
end process p_led_blink;
end process p_led_pwn;
aux_leds_o(0) <= led_pwm;
end rtl;
hdl/spec/sim/Makefile
View file @ 2f92c67d
......@@ -16,12 +16,34 @@ VERILOG_SRC := sim_models/2048Mb_ddr3/ddr3.v \
../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v \
../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v \
../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v \
../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v \
VERILOG_OBJ := work/ddr3/.ddr3_v \
work/sockit_owm/.sockit_owm_v \
work/spi_clgen/.spi_clgen_v \
work/spi_shift/.spi_shift_v \
work/spi_top/.spi_top_v \
work/lm32_allprofiles/.lm32_allprofiles_v \
work/lm32_mc_arithmetic/.lm32_mc_arithmetic_v \
work/jtag_cores/.jtag_cores_v \
work/lm32_adder/.lm32_adder_v \
work/lm32_addsub/.lm32_addsub_v \
work/lm32_dp_ram/.lm32_dp_ram_v \
work/lm32_logic_op/.lm32_logic_op_v \
work/lm32_ram/.lm32_ram_v \
work/lm32_shifter/.lm32_shifter_v \
work/lm32_multiplier/.lm32_multiplier_v \
work/jtag_tap/.jtag_tap_v \
VHDL_SRC := testbench/util.vhd \
testbench/textutil.vhd \
......@@ -36,41 +58,45 @@ testbench/cmd_router1.vhd \
../ip_cores/monostable/monostable_rtl.vhd \
../ip_cores/utils/utils_pkg.vhd \
../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd \
../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../rtl/carrier_csr.vhd \
../rtl/utc_core_regs.vhd \
../rtl/utc_core.vhd \
../rtl/irq_controller_regs.vhd \
../rtl/irq_controller.vhd \
../../adc/rtl/fmc_adc_100Ms_core_pkg.vhd \
testbench/gn412x_bfm.vhd \
../../adc/rtl/fmc_adc_100Ms_core.vhd \
../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../adc/rtl/fmc_adc_100Ms_csr.vhd \
../../adc/rtl/offset_gain_s.vhd \
../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd \
../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd \
../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/l2p_arbiter.vhd \
../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/p2l_decode32.vhd \
../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/p2l_dma_master.vhd \
../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/wbmaster32.vhd \
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../ip_cores/gn4124-core/trunk/hdl/common/rtl/dummy_stat_regs.vhd \
../ip_cores/gn4124-core/trunk/hdl/common/rtl/wb_addr_decoder.vhd \
../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../rtl/sdb_meta_pkg.vhd \
../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../ip_cores/general-cores/modules/common/gc_reset.vhd \
../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/l2p_dma_master.vhd \
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../ip_cores/general-cores/modules/genrams/xilinx/generic_async_fifo.vhd \
../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd \
../ip_cores/general-cores/modules/common/gc_wfifo.vhd \
../../adc/rtl/fmc_adc_100Ms_core.vhd \
../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd \
../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../ip_cores/general-cores/modules/genrams/xilinx/generic_sync_fifo.vhd \
../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_async_fifo.vhd \
../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd \
../ip_cores/general-cores/modules/genrams/xilinx/sim_stub/dummy.vhd \
../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
......@@ -79,63 +105,70 @@ testbench/gn412x_bfm.vhd \
../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_dec.vhd \
../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_enc.vhd \
../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_arb.vhd \
../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_msel.vhd \
../ip_cores/general-cores/modules/wishbone/wb_conmax/wbconmax_pkg.vhd \
../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_slave_if.vhd \
../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_master_if.vhd \
../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_rf.vhd \
../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_top.vhd \
../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../ip_cores/general-cores/modules/wishbone/wb_uart/uart_wb_slave.vhd \
../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart.vhd \
../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd \
../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart_slave.vhd \
../ip_cores/ddr3-sp6-core/trunk/hdl/rtl/ddr3_ctrl.vhd \
../ip_cores/ddr3-sp6-core/trunk/hdl/rtl/ddr3_ctrl_wb.vhd \
../ip_cores/ddr3-sp6-core/trunk/hdl/rtl/ddr3_ctrl_wrapper.vhd \
../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd \
../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd \
../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd \
../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd \
../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd \
../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd \
../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd \
../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd \
../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd \
../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd \
../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd \
../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd \
../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd \
../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd \
../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd \
../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd \
../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd \
../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd \
../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd \
../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd \
../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd \
../rtl/spec_top_fmc_adc_100Ms.vhd \
../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/ddr3_ctrl_bank3_32b_32b.vhd \
../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/iodrp_controller.vhd \
../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/iodrp_mcb_controller.vhd \
../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/mcb_raw_wrapper.vhd \
../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/mcb_soft_calibration_top.vhd \
../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/mcb_soft_calibration.vhd \
../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/memc3_infrastructure.vhd \
../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/memc3_wrapper.vhd \
../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/ddr3_ctrl_bank3_64b_32b.vhd \
../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd \
../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd \
../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd \
../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd \
../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd \
../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd \
../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd \
../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd \
../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/dma_controller.vhd \
../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd \
../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/p2l_des.vhd \
../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd \
../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd \
../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd \
../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd \
../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd \
../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd \
../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd \
../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd \
../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd \
../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd \
VHDL_OBJ := work/util/.util_vhd \
work/textutil/.textutil_vhd \
......@@ -150,41 +183,45 @@ work/adc_serdes/.adc_serdes_vhd \
work/monostable_rtl/.monostable_rtl_vhd \
work/utils_pkg/.utils_pkg_vhd \
work/ext_pulse_sync_rtl/.ext_pulse_sync_rtl_vhd \
work/gencores_pkg/.gencores_pkg_vhd \
work/genram_pkg/.genram_pkg_vhd \
work/carrier_csr/.carrier_csr_vhd \
work/utc_core_regs/.utc_core_regs_vhd \
work/utc_core/.utc_core_vhd \
work/irq_controller_regs/.irq_controller_regs_vhd \
work/irq_controller/.irq_controller_vhd \
work/fmc_adc_100Ms_core_pkg/.fmc_adc_100Ms_core_pkg_vhd \
work/gn412x_bfm/.gn412x_bfm_vhd \
work/fmc_adc_100Ms_core/.fmc_adc_100Ms_core_vhd \
work/wishbone_pkg/.wishbone_pkg_vhd \
work/gencores_pkg/.gencores_pkg_vhd \
work/fmc_adc_100Ms_csr/.fmc_adc_100Ms_csr_vhd \
work/offset_gain_s/.offset_gain_s_vhd \
work/gn4124_core_pkg/.gn4124_core_pkg_vhd \
work/dma_controller_wb_slave/.dma_controller_wb_slave_vhd \
work/l2p_arbiter/.l2p_arbiter_vhd \
work/genram_pkg/.genram_pkg_vhd \
work/p2l_decode32/.p2l_decode32_vhd \
work/p2l_dma_master/.p2l_dma_master_vhd \
work/wbmaster32/.wbmaster32_vhd \
work/dummy_ctrl_regs/.dummy_ctrl_regs_vhd \
work/dummy_stat_regs/.dummy_stat_regs_vhd \
work/wb_addr_decoder/.wb_addr_decoder_vhd \
work/wishbone_pkg/.wishbone_pkg_vhd \
work/sdb_meta_pkg/.sdb_meta_pkg_vhd \
work/gc_crc_gen/.gc_crc_gen_vhd \
work/gc_moving_average/.gc_moving_average_vhd \
work/gc_extend_pulse/.gc_extend_pulse_vhd \
work/gc_delay_gen/.gc_delay_gen_vhd \
work/gc_dual_pi_controller/.gc_dual_pi_controller_vhd \
work/gc_reset/.gc_reset_vhd \
work/gc_serial_dac/.gc_serial_dac_vhd \
work/gc_sync_ffs/.gc_sync_ffs_vhd \
work/l2p_dma_master/.l2p_dma_master_vhd \
work/gc_arbitrated_mux/.gc_arbitrated_mux_vhd \
work/gc_pulse_synchronizer/.gc_pulse_synchronizer_vhd \
work/gc_frequency_meter/.gc_frequency_meter_vhd \
work/gc_dual_clock_ram/.gc_dual_clock_ram_vhd \
work/gc_wfifo/.gc_wfifo_vhd \
work/fmc_adc_100Ms_core/.fmc_adc_100Ms_core_vhd \
work/memory_loader_pkg/.memory_loader_pkg_vhd \
work/generic_shiftreg_fifo/.generic_shiftreg_fifo_vhd \
work/ddr3_ctrl_pkg/.ddr3_ctrl_pkg_vhd \
work/generic_async_fifo/.generic_async_fifo_vhd \
work/generic_dpram/.generic_dpram_vhd \
work/generic_dpram_sameclock/.generic_dpram_sameclock_vhd \
work/generic_dpram_dualclock/.generic_dpram_dualclock_vhd \
work/generic_spram/.generic_spram_vhd \
work/generic_async_fifo/.generic_async_fifo_vhd \
work/generic_sync_fifo/.generic_sync_fifo_vhd \
fifo_generator_v6_1/dummy/.dummy_vhd \
work/wb_async_bridge/.wb_async_bridge_vhd \
work/xwb_async_bridge/.xwb_async_bridge_vhd \
work/wb_onewire_master/.wb_onewire_master_vhd \
work/xwb_onewire_master/.xwb_onewire_master_vhd \
work/i2c_master_bit_ctrl/.i2c_master_bit_ctrl_vhd \
......@@ -193,56 +230,63 @@ work/i2c_master_top/.i2c_master_top_vhd \
work/wb_i2c_master/.wb_i2c_master_vhd \
work/xwb_i2c_master/.xwb_i2c_master_vhd \
work/xwb_bus_fanout/.xwb_bus_fanout_vhd \
work/wb_conmax_pri_dec/.wb_conmax_pri_dec_vhd \
work/wb_conmax_pri_enc/.wb_conmax_pri_enc_vhd \
work/wb_conmax_arb/.wb_conmax_arb_vhd \
work/wb_conmax_msel/.wb_conmax_msel_vhd \
work/wbconmax_pkg/.wbconmax_pkg_vhd \
work/wb_conmax_slave_if/.wb_conmax_slave_if_vhd \
work/wb_conmax_master_if/.wb_conmax_master_if_vhd \
work/wb_conmax_rf/.wb_conmax_rf_vhd \
work/wb_conmax_top/.wb_conmax_top_vhd \
work/xwb_dpram/.xwb_dpram_vhd \
work/wb_gpio_port/.wb_gpio_port_vhd \
work/xwb_gpio_port/.xwb_gpio_port_vhd \
work/wb_tics/.wb_tics_vhd \
work/xwb_tics/.xwb_tics_vhd \
work/uart_async_rx/.uart_async_rx_vhd \
work/uart_async_tx/.uart_async_tx_vhd \
work/uart_baud_gen/.uart_baud_gen_vhd \
work/uart_wb_slave/.uart_wb_slave_vhd \
work/simple_uart_pkg/.simple_uart_pkg_vhd \
work/simple_uart_wb/.simple_uart_wb_vhd \
work/wb_simple_uart/.wb_simple_uart_vhd \
work/xwb_simple_uart/.xwb_simple_uart_vhd \
work/vic_prio_enc/.vic_prio_enc_vhd \
work/wbgen2_pkg/.wbgen2_pkg_vhd \
work/wb_vic/.wb_vic_vhd \
work/xwb_vic/.xwb_vic_vhd \
work/wb_spi/.wb_spi_vhd \
work/xwb_spi/.xwb_spi_vhd \
work/wb_virtual_uart/.wb_virtual_uart_vhd \
work/wbgen2_pkg/.wbgen2_pkg_vhd \
work/sdb_rom/.sdb_rom_vhd \
work/xwb_crossbar/.xwb_crossbar_vhd \
work/xwb_sdb_crossbar/.xwb_sdb_crossbar_vhd \
work/xwb_lm32/.xwb_lm32_vhd \
work/wb_slave_adapter/.wb_slave_adapter_vhd \
work/xloader_registers_pkg/.xloader_registers_pkg_vhd \
work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd \
work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd \
work/xloader_wb/.xloader_wb_vhd \
work/xwb_clock_crossing/.xwb_clock_crossing_vhd \
work/xwb_dma/.xwb_dma_vhd \
work/wb_serial_lcd/.wb_serial_lcd_vhd \
work/wbgen2_dpssram/.wbgen2_dpssram_vhd \
work/wbgen2_eic/.wbgen2_eic_vhd \
work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd \
work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd \
work/wb_virtual_uart_slave/.wb_virtual_uart_slave_vhd \
work/wb_slave_vic/.wb_slave_vic_vhd \
work/ddr3_ctrl/.ddr3_ctrl_vhd \
work/ddr3_ctrl_wb/.ddr3_ctrl_wb_vhd \
work/ddr3_ctrl_wrapper_pkg/.ddr3_ctrl_wrapper_pkg_vhd \
work/ddr3_ctrl_wrapper/.ddr3_ctrl_wrapper_vhd \
work/spec_top_fmc_adc_100Ms/.spec_top_fmc_adc_100Ms_vhd \
work/ddr3_ctrl_bank3_32b_32b/.ddr3_ctrl_bank3_32b_32b_vhd \
work/iodrp_controller/.iodrp_controller_vhd \
work/iodrp_mcb_controller/.iodrp_mcb_controller_vhd \
work/mcb_raw_wrapper/.mcb_raw_wrapper_vhd \
work/mcb_soft_calibration_top/.mcb_soft_calibration_top_vhd \
work/mcb_soft_calibration/.mcb_soft_calibration_vhd \
work/gn4124_core_pkg/.gn4124_core_pkg_vhd \
work/ddr3_ctrl_spec_bank3_64b_32b/.ddr3_ctrl_spec_bank3_64b_32b_vhd \
work/memc3_infrastructure/.memc3_infrastructure_vhd \
work/memc3_wrapper/.memc3_wrapper_vhd \
work/ddr3_ctrl_bank3_64b_32b/.ddr3_ctrl_bank3_64b_32b_vhd \
work/iodrp_controller/.iodrp_controller_vhd \
work/iodrp_mcb_controller/.iodrp_mcb_controller_vhd \
work/mcb_raw_wrapper/.mcb_raw_wrapper_vhd \
work/mcb_soft_calibration_top/.mcb_soft_calibration_top_vhd \
work/mcb_soft_calibration/.mcb_soft_calibration_vhd \
work/memc3_infrastructure/.memc3_infrastructure_vhd \
work/memc3_wrapper/.memc3_wrapper_vhd \
work/gn4124_core/.gn4124_core_vhd \
work/dma_controller/.dma_controller_vhd \
work/dma_controller_wb_slave/.dma_controller_wb_slave_vhd \
work/l2p_arbiter/.l2p_arbiter_vhd \
work/l2p_dma_master/.l2p_dma_master_vhd \
work/p2l_decode32/.p2l_decode32_vhd \
work/p2l_dma_master/.p2l_dma_master_vhd \
work/wbmaster32/.wbmaster32_vhd \
work/gn4124_core/.gn4124_core_vhd \
work/spec_top_fmc_adc_100Ms/.spec_top_fmc_adc_100Ms_vhd \
work/l2p_ser/.l2p_ser_vhd \
work/p2l_des/.p2l_des_vhd \
work/serdes_1_to_n_clk_pll_s2_diff/.serdes_1_to_n_clk_pll_s2_diff_vhd \
......@@ -280,21 +324,76 @@ work/sockit_owm/.sockit_owm_v: ../ip_cores/general-cores/modules/wishbone/wb_one
@mkdir -p $(dir $@) && touch $@
work/spi_clgen/.spi_clgen_v: ../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v ../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v ../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v
work/spi_clgen/.spi_clgen_v: ../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v ../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_spi $<
@mkdir -p $(dir $@) && touch $@
work/spi_shift/.spi_shift_v: ../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v ../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v ../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v
work/spi_shift/.spi_shift_v: ../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v ../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_spi $<
@mkdir -p $(dir $@) && touch $@
work/spi_top/.spi_top_v: ../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v ../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v ../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v
work/spi_top/.spi_top_v: ../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v ../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_spi $<
@mkdir -p $(dir $@) && touch $@
work/lm32_allprofiles/.lm32_allprofiles_v: ../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_lm32/generated $<
@mkdir -p $(dir $@) && touch $@
work/lm32_mc_arithmetic/.lm32_mc_arithmetic_v: ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/jtag_cores/.jtag_cores_v: ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_adder/.lm32_adder_v: ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_addsub/.lm32_addsub_v: ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_dp_ram/.lm32_dp_ram_v: ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v
vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_logic_op/.lm32_logic_op_v: ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_ram/.lm32_ram_v: ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_shifter/.lm32_shifter_v: ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v ../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_multiplier/.lm32_multiplier_v: ../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v ../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/../../src/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic $<
@mkdir -p $(dir $@) && touch $@
work/jtag_tap/.jtag_tap_v: ../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v
vlog -work work $(VLOG_FLAGS) +incdir+../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic $<
@mkdir -p $(dir $@) && touch $@
work/util/.util_vhd: testbench/util.vhd
vcom $(VCOM_FLAGS) -work work $<
......@@ -320,8 +419,8 @@ work/cmd_router/.cmd_router_vhd: testbench/cmd_router.vhd
work/cmd_router/.cmd_router: \
work/textutil/.textutil \
work/util/.util
work/util/.util \
work/textutil/.textutil
work/tb_spec/.tb_spec_vhd: testbench/tb_spec.vhd
vcom $(VCOM_FLAGS) -work work $<
......@@ -329,8 +428,8 @@ work/tb_spec/.tb_spec_vhd: testbench/tb_spec.vhd
work/tb_spec/.tb_spec: \
work/textutil/.textutil \
work/util/.util
work/util/.util \
work/textutil/.textutil
work/cmd_router1/.cmd_router1_vhd: testbench/cmd_router1.vhd
vcom $(VCOM_FLAGS) -work work $<
......@@ -338,8 +437,8 @@ work/cmd_router1/.cmd_router1_vhd: testbench/cmd_router1.vhd
work/cmd_router1/.cmd_router1: \
work/textutil/.textutil \
work/util/.util
work/util/.util \
work/textutil/.textutil
work/adc_sync_fifo/.adc_sync_fifo_vhd: ../ip_cores/adc_sync_fifo.vhd
vcom $(VCOM_FLAGS) -work work $<
......@@ -379,7 +478,7 @@ work/ext_pulse_sync_rtl/.ext_pulse_sync_rtl_vhd: ../ip_cores/ext_pulse_sync/ext_
work/ext_pulse_sync_rtl/.ext_pulse_sync_rtl: \
work/utils_pkg/.utils_pkg
work/gencores_pkg/.gencores_pkg_vhd: ../ip_cores/general-cores/modules/common/gencores_pkg.vhd
work/genram_pkg/.genram_pkg_vhd: ../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......@@ -409,192 +508,221 @@ work/irq_controller/.irq_controller_vhd: ../rtl/irq_controller.vhd
@mkdir -p $(dir $@) && touch $@
work/fmc_adc_100Ms_core_pkg/.fmc_adc_100Ms_core_pkg_vhd: ../../adc/rtl/fmc_adc_100Ms_core_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gn412x_bfm/.gn412x_bfm_vhd: testbench/gn412x_bfm.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gn412x_bfm/.gn412x_bfm: \
work/textutil/.textutil \
work/util/.util \
work/mem_model/.mem_model
work/mem_model/.mem_model \
work/textutil/.textutil
work/fmc_adc_100Ms_core/.fmc_adc_100Ms_core_vhd: ../../adc/rtl/fmc_adc_100Ms_core.vhd
work/wishbone_pkg/.wishbone_pkg_vhd: ../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fmc_adc_100Ms_csr/.fmc_adc_100Ms_csr_vhd: ../../adc/rtl/fmc_adc_100Ms_csr.vhd
work/wishbone_pkg/.wishbone_pkg: \
work/genram_pkg/.genram_pkg
work/gencores_pkg/.gencores_pkg_vhd: ../ip_cores/general-cores/modules/common/gencores_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/offset_gain_s/.offset_gain_s_vhd: ../../adc/rtl/offset_gain_s.vhd
work/gencores_pkg/.gencores_pkg: \
work/genram_pkg/.genram_pkg
work/fmc_adc_100Ms_csr/.fmc_adc_100Ms_csr_vhd: ../../adc/rtl/fmc_adc_100Ms_csr.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gn4124_core_pkg/.gn4124_core_pkg_vhd: ../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd
work/offset_gain_s/.offset_gain_s_vhd: ../../adc/rtl/offset_gain_s.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/dma_controller_wb_slave/.dma_controller_wb_slave_vhd: ../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd
work/sdb_meta_pkg/.sdb_meta_pkg_vhd: ../rtl/sdb_meta_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/l2p_arbiter/.l2p_arbiter_vhd: ../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/l2p_arbiter.vhd
work/sdb_meta_pkg/.sdb_meta_pkg: \
work/wishbone_pkg/.wishbone_pkg
work/gc_crc_gen/.gc_crc_gen_vhd: ../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/l2p_arbiter/.l2p_arbiter: \
work/gn4124_core_pkg/.gn4124_core_pkg
work/gc_crc_gen/.gc_crc_gen: \
work/gencores_pkg/.gencores_pkg
work/genram_pkg/.genram_pkg_vhd: ../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
work/gc_moving_average/.gc_moving_average_vhd: ../ip_cores/general-cores/modules/common/gc_moving_average.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/p2l_decode32/.p2l_decode32_vhd: ../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/p2l_decode32.vhd
work/gc_moving_average/.gc_moving_average: \
work/gencores_pkg/.gencores_pkg
work/gc_extend_pulse/.gc_extend_pulse_vhd: ../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/p2l_decode32/.p2l_decode32: \
work/gn4124_core_pkg/.gn4124_core_pkg
work/gc_extend_pulse/.gc_extend_pulse: \
work/gencores_pkg/.gencores_pkg
work/p2l_dma_master/.p2l_dma_master_vhd: ../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/p2l_dma_master.vhd
work/gc_delay_gen/.gc_delay_gen_vhd: ../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/p2l_dma_master/.p2l_dma_master: \
work/gn4124_core_pkg/.gn4124_core_pkg \
work/genram_pkg/.genram_pkg
work/gc_delay_gen/.gc_delay_gen: \
work/gencores_pkg/.gencores_pkg
work/wbmaster32/.wbmaster32_vhd: ../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/wbmaster32.vhd
work/gc_dual_pi_controller/.gc_dual_pi_controller_vhd: ../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wbmaster32/.wbmaster32: \
work/gn4124_core_pkg/.gn4124_core_pkg \
work/genram_pkg/.genram_pkg
work/gc_dual_pi_controller/.gc_dual_pi_controller: \
work/gencores_pkg/.gencores_pkg
work/dummy_ctrl_regs/.dummy_ctrl_regs_vhd: ../ip_cores/gn4124-core/trunk/hdl/common/rtl/dummy_ctrl_regs.vhd
work/gc_reset/.gc_reset_vhd: ../ip_cores/general-cores/modules/common/gc_reset.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/dummy_stat_regs/.dummy_stat_regs_vhd: ../ip_cores/gn4124-core/trunk/hdl/common/rtl/dummy_stat_regs.vhd
work/gc_serial_dac/.gc_serial_dac_vhd: ../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_addr_decoder/.wb_addr_decoder_vhd: ../ip_cores/gn4124-core/trunk/hdl/common/rtl/wb_addr_decoder.vhd
work/gc_sync_ffs/.gc_sync_ffs_vhd: ../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_addr_decoder/.wb_addr_decoder: \
work/gn4124_core_pkg/.gn4124_core_pkg
work/wishbone_pkg/.wishbone_pkg_vhd: ../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
work/gc_arbitrated_mux/.gc_arbitrated_mux_vhd: ../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_crc_gen/.gc_crc_gen_vhd: ../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
work/gc_arbitrated_mux/.gc_arbitrated_mux: \
work/genram_pkg/.genram_pkg \
work/gencores_pkg/.gencores_pkg
work/gc_pulse_synchronizer/.gc_pulse_synchronizer_vhd: ../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_crc_gen/.gc_crc_gen: \
work/gc_pulse_synchronizer/.gc_pulse_synchronizer: \
work/gencores_pkg/.gencores_pkg
work/gc_moving_average/.gc_moving_average_vhd: ../ip_cores/general-cores/modules/common/gc_moving_average.vhd
work/gc_frequency_meter/.gc_frequency_meter_vhd: ../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_moving_average/.gc_moving_average: \
work/gc_frequency_meter/.gc_frequency_meter: \
work/gencores_pkg/.gencores_pkg
work/gc_extend_pulse/.gc_extend_pulse_vhd: ../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
work/gc_dual_clock_ram/.gc_dual_clock_ram_vhd: ../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_extend_pulse/.gc_extend_pulse: \
work/gc_wfifo/.gc_wfifo_vhd: ../ip_cores/general-cores/modules/common/gc_wfifo.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_wfifo/.gc_wfifo: \
work/gencores_pkg/.gencores_pkg
work/gc_delay_gen/.gc_delay_gen_vhd: ../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
work/fmc_adc_100Ms_core/.fmc_adc_100Ms_core_vhd: ../../adc/rtl/fmc_adc_100Ms_core.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_delay_gen/.gc_delay_gen: \
work/gencores_pkg/.gencores_pkg
work/fmc_adc_100Ms_core/.fmc_adc_100Ms_core: \
work/genram_pkg/.genram_pkg
work/gc_dual_pi_controller/.gc_dual_pi_controller_vhd: ../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
work/memory_loader_pkg/.memory_loader_pkg_vhd: ../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_dual_pi_controller/.gc_dual_pi_controller: \
work/gencores_pkg/.gencores_pkg
work/memory_loader_pkg/.memory_loader_pkg: \
work/genram_pkg/.genram_pkg
work/gc_serial_dac/.gc_serial_dac_vhd: ../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
work/generic_shiftreg_fifo/.generic_shiftreg_fifo_vhd: ../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_sync_ffs/.gc_sync_ffs_vhd: ../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
work/generic_shiftreg_fifo/.generic_shiftreg_fifo: \
work/genram_pkg/.genram_pkg
work/ddr3_ctrl_pkg/.ddr3_ctrl_pkg_vhd: ../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/l2p_dma_master/.l2p_dma_master_vhd: ../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/l2p_dma_master.vhd
work/generic_dpram/.generic_dpram_vhd: ../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/l2p_dma_master/.l2p_dma_master: \
work/gn4124_core_pkg/.gn4124_core_pkg \
work/generic_dpram/.generic_dpram: \
work/memory_loader_pkg/.memory_loader_pkg \
work/genram_pkg/.genram_pkg
work/ddr3_ctrl_pkg/.ddr3_ctrl_pkg_vhd: ../ip_cores/ddr3-sp6-core/trunk/hdl/rtl/ddr3_ctrl_pkg.vhd
work/generic_dpram_sameclock/.generic_dpram_sameclock_vhd: ../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_async_fifo/.generic_async_fifo_vhd: ../ip_cores/general-cores/modules/genrams/xilinx/generic_async_fifo.vhd
work/generic_dpram_sameclock/.generic_dpram_sameclock: \
work/memory_loader_pkg/.memory_loader_pkg \
work/genram_pkg/.genram_pkg
work/generic_dpram_dualclock/.generic_dpram_dualclock_vhd: ../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_async_fifo/.generic_async_fifo: \
work/generic_dpram_dualclock/.generic_dpram_dualclock: \
work/memory_loader_pkg/.memory_loader_pkg \
work/genram_pkg/.genram_pkg
work/generic_dpram/.generic_dpram_vhd: ../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
work/generic_spram/.generic_spram_vhd: ../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_dpram/.generic_dpram: \
work/generic_spram/.generic_spram: \
work/genram_pkg/.genram_pkg
work/generic_spram/.generic_spram_vhd: ../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd
work/generic_async_fifo/.generic_async_fifo_vhd: ../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_async_fifo.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_spram/.generic_spram: \
work/generic_async_fifo/.generic_async_fifo: \
work/genram_pkg/.genram_pkg
work/generic_sync_fifo/.generic_sync_fifo_vhd: ../ip_cores/general-cores/modules/genrams/xilinx/generic_sync_fifo.vhd
work/generic_sync_fifo/.generic_sync_fifo_vhd: ../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......@@ -607,12 +735,30 @@ fifo_generator_v6_1/dummy/.dummy_vhd: ../ip_cores/general-cores/modules/genrams/
@mkdir -p $(dir $@) && touch $@
work/wb_async_bridge/.wb_async_bridge_vhd: ../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_async_bridge/.wb_async_bridge: \
work/wishbone_pkg/.wishbone_pkg \
work/gencores_pkg/.gencores_pkg
work/xwb_async_bridge/.xwb_async_bridge_vhd: ../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_async_bridge/.xwb_async_bridge: \
work/wishbone_pkg/.wishbone_pkg
work/wb_onewire_master/.wb_onewire_master_vhd: ../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_onewire_master/.wb_onewire_master: \
work/wishbone_pkg/.wishbone_pkg \
work/gencores_pkg/.gencores_pkg
work/xwb_onewire_master/.xwb_onewire_master_vhd: ../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
......@@ -662,149 +808,237 @@ work/xwb_bus_fanout/.xwb_bus_fanout_vhd: ../ip_cores/general-cores/modules/wishb
work/xwb_bus_fanout/.xwb_bus_fanout: \
work/wishbone_pkg/.wishbone_pkg
work/wb_conmax_pri_dec/.wb_conmax_pri_dec_vhd: ../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_dec.vhd
work/xwb_dpram/.xwb_dpram_vhd: ../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_pri_enc/.wb_conmax_pri_enc_vhd: ../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_enc.vhd
work/xwb_dpram/.xwb_dpram: \
work/wishbone_pkg/.wishbone_pkg \
work/genram_pkg/.genram_pkg
work/wb_gpio_port/.wb_gpio_port_vhd: ../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_arb/.wb_conmax_arb_vhd: ../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_arb.vhd
work/wb_gpio_port/.wb_gpio_port: \
work/wishbone_pkg/.wishbone_pkg \
work/gencores_pkg/.gencores_pkg
work/xwb_gpio_port/.xwb_gpio_port_vhd: ../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_msel/.wb_conmax_msel_vhd: ../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_msel.vhd
work/xwb_gpio_port/.xwb_gpio_port: \
work/wishbone_pkg/.wishbone_pkg
work/wb_tics/.wb_tics_vhd: ../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wbconmax_pkg/.wbconmax_pkg_vhd: ../ip_cores/general-cores/modules/wishbone/wb_conmax/wbconmax_pkg.vhd
work/wb_tics/.wb_tics: \
work/wishbone_pkg/.wishbone_pkg
work/xwb_tics/.xwb_tics_vhd: ../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_slave_if/.wb_conmax_slave_if_vhd: ../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_slave_if.vhd
work/xwb_tics/.xwb_tics: \
work/wishbone_pkg/.wishbone_pkg
work/uart_async_rx/.uart_async_rx_vhd: ../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_slave_if/.wb_conmax_slave_if: \
work/wbconmax_pkg/.wbconmax_pkg
work/uart_async_tx/.uart_async_tx_vhd: ../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_master_if/.wb_conmax_master_if_vhd: ../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_master_if.vhd
work/uart_baud_gen/.uart_baud_gen_vhd: ../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_master_if/.wb_conmax_master_if: \
work/wbconmax_pkg/.wbconmax_pkg
work/simple_uart_pkg/.simple_uart_pkg_vhd: ../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_rf/.wb_conmax_rf_vhd: ../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_rf.vhd
work/simple_uart_wb/.simple_uart_wb_vhd: ../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_rf/.wb_conmax_rf: \
work/wbconmax_pkg/.wbconmax_pkg
work/simple_uart_wb/.simple_uart_wb: \
work/simple_uart_pkg/.simple_uart_pkg
work/wb_conmax_top/.wb_conmax_top_vhd: ../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_top.vhd
work/wb_simple_uart/.wb_simple_uart_vhd: ../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_top/.wb_conmax_top: \
work/wbconmax_pkg/.wbconmax_pkg
work/wb_simple_uart/.wb_simple_uart: \
work/simple_uart_pkg/.simple_uart_pkg \
work/wishbone_pkg/.wishbone_pkg \
work/genram_pkg/.genram_pkg
work/wb_gpio_port/.wb_gpio_port_vhd: ../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
work/xwb_simple_uart/.xwb_simple_uart_vhd: ../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_gpio_port/.wb_gpio_port: \
work/gencores_pkg/.gencores_pkg \
work/xwb_simple_uart/.xwb_simple_uart: \
work/wishbone_pkg/.wishbone_pkg
work/xwb_gpio_port/.xwb_gpio_port_vhd: ../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
work/vic_prio_enc/.vic_prio_enc_vhd: ../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_gpio_port/.xwb_gpio_port: \
work/wishbone_pkg/.wishbone_pkg
work/wbgen2_pkg/.wbgen2_pkg_vhd: ../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_tics/.wb_tics_vhd: ../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
work/wb_vic/.wb_vic_vhd: ../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/uart_async_rx/.uart_async_rx_vhd: ../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
work/wb_vic/.wb_vic: \
work/wishbone_pkg/.wishbone_pkg
work/xwb_vic/.xwb_vic_vhd: ../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/uart_async_tx/.uart_async_tx_vhd: ../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
work/xwb_vic/.xwb_vic: \
work/wishbone_pkg/.wishbone_pkg
work/wb_spi/.wb_spi_vhd: ../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/uart_baud_gen/.uart_baud_gen_vhd: ../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
work/wb_spi/.wb_spi: \
work/wishbone_pkg/.wishbone_pkg
work/xwb_spi/.xwb_spi_vhd: ../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/uart_wb_slave/.uart_wb_slave_vhd: ../ip_cores/general-cores/modules/wishbone/wb_uart/uart_wb_slave.vhd
work/xwb_spi/.xwb_spi: \
work/wishbone_pkg/.wishbone_pkg
work/sdb_rom/.sdb_rom_vhd: ../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_simple_uart/.wb_simple_uart_vhd: ../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
work/sdb_rom/.sdb_rom: \
work/wishbone_pkg/.wishbone_pkg
work/xwb_crossbar/.xwb_crossbar_vhd: ../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/vic_prio_enc/.vic_prio_enc_vhd: ../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
work/xwb_crossbar/.xwb_crossbar: \
work/wishbone_pkg/.wishbone_pkg
work/xwb_sdb_crossbar/.xwb_sdb_crossbar_vhd: ../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_vic/.wb_vic_vhd: ../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
work/xwb_sdb_crossbar/.xwb_sdb_crossbar: \
work/wishbone_pkg/.wishbone_pkg
work/xwb_lm32/.xwb_lm32_vhd: ../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_vic/.wb_vic: \
work/xwb_lm32/.xwb_lm32: \
work/wishbone_pkg/.wishbone_pkg
work/wb_spi/.wb_spi_vhd: ../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
work/wb_slave_adapter/.wb_slave_adapter_vhd: ../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_spi/.wb_spi: \
work/wb_slave_adapter/.wb_slave_adapter: \
work/wishbone_pkg/.wishbone_pkg
work/xwb_spi/.xwb_spi_vhd: ../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
work/xloader_registers_pkg/.xloader_registers_pkg_vhd: ../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_spi/.xwb_spi: \
work/xloader_registers_pkg/.xloader_registers_pkg: \
work/wbgen2_pkg/.wbgen2_pkg
work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd: ../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader: \
work/wishbone_pkg/.wishbone_pkg
work/wb_virtual_uart/.wb_virtual_uart_vhd: ../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart.vhd
work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd: ../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wbgen2_pkg/.wbgen2_pkg_vhd: ../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader: \
work/wishbone_pkg/.wishbone_pkg \
work/xloader_registers_pkg/.xloader_registers_pkg \
work/gencores_pkg/.gencores_pkg
work/xloader_wb/.xloader_wb_vhd: ../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xloader_wb/.xloader_wb: \
work/xloader_registers_pkg/.xloader_registers_pkg \
work/wbgen2_pkg/.wbgen2_pkg
work/xwb_clock_crossing/.xwb_clock_crossing_vhd: ../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_clock_crossing/.xwb_clock_crossing: \
work/wishbone_pkg/.wishbone_pkg \
work/gencores_pkg/.gencores_pkg
work/xwb_dma/.xwb_dma_vhd: ../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_dma/.xwb_dma: \
work/wishbone_pkg/.wishbone_pkg
work/wb_serial_lcd/.wb_serial_lcd_vhd: ../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_serial_lcd/.wb_serial_lcd: \
work/wishbone_pkg/.wishbone_pkg \
work/genram_pkg/.genram_pkg
work/wbgen2_dpssram/.wbgen2_dpssram_vhd: ../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......@@ -827,8 +1061,8 @@ work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd: ../ip_cores/general-cores/modules
work/wbgen2_fifo_async/.wbgen2_fifo_async: \
work/wbgen2_pkg/.wbgen2_pkg \
work/genram_pkg/.genram_pkg
work/genram_pkg/.genram_pkg \
work/wbgen2_pkg/.wbgen2_pkg
work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd: ../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
vcom $(VCOM_FLAGS) -work work $<
......@@ -838,20 +1072,20 @@ work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd: ../ip_cores/general-cores/modules/w
work/wbgen2_fifo_sync/.wbgen2_fifo_sync: \
work/wbgen2_pkg/.wbgen2_pkg
work/wb_virtual_uart_slave/.wb_virtual_uart_slave_vhd: ../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart_slave.vhd
work/wb_slave_vic/.wb_slave_vic_vhd: ../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_virtual_uart_slave/.wb_virtual_uart_slave: \
work/wb_slave_vic/.wb_slave_vic: \
work/wbgen2_pkg/.wbgen2_pkg
work/ddr3_ctrl/.ddr3_ctrl_vhd: ../ip_cores/ddr3-sp6-core/trunk/hdl/rtl/ddr3_ctrl.vhd
work/ddr3_ctrl/.ddr3_ctrl_vhd: ../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ddr3_ctrl_wb/.ddr3_ctrl_wb_vhd: ../ip_cores/ddr3-sp6-core/trunk/hdl/rtl/ddr3_ctrl_wb.vhd
work/ddr3_ctrl_wb/.ddr3_ctrl_wb_vhd: ../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......@@ -859,103 +1093,121 @@ work/ddr3_ctrl_wb/.ddr3_ctrl_wb_vhd: ../ip_cores/ddr3-sp6-core/trunk/hdl/rtl/ddr
work/ddr3_ctrl_wb/.ddr3_ctrl_wb: \
work/ddr3_ctrl_pkg/.ddr3_ctrl_pkg
work/ddr3_ctrl_wrapper/.ddr3_ctrl_wrapper_vhd: ../ip_cores/ddr3-sp6-core/trunk/hdl/rtl/ddr3_ctrl_wrapper.vhd
work/ddr3_ctrl_wrapper_pkg/.ddr3_ctrl_wrapper_pkg_vhd: ../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/spec_top_fmc_adc_100Ms/.spec_top_fmc_adc_100Ms_vhd: ../rtl/spec_top_fmc_adc_100Ms.vhd
work/ddr3_ctrl_wrapper/.ddr3_ctrl_wrapper_vhd: ../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/spec_top_fmc_adc_100Ms/.spec_top_fmc_adc_100Ms: \
work/gencores_pkg/.gencores_pkg \
work/ddr3_ctrl_pkg/.ddr3_ctrl_pkg \
work/gn4124_core_pkg/.gn4124_core_pkg \
work/wishbone_pkg/.wishbone_pkg
work/ddr3_ctrl_wrapper/.ddr3_ctrl_wrapper: \
work/ddr3_ctrl_wrapper_pkg/.ddr3_ctrl_wrapper_pkg
work/ddr3_ctrl_bank3_32b_32b/.ddr3_ctrl_bank3_32b_32b_vhd: ../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/ddr3_ctrl_bank3_32b_32b.vhd
work/gn4124_core_pkg/.gn4124_core_pkg_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/iodrp_controller/.iodrp_controller_vhd: ../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/iodrp_controller.vhd
work/ddr3_ctrl_spec_bank3_64b_32b/.ddr3_ctrl_spec_bank3_64b_32b_vhd: ../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/iodrp_mcb_controller/.iodrp_mcb_controller_vhd: ../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/iodrp_mcb_controller.vhd
work/memc3_infrastructure/.memc3_infrastructure_vhd: ../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/mcb_raw_wrapper/.mcb_raw_wrapper_vhd: ../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/mcb_raw_wrapper.vhd
work/memc3_wrapper/.memc3_wrapper_vhd: ../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/mcb_soft_calibration_top/.mcb_soft_calibration_top_vhd: ../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/mcb_soft_calibration_top.vhd
work/iodrp_controller/.iodrp_controller_vhd: ../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/mcb_soft_calibration/.mcb_soft_calibration_vhd: ../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/mcb_soft_calibration.vhd
work/iodrp_mcb_controller/.iodrp_mcb_controller_vhd: ../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/memc3_infrastructure/.memc3_infrastructure_vhd: ../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/memc3_infrastructure.vhd
work/mcb_raw_wrapper/.mcb_raw_wrapper_vhd: ../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/memc3_wrapper/.memc3_wrapper_vhd: ../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/memc3_wrapper.vhd
work/mcb_soft_calibration_top/.mcb_soft_calibration_top_vhd: ../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ddr3_ctrl_bank3_64b_32b/.ddr3_ctrl_bank3_64b_32b_vhd: ../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/ddr3_ctrl_bank3_64b_32b.vhd
work/mcb_soft_calibration/.mcb_soft_calibration_vhd: ../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/iodrp_controller/.iodrp_controller_vhd: ../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd
work/dma_controller/.dma_controller_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/iodrp_mcb_controller/.iodrp_mcb_controller_vhd: ../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd
work/dma_controller/.dma_controller: \
work/gn4124_core_pkg/.gn4124_core_pkg
work/dma_controller_wb_slave/.dma_controller_wb_slave_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/mcb_raw_wrapper/.mcb_raw_wrapper_vhd: ../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd
work/l2p_arbiter/.l2p_arbiter_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/mcb_soft_calibration_top/.mcb_soft_calibration_top_vhd: ../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd
work/l2p_arbiter/.l2p_arbiter: \
work/gn4124_core_pkg/.gn4124_core_pkg
work/l2p_dma_master/.l2p_dma_master_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/mcb_soft_calibration/.mcb_soft_calibration_vhd: ../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd
work/l2p_dma_master/.l2p_dma_master: \
work/gn4124_core_pkg/.gn4124_core_pkg \
work/genram_pkg/.genram_pkg
work/p2l_decode32/.p2l_decode32_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/memc3_infrastructure/.memc3_infrastructure_vhd: ../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd
work/p2l_decode32/.p2l_decode32: \
work/gn4124_core_pkg/.gn4124_core_pkg
work/p2l_dma_master/.p2l_dma_master_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/memc3_wrapper/.memc3_wrapper_vhd: ../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd
work/p2l_dma_master/.p2l_dma_master: \
work/gn4124_core_pkg/.gn4124_core_pkg \
work/genram_pkg/.genram_pkg
work/wbmaster32/.wbmaster32_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gn4124_core/.gn4124_core_vhd: ../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
work/wbmaster32/.wbmaster32: \
work/gn4124_core_pkg/.gn4124_core_pkg \
work/genram_pkg/.genram_pkg
work/gn4124_core/.gn4124_core_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......@@ -963,15 +1215,20 @@ work/gn4124_core/.gn4124_core_vhd: ../ip_cores/gn4124-core/trunk/hdl/gn4124core/
work/gn4124_core/.gn4124_core: \
work/gn4124_core_pkg/.gn4124_core_pkg
work/dma_controller/.dma_controller_vhd: ../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/dma_controller.vhd
work/spec_top_fmc_adc_100Ms/.spec_top_fmc_adc_100Ms_vhd: ../rtl/spec_top_fmc_adc_100Ms.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/dma_controller/.dma_controller: \
work/gn4124_core_pkg/.gn4124_core_pkg
work/spec_top_fmc_adc_100Ms/.spec_top_fmc_adc_100Ms: \
work/wishbone_pkg/.wishbone_pkg \
work/fmc_adc_100Ms_core_pkg/.fmc_adc_100Ms_core_pkg \
work/gn4124_core_pkg/.gn4124_core_pkg \
work/ddr3_ctrl_pkg/.ddr3_ctrl_pkg \
work/sdb_meta_pkg/.sdb_meta_pkg \
work/gencores_pkg/.gencores_pkg
work/l2p_ser/.l2p_ser_vhd: ../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd
work/l2p_ser/.l2p_ser_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......@@ -979,7 +1236,7 @@ work/l2p_ser/.l2p_ser_vhd: ../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spar
work/l2p_ser/.l2p_ser: \
work/gn4124_core_pkg/.gn4124_core_pkg
work/p2l_des/.p2l_des_vhd: ../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/p2l_des.vhd
work/p2l_des/.p2l_des_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......@@ -987,27 +1244,27 @@ work/p2l_des/.p2l_des_vhd: ../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spar
work/p2l_des/.p2l_des: \
work/gn4124_core_pkg/.gn4124_core_pkg
work/serdes_1_to_n_clk_pll_s2_diff/.serdes_1_to_n_clk_pll_s2_diff_vhd: ../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd
work/serdes_1_to_n_clk_pll_s2_diff/.serdes_1_to_n_clk_pll_s2_diff_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/serdes_1_to_n_data_s2_se/.serdes_1_to_n_data_s2_se_vhd: ../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd
work/serdes_1_to_n_data_s2_se/.serdes_1_to_n_data_s2_se_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/serdes_n_to_1_s2_diff/.serdes_n_to_1_s2_diff_vhd: ../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd
work/serdes_n_to_1_s2_diff/.serdes_n_to_1_s2_diff_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/serdes_n_to_1_s2_se/.serdes_n_to_1_s2_se_vhd: ../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd
work/serdes_n_to_1_s2_se/.serdes_n_to_1_s2_se_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/pulse_sync_rtl/.pulse_sync_rtl_vhd: ../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd
work/pulse_sync_rtl/.pulse_sync_rtl_vhd: ../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......
hdl/spec/sim/cmd0.vec
View file @ 2f92c67d
......@@ -165,162 +165,176 @@ wr 0000000020000028 F 00000000
-- DMA length
wr 000000002000002C F 00001000
-- Next item address (lsb)
wr 0000000020000030 F 20000030
wr 0000000020000030 F 20000040
-- Next item address (msb)
wr 0000000020000034 F 00000000
-- DMA attributes (from carrier to host, last item)
wr 0000000020000038 F 00000000
wr 0000000020000038 F 00000001
wait %d2000
-- DMA item stored in host memory
------------------------------
-- Carrier start address
wr 0000000020000040 F 00003000
-- Host start address (lsb)
wr 0000000020000044 F 40003000
-- Host start address (msb)
wr 0000000020000048 F 00000000
-- DMA length
wr 000000002000004C F 00001000
-- Next item address (lsb)
wr 0000000020000050 F 20000060
-- Next item address (msb)
wr 0000000020000054 F 00000000
-- DMA attributes (from carrier to host, last item)
wr 0000000020000058 F 00000001
-- DMA
-- DMA item stored in host memory
------------------------------
-- Carrier start address
wr FF00000000000008 F 00000000
wr 0000000020000060 F 00004000
-- Host start address (lsb)
wr FF0000000000000C F 40000000
wr 0000000020000064 F 40004000
-- Host start address (msb)
wr FF00000000000010 F 00000000
wr 0000000020000068 F 00000000
-- DMA length
wr FF00000000000014 F 00001000
wr 000000002000006C F 00001000
-- Next item address (lsb)
wr FF00000000000018 F 20000000
wr 0000000020000070 F 20000080
-- Next item address (msb)
wr FF0000000000001C F 00000000
wr 0000000020000074 F 00000000
-- DMA attributes (from carrier to host, last item)
wr FF00000000000020 F 00000001
-- Start DMA
--wr FF00000000000000 F 00000001
wr 0000000020000078 F 00000000
wait %d2000
wait %d100
-- onewire config
wr FF000000000A0004 F 007C0270
wr FF00000000001A04 F 007C0270
wait %d100
wr FF000000000A0000 F 0000000A
wr FF00000000001A00 F 0000000A
wait %d100
-- trigger config (sw trig enable)
--wr FF00000000090008 F 00000008
wr FF00000000001908 F 00000008
-- trigger config (hw int trig enable)
--wr FF00000000090008 F 00000004
--wr FF00000000001908 F 00000004
-- trigger config (int trig)
wr FF00000000090008 F 02600004
--wr FF00000000001908 F 02600004
-- decimation factor = 1
wr FF0000000009001C F 00000001
wr FF0000000000191C F 00000001
-- pre-trig samples
wr FF00000000090020 F 0000000A
wr FF00000000001920 F 0000000A
-- post-trig samples
wr FF00000000090024 F 00000100
wr FF00000000001924 F 00000100
-- number of shots
wr FF00000000090014 F 00000001
wr FF00000000001914 F 00000003
-- Channel 1 gain
wr FF00000000090034 F 00008000
wr FF00000000001934 F 00008000
-- Channel 1 offset
wr FF00000000090038 F 00000000
wr FF00000000001938 F 00000000
-- Channel 2 gain
wr FF00000000090044 F 00008000
wr FF00000000001944 F 00008000
-- Channel 2 offset
wr FF00000000090048 F 00000000
wr FF00000000001948 F 00000000
-- Channel 3 gain
wr FF00000000090054 F 00008000
wr FF00000000001954 F 00008000
-- Channel 3 offset
wr FF00000000090058 F 00000000
wr FF00000000001958 F 00000000
-- Channel 4 gain
wr FF00000000090064 F 00008000
wr FF00000000001964 F 00008000
-- Channel 4 offset
wr FF00000000090068 F 00000000
wr FF00000000001968 F 00000000
-- Enable test data and sampling clock
--wr FF00000000090000 F 00000024
wr FF00000000001900 F 00000024
-- Enable sampling clock
wr FF00000000090000 F 00000004
--wr FF00000000001900 F 00000004
-- start acquisition
--wr FF00000000090000 F 00000025
wr FF00000000090000 F 00000005
wr FF00000000001900 F 00000025
--wr FF00000000001900 F 00000005
wait %d800
-- sw trigger
--wr FF00000000090010 F FFFFFFFF
wr FF00000000001910 F FFFFFFFF
--wait %d800
wait %d800
-- sw trigger
--wr FF00000000090010 F FFFFFFFF
wr FF00000000001910 F FFFFFFFF
--wait %d800
wait %d800
-- sw trigger
-wr FF00000000090010 F FFFFFFFF
wr FF00000000001910 F FFFFFFFF
--wait %d800
-- sw trigger
--wr FF00000000090010 F FFFFFFFF
--wr FF00000000001910 F FFFFFFFF
--wait %d800
-- sw trigger
--wr FF00000000090010 F FFFFFFFF
--wr FF00000000001910 F FFFFFFFF
wait %d700
wait %d1000
-- DMA
------------------------------
-- Carrier start address
wr FF00000000000008 F 00000000
wr FF00000000001008 F 00000000
-- Host start address (lsb)
wr FF0000000000000C F 40000000
wr FF0000000000100C F 40000000
-- Host start address (msb)
wr FF00000000000010 F 00000000
wr FF00000000001010 F 00000000
-- DMA length
wr FF00000000000014 F 00001000
wr FF00000000001014 F 00001000
-- Next item address (lsb)
wr FF00000000000018 F 00000000
wr FF00000000001018 F 20000000
-- Next item address (msb)
wr FF0000000000001C F 00000000
wr FF0000000000101C F 00000000
-- DMA attributes (from carrier to host, last item)
wr FF00000000000020 F 00000000
wr FF00000000001020 F 00000001
-- Start DMA
wr FF00000000000000 F 00000001
wr FF00000000001000 F 00000001
wait %d3000
---------------------------------------------
---------------------------------------------
-- start acquisition
wr FF00000000090000 F 00000001
--wr FF00000000001900 F 00000001
wait %d500
-- sw trigger
wr FF00000000090010 F FFFFFFFF
--wr FF00000000001910 F FFFFFFFF
wait %d400
-- DMA
------------------------------
-- Carrier start address
wr FF00000000000008 F 00000000
--wr FF00000000001008 F 00000000
-- Host start address (lsb)
wr FF0000000000000C F 40000000
--wr FF0000000000100C F 40000000
-- Host start address (msb)
wr FF00000000000010 F 00000000
--wr FF00000000001010 F 00000000
-- DMA length
wr FF00000000000014 F 00000200
--wr FF00000000001014 F 00000200
-- Next item address (lsb)
wr FF00000000000018 F 20000000
--wr FF00000000001018 F 20000000
-- Next item address (msb)
wr FF0000000000001C F 00000000
--wr FF0000000000101C F 00000000
-- DMA attributes (from carrier to host, last item)
wr FF00000000000020 F 00000000
--wr FF00000000001020 F 00000000
-- Start DMA
wr FF00000000000000 F 00000001
--wr FF00000000001000 F 00000001
wait %d1000
......@@ -332,49 +346,29 @@ wait %d1000
-- FMC I2C (prescaler)
wr FF00000000080000 F 000000F9
rd FF00000000080000 F 000000F9 FFFFFFFF
--wr FF00000000080000 F 000000F9
--rd FF00000000080000 F 000000F9 FFFFFFFF
wait %d640
-- Carrier CSR (read carrier type and PCB version)
rd FF00000000030000 F 00010001 FFFFFFFF
--rd FF00000000030000 F 00010001 FFFFFFFF
-- Carrier CSR (switch front panel LED ON)
wr FF00000000030010 F 00000003
rd FF00000000030010 F 00000003 FFFFFFFF
--wr FF00000000030010 F 00000003
--rd FF00000000030010 F 00000003 FFFFFFFF
wait %d640
-- FMC SPI (divider = 100)
wr FF00000000070014 F 00000064
--wr FF00000000070014 F 00000064
-- FMC SPI (select ADC)
wr FF00000000070018 F 00000001
--wr FF00000000070018 F 00000001
-- FMC SPI (data)
wr FF00000000070000 F 000081FF
--wr FF00000000070000 F 000081FF
-- FMC SPI (ass, tx_neg, go, len=16)
wr FF00000000070010 F 00002510
--wr FF00000000070010 F 00002510
wait %d300
-- DDR access trough DMA wishbone
wr 0000000020000000 F 00000000
wr 0000000020000004 F 40000000
wr 0000000020000008 F 00000000
-- DMA length
wr 000000002000000C F 000000C0
wr 0000000020000010 F 00000000
wr 0000000020000014 F 00000000
wr 0000000020000018 F 00000000
-- wrb FF00000010004004 F 00000000
wr FF00000000000008 F 00000000
wr FF0000000000000C F 40000000
wr FF00000000000010 F 00000000
-- DMA length
wr FF00000000000014 F 000000C0
wr FF00000000000018 F 20000000
wr FF0000000000001C F 00000000
wr FF00000000000020 F 00000003
wr FF00000000000000 F 00000001
-- Now read back what was just written
-- the following three reads will go out as a single request
......
hdl/spec/sim/sim_models/2048Mb_ddr3/ddr3_parameters.vh
View file @ 2f92c67d
......@@ -820,7 +820,7 @@
parameter RZQ = 240; // termination resistance
parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout
parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors
parameter DEBUG = 1; // Turn on Debug messages
parameter DEBUG = 0; // Turn on Debug messages
parameter BUS_DELAY = 0; // delay in nanoseconds
parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads
parameter RANDOM_SEED = 711689044; //seed value for random generator.
......
hdl/spec/sim/spec.do
View file @ 2f92c67d
......@@ -5,14 +5,15 @@ log -r /*
##do wave_datapath.do
##do wave_multishot.do
##do wave_onewire.do
##do wave_adc_core.do
do wave_adc_core.do
##do wave_gnum.do
do wave_end_acq_irq.do
##do wave_end_acq_irq.do
##do wave_ddr_wb.do
view wave
view transcript
run 30 us
run 50 us
##run 15000 ns
##run 25057 ns
##force -freeze sim:/tb_lambo/l2p_rdy 0 0 -cancel {80 ns}
......
hdl/spec/sim/testbench/tb_spec.vhd
View file @ 2f92c67d
......@@ -46,7 +46,7 @@ architecture TEST of TB_SPEC is
generic
(
STRING_MAX : integer := 256; -- Command string maximum length
T_LCLK : time := 10 ns; -- Local Bus Clock Period
T_LCLK : time := 5 ns; -- Local Bus Clock Period
T_P2L_CLK_DLY : time := 2 ns; -- Delay from LCLK to P2L_CLK
INSTANCE_LABEL : string := "GN412X_BFM"; -- Label string to be used as a prefix for messages from the model
MODE_PRIMARY : boolean := true -- TRUE for BFM acting as GN412x, FALSE for BFM acting as the DUT
......@@ -492,7 +492,7 @@ begin
generic map
(
STRING_MAX => STRING_MAX,
T_LCLK => 6.25 ns,
T_LCLK => 5 ns,
T_P2L_CLK_DLY => 2 ns,
INSTANCE_LABEL => "U0(Primary GN412x): ",
MODE_PRIMARY => true
......
hdl/spec/sim/wave_adc_core.do
View file @ 2f92c67d
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /tb_spec/rstout18n
add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb_spec/adc_data(0) {-height 16 -radix hexadecimal} /tb_spec/adc_data(1) {-height 16 -radix hexadecimal} /tb_spec/adc_data(2) {-height 16 -radix hexadecimal} /tb_spec/adc_data(3) {-height 16 -radix hexadecimal}} /tb_spec/adc_data
add wave -noupdate /tb_spec/RSTOUT18n
add wave -noupdate -radix hexadecimal -childformat {{/tb_spec/ADC_DATA(0) -radix hexadecimal} {/tb_spec/ADC_DATA(1) -radix hexadecimal} {/tb_spec/ADC_DATA(2) -radix hexadecimal} {/tb_spec/ADC_DATA(3) -radix hexadecimal}} -expand -subitemconfig {/tb_spec/ADC_DATA(0) {-height 17 -radix hexadecimal} /tb_spec/ADC_DATA(1) {-height 17 -radix hexadecimal} /tb_spec/ADC_DATA(2) {-height 17 -radix hexadecimal} /tb_spec/ADC_DATA(3) {-height 17 -radix hexadecimal}} /tb_spec/ADC_DATA
add wave -noupdate -divider {adc core}
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/sys_clk_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/sys_rst_n_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_csr_adr_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_csr_dat_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_csr_dat_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_csr_cyc_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_csr_sel_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_csr_stb_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_csr_we_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_csr_ack_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_clk_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_adr_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_dat_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_sel_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_stb_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_we_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_cyc_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_ack_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_stall_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/ext_trigger_p_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/ext_trigger_n_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/adc_dco_p_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/adc_dco_n_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/adc_fr_p_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/adc_fr_n_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/adc_outa_p_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/adc_outa_n_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/adc_outb_p_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/adc_outb_n_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/gpio_dac_clr_n_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/gpio_led_acq_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/gpio_led_trig_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/gpio_ssr_ch1_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/gpio_ssr_ch2_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/gpio_ssr_ch3_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/gpio_ssr_ch4_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/gpio_si570_oe_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/sys_rst
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/fs_rst
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/fs_rst_n
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/dco_clk
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/clk_fb
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/locked_in
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/locked_out
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_clk
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/fs_clk
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/fs_clk_buf
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_in_p
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_in_n
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_out_raw
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_out_data
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_out_data_d
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/data_calibr_in
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/offset_calibr
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/gain_calibr
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/data_calibr_out
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_out_fr
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_auto_bitslip
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_man_bitslip
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_bitslip
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_synced
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/bitslip_sreg
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/ext_trig_a
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/ext_trig
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/int_trig
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/int_trig_sel
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/int_trig_thres
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/int_trig_data
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/int_trig_over_thres_d
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/int_trig_over_thres
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/hw_trig
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/hw_trig_t
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/hw_trig_sel
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/hw_trig_en
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/sw_trig
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/sw_trig_t
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/sw_trig_en
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/trig
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/trig_delay
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/trig_delay_cnt
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/trig_d
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/trig_align
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/decim_factor
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/decim_cnt
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/decim_en
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_din
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_dout
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_empty
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_full
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_wr
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_rd
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_valid
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_dreq
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/gain_calibr
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/offset_calibr
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/acq_fsm_current_state
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/acq_fsm_state
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/fsm_cmd
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/fsm_cmd_wr
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/acq_start
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/acq_stop
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/acq_trig
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/acq_end
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/acq_in_pre_trig
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/acq_in_post_trig
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/samples_wr_en
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_100ms_core/pre_trig_value
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_100ms_core/pre_trig_cnt
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/pre_trig_done
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_100ms_core/post_trig_value
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_100ms_core/post_trig_cnt
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/post_trig_done
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_100ms_core/samples_cnt
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_100ms_core/shots_value
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_100ms_core/shots_cnt
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/shots_done
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/shots_decr
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/single_shot
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/multishot_buffer_sel
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_100ms_core/dpram_addra_cnt
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_100ms_core/dpram_addra_trig
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_100ms_core/dpram_addra_post_done
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_100ms_core/dpram_addrb_cnt
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_100ms_core/dpram_dout
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/dpram_valid
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/dpram_valid_t
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/dpram0_dina
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_100ms_core/dpram0_addra
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/dpram0_wea
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_100ms_core/dpram0_addrb
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/dpram0_doutb
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/dpram1_dina
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/dpram1_addra
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/dpram1_wea
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_100ms_core/dpram1_addrb
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/dpram1_doutb
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_100ms_core/trig_addr
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_din
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_dout
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_empty
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_full
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_wr
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_rd
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_valid
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_dreq
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_wr_en
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_100ms_core/ram_addr_cnt
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/test_data_en
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_stall_t
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/trig_led
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/trig_led_man
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/acq_led_man
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sys_clk_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sys_rst_n_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_csr_adr_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_csr_dat_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_csr_dat_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_csr_cyc_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_csr_sel_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_csr_stb_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_csr_we_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_csr_ack_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_clk_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_adr_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_dat_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_sel_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_stb_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_we_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_cyc_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_ack_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_stall_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/ext_trigger_p_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/ext_trigger_n_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/adc_dco_p_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/adc_dco_n_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/adc_fr_p_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/adc_fr_n_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/adc_outa_p_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/adc_outa_n_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/adc_outb_p_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/adc_outb_n_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/gpio_dac_clr_n_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/gpio_led_acq_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/gpio_led_trig_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/gpio_ssr_ch1_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/gpio_ssr_ch2_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/gpio_ssr_ch3_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/gpio_ssr_ch4_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/gpio_si570_oe_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sys_rst
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/fs_rst
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/fs_rst_n
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dco_clk
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/clk_fb
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/locked_in
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/locked_out
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_clk
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/fs_clk
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/fs_clk_buf
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_in_p
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_in_n
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_out_raw
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_out_data
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_out_data_d
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/data_calibr_in
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/offset_calibr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/gain_calibr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/data_calibr_out
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_out_fr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_man_bitslip
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_bitslip
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_synced
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/bitslip_sreg
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/ext_trig_a
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/ext_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/int_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/int_trig_sel
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/int_trig_thres
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/int_trig_data
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/int_trig_over_thres_d
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/int_trig_over_thres
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/hw_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/hw_trig_t
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/hw_trig_sel
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/hw_trig_en
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sw_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sw_trig_t
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sw_trig_en
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_delay
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_delay_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_d
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_align
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_factor
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_en
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_din
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_dout
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_empty
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_full
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_wr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_rd
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_valid
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_dreq
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/gain_calibr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/offset_calibr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_fsm_current_state
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_fsm_state
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/fsm_cmd
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/fsm_cmd_wr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_start
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_stop
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_end
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_in_pre_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_in_post_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/samples_wr_en
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/pre_trig_value
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/pre_trig_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/pre_trig_done
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/post_trig_value
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/post_trig_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/post_trig_done
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/samples_cnt
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_value
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_done
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_decr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/single_shot
add wave -noupdate -divider {dpram wr}
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/multishot_buffer_sel
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_addra_cnt
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_addra_trig
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_addra_post_done
add wave -noupdate -divider {dpram 0}
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram0_dina
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram0_addra
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram0_wea
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram0_addrb
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram0_doutb
add wave -noupdate -divider {dpram 1}
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram1_dina
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram1_addra
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram1_wea
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram1_addrb
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram1_doutb
add wave -noupdate -divider {dpram rd}
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_dout
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_valid
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_valid_t
add wave -noupdate -divider {ddr fifo}
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_addr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr_en
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_din
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_full
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_rd
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_dout
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_empty
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_valid
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_dreq
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/ram_addr_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/test_data_en
add wave -noupdate -divider {ddr wb}
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_cyc_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_stall_t
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_we_o
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_stb_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_dat_o
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_adr_o
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_ack_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_led
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_led_man
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_led_man
add wave -noupdate /tb_spec/RSTOUT18n
add wave -noupdate -radix hexadecimal -childformat {{/tb_spec/ADC_DATA(0) -radix hexadecimal} {/tb_spec/ADC_DATA(1) -radix hexadecimal} {/tb_spec/ADC_DATA(2) -radix hexadecimal} {/tb_spec/ADC_DATA(3) -radix hexadecimal}} -expand -subitemconfig {/tb_spec/ADC_DATA(0) {-radix hexadecimal} /tb_spec/ADC_DATA(1) {-radix hexadecimal} /tb_spec/ADC_DATA(2) {-radix hexadecimal} /tb_spec/ADC_DATA(3) {-radix hexadecimal}} /tb_spec/ADC_DATA
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1153292 ps} 0} {{Cursor 2} {23048000 ps} 0}
WaveRestoreCursors {{Cursor 1} {20587606 ps} 0} {{Cursor 2} {47376100 ps} 0}
configure wave -namecolwidth 496
configure wave -valuecolwidth 172
configure wave -justifyvalue left
......@@ -171,4 +184,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {3298923 ps}
WaveRestoreZoom {20271883 ps} {20896118 ps}
hdl/spec/sim/wave_datapath.do
View file @ 2f92c67d
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {Wishbone CSR interface}
add wave -noupdate /tb_spec/u1/sys_clk_125
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_adr
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_dat_o
add wave -noupdate /tb_spec/u1/wb_stb
add wave -noupdate /tb_spec/u1/wb_we
add wave -noupdate /tb_spec/u1/wb_sel
add wave -noupdate /tb_spec/U1/sys_clk_125
add wave -noupdate -divider trigger
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/sw_trig_en
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/sw_trig
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/trig
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/trig_d
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/trig_align
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sw_trig_en
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sw_trig
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_d
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_align
add wave -noupdate -divider {acq fsm}
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/post_trig_done
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/shots_cnt
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/shots_value
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/shots_decr
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/shots_done
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/acq_fsm_current_state
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/post_trig_done
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_value
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_decr
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_done
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_fsm_current_state
add wave -noupdate -divider datapath
add wave -noupdate /tb_spec/u1/adc_dco_n_i
add wave -noupdate /tb_spec/u1/adc_dco_p_i
add wave -noupdate /tb_spec/u1/adc_fr_p_i
add wave -noupdate /tb_spec/u1/adc_outa_p_i(0)
add wave -noupdate /tb_spec/u1/adc_outb_p_i(0)
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_out_fr
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_out_data
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/locked_out
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/fs_clk
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/fs_rst_n
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_synced
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_100ms_core/decim_cnt
add wave -noupdate -radix decimal /tb_spec/u1/cmp_fmc_adc_100ms_core/decim_factor
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/decim_en
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_wr
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_din
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_full
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_dreq
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_dout
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_dout(48)
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_empty
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_rd
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_valid
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_out_data
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_wr
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_wr_en
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_din
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_full
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_dreq
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_rd
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_dout
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_empty
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_valid
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/ram_addr_cnt
add wave -noupdate -radix hexadecimal /tb_spec/ADC_DATA
add wave -noupdate /tb_spec/U1/adc_dco_n_i
add wave -noupdate /tb_spec/U1/adc_dco_p_i
add wave -noupdate /tb_spec/U1/adc_fr_p_i
add wave -noupdate /tb_spec/U1/adc_outa_p_i(0)
add wave -noupdate /tb_spec/U1/adc_outb_p_i(0)
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_out_fr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_out_data
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/locked_out
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/fs_clk
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/fs_rst_n
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_synced
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_cnt
add wave -noupdate -radix decimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_factor
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_en
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_wr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_din
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_full
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_dreq
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_dout
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_dout(48)
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_empty
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_rd
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_valid
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_out_data
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr_en
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_din
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_full
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_dreq
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_rd
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_dout
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_empty
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_valid
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/ram_addr_cnt
add wave -noupdate -divider {adc to ddr WB}
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_ack_i
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_clk_i
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_cyc_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_dat_o
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_stb_o
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_we_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_adr_o
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_stall_i
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_ack_i
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_clk_i
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_cyc_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_dat_o
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_stb_o
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_we_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_adr_o
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_stall_i
add wave -noupdate -divider {ddr controller}
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/status_o(0)
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/wb0_clk_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/rst_n_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p0_wr_empty
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_ddr_ctrl/p0_wr_count
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p0_wr_full
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/p0_wr_data
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p0_wr_en
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/p0_cmd_bl
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/p0_cmd_byte_addr
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p0_cmd_empty
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p0_cmd_full
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p0_cmd_en
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/p1_cmd_bl
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/p1_cmd_byte_addr
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p1_cmd_empty
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p1_cmd_en
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p1_cmd_full
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p1_rd_error
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p1_rd_overflow
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p1_rd_full
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/p1_rd_count
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/p1_rd_data
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p1_rd_empty
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p1_rd_en
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/p1_wr_count
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/p1_wr_data
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p1_wr_en
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p1_wr_full
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/status_o(0)
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/wb0_clk_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/rst_n_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_wr_empty
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_ddr_ctrl/p0_wr_count
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_wr_full
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/p0_wr_data
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_wr_en
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/p0_cmd_bl
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/p0_cmd_byte_addr
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_cmd_empty
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_cmd_full
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_cmd_en
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/p1_cmd_bl
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/p1_cmd_byte_addr
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p1_cmd_empty
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p1_cmd_en
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p1_cmd_full
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p1_rd_error
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p1_rd_overflow
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p1_rd_full
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/p1_rd_count
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/p1_rd_data
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p1_rd_empty
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p1_rd_en
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/p1_wr_count
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/p1_wr_data
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p1_wr_en
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p1_wr_full
add wave -noupdate -divider {ddr to gennum WB}
add wave -noupdate /tb_spec/u1/sys_clk_125
add wave -noupdate /tb_spec/u1/wb_dma_ack
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_dma_adr
add wave -noupdate /tb_spec/u1/wb_dma_cyc
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_dma_dat_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_dma_dat_o
add wave -noupdate /tb_spec/u1/wb_dma_stall
add wave -noupdate /tb_spec/u1/wb_dma_stb
add wave -noupdate /tb_spec/u1/wb_dma_we
add wave -noupdate /tb_spec/U1/sys_clk_125
add wave -noupdate /tb_spec/U1/wb_dma_ack
add wave -noupdate -radix hexadecimal /tb_spec/U1/wb_dma_adr
add wave -noupdate /tb_spec/U1/wb_dma_cyc
add wave -noupdate -radix hexadecimal /tb_spec/U1/wb_dma_dat_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/wb_dma_dat_o
add wave -noupdate /tb_spec/U1/wb_dma_stall
add wave -noupdate /tb_spec/U1/wb_dma_stb
add wave -noupdate /tb_spec/U1/wb_dma_we
add wave -noupdate -divider l2p
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/dma_ctrl_start_l2p_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/dma_ctrl_len_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_last_packet
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_header
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/dma_ctrl_done_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_current_state
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/ldm_arb_data
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/ldm_arb_dframe
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/ldm_arb_req
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/ldm_arb_valid
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/dma_ctrl_start_l2p_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/dma_ctrl_len_i
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_last_packet
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_header
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_empty
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_rd
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/dma_ctrl_done_o
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_current_state
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/ldm_arb_data
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/ldm_arb_dframe
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/ldm_arb_req
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/ldm_arb_valid
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/arb_ldm_gnt
add wave -noupdate -divider p2l
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_current_state
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_cnt
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/to_wb_fifo_din
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/to_wb_fifo_wr
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_current_state
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/to_wb_fifo_din
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/to_wb_fifo_wr
add wave -noupdate -divider {GN4124 LOCAL BUS}
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/l2p_data_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/l2p_dframe_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/l2p_valid_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/l2p_edb_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/l_wr_rdy_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/p2l_data_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/p2l_dframe_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/p2l_rdy_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/p2l_valid_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/p_rd_d_rdy_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/p_wr_rdy_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/p_wr_req_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/tx_error_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/vc_rdy_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/l2p_data_o
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/l2p_dframe_o
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/l2p_valid_o
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/l2p_edb_o
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/l_wr_rdy_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/p2l_data_i
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/p2l_dframe_i
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/p2l_rdy_o
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/p2l_valid_i
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/p_rd_d_rdy_i
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/p_wr_rdy_o
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/p_wr_req_i
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/tx_error_i
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/vc_rdy_i
add wave -noupdate -divider {gennum global}
add wave -noupdate -expand /tb_spec/u1/irq_sources
add wave -noupdate -expand /tb_spec/U1/irq_sources
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1990664 ps} 0}
WaveRestoreCursors {{Cursor 1} {44575961 ps} 0}
configure wave -namecolwidth 496
configure wave -valuecolwidth 172
configure wave -justifyvalue left
......@@ -158,4 +157,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {34650 ns}
WaveRestoreZoom {44465609 ps} {44570867 ps}
hdl/spec/sim/wave_ddr_wb.do 0 → 100644
View file @ 2f92c67d
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {Local Clock}
add wave -noupdate /tb_spec/U1/clk20_vcxo_i
add wave -noupdate -divider L2P
add wave -noupdate /tb_spec/L2P_CLKp
add wave -noupdate /tb_spec/L2P_CLKn
add wave -noupdate -radix hexadecimal /tb_spec/L2P_DATA
add wave -noupdate -radix hexadecimal /tb_spec/L2P_DATA_32
add wave -noupdate /tb_spec/L2P_DFRAME
add wave -noupdate /tb_spec/L2P_VALID
add wave -noupdate /tb_spec/L2P_EDB
add wave -noupdate /tb_spec/L_WR_RDY
add wave -noupdate /tb_spec/P_RD_D_RDY
add wave -noupdate /tb_spec/L2P_RDY
add wave -noupdate /tb_spec/TX_ERROR
add wave -noupdate -divider P2L
add wave -noupdate /tb_spec/P2L_CLKp
add wave -noupdate /tb_spec/P2L_CLKn
add wave -noupdate -radix hexadecimal /tb_spec/P2L_DATA
add wave -noupdate -radix hexadecimal /tb_spec/P2L_DATA_32
add wave -noupdate /tb_spec/P2L_DFRAME
add wave -noupdate /tb_spec/P2L_VALID
add wave -noupdate /tb_spec/P2L_RDY
add wave -noupdate /tb_spec/P_WR_REQ
add wave -noupdate /tb_spec/P_WR_RDY
add wave -noupdate /tb_spec/RX_ERROR
add wave -noupdate /tb_spec/VC_RDY
add wave -noupdate -divider IRQ
add wave -noupdate -radix hexadecimal /tb_spec/GPIO
add wave -noupdate -divider {Wishbone DMA Interface}
add wave -noupdate /tb_spec/U1/sys_clk_125
add wave -noupdate -radix hexadecimal /tb_spec/U1/wb_dma_adr
add wave -noupdate -radix hexadecimal /tb_spec/U1/wb_dma_dat_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/wb_dma_dat_o
add wave -noupdate /tb_spec/U1/wb_dma_sel
add wave -noupdate /tb_spec/U1/wb_dma_cyc
add wave -noupdate /tb_spec/U1/wb_dma_stb
add wave -noupdate /tb_spec/U1/wb_dma_we
add wave -noupdate /tb_spec/U1/wb_dma_ack
add wave -noupdate /tb_spec/U1/wb_dma_stall
add wave -noupdate -divider {DDR interface (dma)}
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_wr_underrun_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_wr_mask
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_wr_full_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_wr_error_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_wr_en_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_wr_en
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_wr_empty_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_wr_data
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_wr_count_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_wr_clk_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_overflow_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_full_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_error_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_en_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_en
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_empty_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_data_i
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_count_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_clk_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_instr_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_instr
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_full_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_en_r_edge
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_en_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_en_d
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_en
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_empty_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_clk_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_bl
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_burst_cnt
add wave -noupdate -divider {Wishbone ADC to DDR}
add wave -noupdate -radix hexadecimal /tb_spec/U1/wb_ddr_adr
add wave -noupdate -radix hexadecimal /tb_spec/U1/wb_ddr_dat_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/wb_ddr_sel
add wave -noupdate -radix hexadecimal /tb_spec/U1/wb_ddr_cyc
add wave -noupdate -radix hexadecimal /tb_spec/U1/wb_ddr_stb
add wave -noupdate -radix hexadecimal /tb_spec/U1/wb_ddr_we
add wave -noupdate -radix hexadecimal /tb_spec/U1/wb_ddr_ack
add wave -noupdate -radix hexadecimal /tb_spec/U1/wb_ddr_stall
add wave -noupdate -divider {DDR interface (adc)}
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_underrun_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_mask_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_mask
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_full_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_error_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_en_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_en
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_empty_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_data
add wave -noupdate -radix decimal /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_count_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_clk_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_rd_overflow_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_rd_full_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_rd_error_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_rd_en_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_rd_en
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_rd_empty_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_rd_data_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_rd_count_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_rd_clk_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_instr_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_instr
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_full_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_en_r_edge
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_en_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_en_d
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_en
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_empty_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_clk_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_bl_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_bl
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_burst_cnt
add wave -noupdate -divider {Wishbone CSR master}
add wave -noupdate -divider {Wishbone CSR slaves}
add wave -noupdate -radix hexadecimal /tb_spec/U1/sys_clk_125
add wave -noupdate -divider IOs
add wave -noupdate /tb_spec/LED_RED
add wave -noupdate /tb_spec/LED_GREEN
add wave -noupdate -divider {FMC SPI}
add wave -noupdate /tb_spec/spi_din_i
add wave -noupdate /tb_spec/spi_dout_o
add wave -noupdate /tb_spec/spi_sck_o
add wave -noupdate /tb_spec/spi_cs_adc_n_o
add wave -noupdate /tb_spec/spi_cs_dac1_n_o
add wave -noupdate /tb_spec/spi_cs_dac2_n_o
add wave -noupdate /tb_spec/spi_cs_dac3_n_o
add wave -noupdate /tb_spec/spi_cs_dac4_n_o
add wave -noupdate -divider {FMC I2C}
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {34162884 ps} 0}
configure wave -namecolwidth 464
configure wave -valuecolwidth 120
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {24261691 ps} {49099641 ps}
hdl/spec/sim/wave_gnum.do
View file @ 2f92c67d
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /tb_spec/rstout18n
add wave -noupdate /tb_spec/u1/ddr3_calib_done
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/des_pd_valid
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/des_pd_dframe
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/des_pd_data
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/arb_ser_valid
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/arb_ser_dframe
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/arb_ser_data
add wave -noupdate /tb_spec/RSTOUT18n
add wave -noupdate /tb_spec/U1/ddr3_calib_done
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/des_pd_valid
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/des_pd_dframe
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/des_pd_data
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/arb_ser_valid
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/arb_ser_dframe
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/arb_ser_data
add wave -noupdate -divider {DDR ADC}
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_en_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_instr_o
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_bl_o
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_empty_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_en_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_data_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_rd_en_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_cyc_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_stb_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_we_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_addr_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_ack_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_stall_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_cyc_f_edge
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_cyc_r_edge
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_stb_f_edge
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_we_f_edge
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_burst_cnt
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_en_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_instr_o
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_bl_o
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_empty_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_en_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_data_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_rd_en_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_cyc_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_stb_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_we_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_addr_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_ack_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_stall_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_cyc_f_edge
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_cyc_r_edge
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_stb_f_edge
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_we_f_edge
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_burst_cnt
add wave -noupdate -divider {DDR GNUM}
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_burst_cnt
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_bl_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_instr_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_en_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_empty_i
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_count_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_data_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_empty_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_en_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_ack_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_addr_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_clk_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_cyc_f_edge
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_cyc_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_cyc_r_edge
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_stall_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_stb_f_edge
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_stb_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_we_f_edge
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_we_i
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_burst_cnt
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_bl_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_instr_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_en_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_empty_i
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_count_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_data_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_empty_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_en_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_ack_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_addr_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_clk_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_cyc_f_edge
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_cyc_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_cyc_r_edge
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_stall_o
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_stb_f_edge
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_stb_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_we_f_edge
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_we_i
add wave -noupdate -divider {P2L DMA master}
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_current_state
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_carrier_addr_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_done_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_done_t
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_error_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_host_addr_l_i
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_len_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_start_next_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_start_p2l_i
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/p2l_data_cnt
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_data_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_data_last_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_data_valid_i
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_hdr_length_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_hdr_start_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_master_cpld_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_master_cpln_i
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_header
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/is_next_item
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_attrib_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_carrier_addr_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_host_addr_h_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_host_addr_l_o
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_len_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_next_h_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_next_l_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_valid_o
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_current_state
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_carrier_addr_i
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_done_o
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_done_t
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_error_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_host_addr_l_i
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_len_i
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_start_next_i
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_start_p2l_i
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/p2l_data_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_data_i
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_data_last_i
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_data_valid_i
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_hdr_length_i
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_hdr_start_i
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_master_cpld_i
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_master_cpln_i
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_header
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/is_next_item
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_attrib_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_carrier_addr_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_host_addr_h_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_host_addr_l_o
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_len_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_next_h_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_next_l_o
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_valid_o
add wave -noupdate -divider {L2P DMA master}
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_empty
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_clk_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_ack_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_cyc_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_dat_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_stb_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_we_o
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/target_addr_cnt
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/target_addr_cnt
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_full
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_valid
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_rd
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_empty
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_dout
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_clk_i
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_cyc_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_stb_o
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_stall_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_dat_i
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_ack_i
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_wr
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_full
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_din
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_empty
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_rd
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_valid
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_last_packet
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_dframe_o
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_valid_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_req_o
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/arb_ldm_gnt_i
add wave -noupdate -divider {DMA controller}
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_current_state
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_reg
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_hstarth_reg
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_len_reg
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_nexth_reg
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_load
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_nextl_load
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_nexth_load
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_len_load
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_hstartl_load
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_hstarth_load
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_cstart_load
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_attrib_load
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_done_irq
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_error_irq
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_start_l2p_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_start_next_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_start_p2l_o
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_len_reg
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/next_item_attrib_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/next_item_carrier_addr_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/next_item_host_addr_h_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/next_item_host_addr_l_i
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/next_item_len_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/next_item_next_h_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/next_item_next_l_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/next_item_valid_i
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_current_state
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_reg
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_hstarth_reg
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_len_reg
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_nexth_reg
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_load
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_nextl_load
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_nexth_load
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_len_load
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_hstartl_load
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_hstarth_load
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_cstart_load
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_attrib_load
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_done_irq
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_error_irq
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_start_l2p_o
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_start_next_o
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_start_p2l_o
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_len_reg
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/next_item_attrib_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/next_item_carrier_addr_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/next_item_host_addr_h_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/next_item_host_addr_l_i
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/next_item_len_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/next_item_next_h_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/next_item_next_l_i
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/next_item_valid_i
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {42220934 ps} 0} {{Cursor 2} {13856000 ps} 0}
WaveRestoreCursors {{Cursor 1} {30090961 ps} 0} {{Cursor 2} {22107797 ps} 0}
configure wave -namecolwidth 496
configure wave -valuecolwidth 172
configure wave -justifyvalue left
......@@ -145,4 +166,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {10050 ns} {11935099 ps}
WaveRestoreZoom {22026423 ps} {22191901 ps}
hdl/spec/spec_top_fmc_adc_100Ms.ucf
View file @ 2f92c67d
......@@ -258,10 +258,10 @@ NET "spi_cs_dac4_n_o" IOSTANDARD = "LVCMOS25";
NET "gpio_dac_clr_n_o" LOC = W18; # LA30_N
NET "gpio_dac_clr_n_o" IOSTANDARD = "LVCMOS25";
NET "gpio_led_power_o" LOC = W15; # LA28_N
NET "gpio_led_power_o" IOSTANDARD = "LVCMOS25";
NET "gpio_led_trigger_o" LOC = Y16; # LA28_P
NET "gpio_led_trigger_o" IOSTANDARD = "LVCMOS25";
NET "gpio_led_acq_o" LOC = W15; # LA28_N
NET "gpio_led_acq_o" IOSTANDARD = "LVCMOS25";
NET "gpio_led_trig_o" LOC = Y16; # LA28_P
NET "gpio_led_trig_o" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch1_o[0]" LOC = Y17; # LA26_P
NET "gpio_ssr_ch1_o[0]" IOSTANDARD = "LVCMOS25";
......@@ -546,8 +546,8 @@ NET "AUX_LEDS_O[3]" IOSTANDARD = "LVCMOS18";
INST "cmp_gn4124_core/l2p_rdy_t" IOB=FALSE;
INST "cmp_gn4124_core/l_wr_rdy_t*" IOB=FALSE;
INST "cmp_fmc_spi/Wrapped_SPI/shift/s_out" IOB=FALSE;
INST "cmp_fmc_spi/Wrapped_SPI/clgen/clk_out" IOB=FALSE;
INST "cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/s_out" IOB=FALSE;
INST "cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/clgen/clk_out" IOB=FALSE;
#===============================================================================
......@@ -564,18 +564,66 @@ NET "DDR3_UDQS_N" IN_TERM = NONE;
#===============================================================================
# Clock constraints
# Timing constraints
#===============================================================================
# GN4124
NET "L_CLKp" TNM_NET = "l_clkp_grp";
TIMESPEC TS_l_clkp = PERIOD "l_clkp_grp" 5 ns HIGH 50%;
#NET "L_CLKp" TNM_NET = "l_clkp_grp";
#TIMESPEC TS_l_clkp = PERIOD "l_clkp_grp" 5 ns HIGH 50%;
NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
TIMESPEC TS_p2l_clkp = PERIOD "p2l_clkp_grp" 5 ns HIGH 50%;
NET "P2L_CLKn" TNM_NET = "p2l_clkn_grp";
TIMESPEC TS_p2l_clkn = PERIOD "p2l_clkn_grp" 5 ns HIGH 50%;
NET "L2P_CLKN" TNM = "gn4124_data_bus_out";
NET "L2P_CLKP" TNM = "gn4124_data_bus_out";
NET "L2P_VALID" TNM = "gn4124_data_bus_out";
NET "L2P_DFRAME" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[0]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[1]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[2]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[3]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[4]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[5]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[6]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[7]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[8]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[9]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[10]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[11]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[12]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[13]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[14]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[15]" TNM = "gn4124_data_bus_out";
#TIMEGRP "gn4124_data_bus_out" OFFSET = OUT AFTER "cmp_gn4124_core/io_clk" REFERENCE_PIN "L2P_CLKP";
NET "P2L_CLKN" TNM = "gn4124_data_bus_in";
NET "P2L_CLKP" TNM = "gn4124_data_bus_in";
NET "P2L_DFRAME" TNM = "gn4124_data_bus_in";
NET "P2L_VALID" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[0]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[1]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[2]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[3]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[4]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[5]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[6]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[7]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[8]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[9]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[10]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[11]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[12]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[13]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[14]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[15]" TNM = "gn4124_data_bus_in";
#TIMEGRP "gn4124_data_bus_in" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE "cmp_gn4124_core/io_clk" RISING;
#TIMEGRP "gn4124_data_bus_in" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE "cmp_gn4124_core/io_clk" FALLING;
# System clock
NET "clk20_vcxo_i" TNM_NET = "clk20_vcxo_i_grp";
......
hdl/spec/syn/spec_fmc_adc_100Ms.xise
View file @ 2f92c67d
......@@ -78,7 +78,6 @@
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -172,7 +171,6 @@
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -211,13 +209,11 @@
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="spec_top_fmc_adc_100Ms_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spec_top_fmc_adc_100Ms_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spec_top_fmc_adc_100Ms_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
......@@ -277,7 +273,6 @@
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
......@@ -332,8 +327,8 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-11-08T18:12:50" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="1F4F849093C7768961E521CF8EC93589" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-05T13:56:04" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="354EEA7886BD17F3531E42B45056CD84" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
......@@ -386,884 +381,716 @@
<file xil_pn:name="../rtl/irq_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../rtl/sdb_meta_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_csr.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../adc/rtl/offset_gain_s.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/offset_gain_s.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/common/rtl/dummy_ctrl_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/common/rtl/dummy_stat_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/common/rtl/wb_addr_decoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_wfifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
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<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_builtin.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="133"/>
<association xil_pn:name="Implementation" xil_pn:seqID="125"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rgtw.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="134"/>
<association xil_pn:name="Implementation" xil_pn:seqID="126"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wgtr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="135"/>
<association xil_pn:name="Implementation" xil_pn:seqID="127"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_block_fifo16_patch.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="136"/>
<association xil_pn:name="Implementation" xil_pn:seqID="128"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_block_fifo16_patch.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="137"/>
<association xil_pn:name="Implementation" xil_pn:seqID="129"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo16_patch_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
<association xil_pn:name="Implementation" xil_pn:seqID="130"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_fifo16_patch.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="139"/>
<association xil_pn:name="Implementation" xil_pn:seqID="131"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
<association xil_pn:name="Implementation" xil_pn:seqID="132"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
<association xil_pn:name="Implementation" xil_pn:seqID="133"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
<association xil_pn:name="Implementation" xil_pn:seqID="134"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
<association xil_pn:name="Implementation" xil_pn:seqID="135"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
<association xil_pn:name="Implementation" xil_pn:seqID="136"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
<association xil_pn:name="Implementation" xil_pn:seqID="137"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="146"/>
<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="147"/>
<association xil_pn:name="Implementation" xil_pn:seqID="139"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="148"/>
<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="149"/>
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="150"/>
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="151"/>
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="153"/>
<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="154"/>
<association xil_pn:name="Implementation" xil_pn:seqID="146"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="155"/>
<association xil_pn:name="Implementation" xil_pn:seqID="147"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="156"/>
<association xil_pn:name="Implementation" xil_pn:seqID="148"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="157"/>
<association xil_pn:name="Implementation" xil_pn:seqID="149"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="158"/>
<association xil_pn:name="Implementation" xil_pn:seqID="150"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="159"/>
<association xil_pn:name="Implementation" xil_pn:seqID="151"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="160"/>
<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
<association xil_pn:name="Implementation" xil_pn:seqID="153"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
<association xil_pn:name="Implementation" xil_pn:seqID="154"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
<association xil_pn:name="Implementation" xil_pn:seqID="155"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="164"/>
<association xil_pn:name="Implementation" xil_pn:seqID="156"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="165"/>
<association xil_pn:name="Implementation" xil_pn:seqID="157"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
<association xil_pn:name="Implementation" xil_pn:seqID="158"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="167"/>
<association xil_pn:name="Implementation" xil_pn:seqID="159"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="168"/>
<association xil_pn:name="Implementation" xil_pn:seqID="160"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="169"/>
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="170"/>
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="171"/>
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="172"/>
<association xil_pn:name="Implementation" xil_pn:seqID="164"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="173"/>
<association xil_pn:name="Implementation" xil_pn:seqID="165"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="174"/>
<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="175"/>
<association xil_pn:name="Implementation" xil_pn:seqID="167"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="176"/>
<association xil_pn:name="Implementation" xil_pn:seqID="168"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="177"/>
<association xil_pn:name="Implementation" xil_pn:seqID="169"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="178"/>
<association xil_pn:name="Implementation" xil_pn:seqID="170"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="179"/>
<association xil_pn:name="Implementation" xil_pn:seqID="171"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="180"/>
<association xil_pn:name="Implementation" xil_pn:seqID="172"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="181"/>
<association xil_pn:name="Implementation" xil_pn:seqID="173"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="182"/>
<association xil_pn:name="Implementation" xil_pn:seqID="174"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="Implementation" xil_pn:seqID="175"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="Implementation" xil_pn:seqID="176"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="185"/>
<association xil_pn:name="Implementation" xil_pn:seqID="177"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="186"/>
<association xil_pn:name="Implementation" xil_pn:seqID="178"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="187"/>
<association xil_pn:name="Implementation" xil_pn:seqID="179"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="188"/>
<association xil_pn:name="Implementation" xil_pn:seqID="180"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="189"/>
<association xil_pn:name="Implementation" xil_pn:seqID="181"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="190"/>
<association xil_pn:name="Implementation" xil_pn:seqID="182"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="191"/>
<association xil_pn:name="Implementation" xil_pn:seqID="183"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="184"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="193"/>
<association xil_pn:name="Implementation" xil_pn:seqID="185"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="194"/>
<association xil_pn:name="Implementation" xil_pn:seqID="186"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="187"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
<association xil_pn:name="Implementation" xil_pn:seqID="188"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
<association xil_pn:name="Implementation" xil_pn:seqID="189"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
<association xil_pn:name="Implementation" xil_pn:seqID="190"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
<association xil_pn:name="Implementation" xil_pn:seqID="191"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="192"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="193"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="194"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="259"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_32b_32b/user_design/rtl/memc1_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="260"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/ddr3_ctrl_vfc_bank1_64b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="261"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="262"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="263"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="264"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="265"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="266"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/memc1_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="267"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/memc1_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="268"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="269"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="270"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="271"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="272"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="273"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="274"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="275"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="276"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="277"/>
</file>
</files>
<bindings/>
......
hdl/spec/syn/spec_top_fmc_adc_100Ms.par
View file @ 2f92c67d
Release 13.3 par O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
pcbe15575:: Fri Aug 03 16:40:29 2012
pcbe15575:: Thu Mar 07 18:50:59 2013
par -w -intstyle ise -ol high -mt off spec_top_fmc_adc_100Ms_map.ncd
spec_top_fmc_adc_100Ms.ncd spec_top_fmc_adc_100Ms.pcf
......@@ -22,16 +22,16 @@ Device speed data version: "PRODUCTION 1.20 2011-10-03".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 6,824 out of 54,576 12%
Number used as Flip Flops: 6,824
Number of Slice Registers: 6,805 out of 54,576 12%
Number used as Flip Flops: 6,805
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,460 out of 27,288 20%
Number used as logic: 4,929 out of 27,288 18%
Number using O6 output only: 3,109
Number using O5 output only: 279
Number using O5 and O6: 1,541
Number of Slice LUTs: 5,450 out of 27,288 19%
Number used as logic: 5,169 out of 27,288 18%
Number using O6 output only: 3,262
Number using O5 output only: 281
Number using O5 and O6: 1,626
Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1%
Number used as Dual Port RAM: 0
......@@ -40,18 +40,18 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 529
Number with same-slice register load: 518
Number used exclusively as route-thrus: 279
Number with same-slice register load: 268
Number with same-slice carry load: 11
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,365 out of 6,822 34%
Number of occupied Slices: 2,618 out of 6,822 38%
Nummber of MUXCYs used: 1,424 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,523
Number with an unused Flip Flop: 1,673 out of 7,523 22%
Number with an unused LUT: 2,063 out of 7,523 27%
Number of fully used LUT-FF pairs: 3,787 out of 7,523 50%
Number of LUT Flip Flop pairs used: 7,968
Number with an unused Flip Flop: 1,934 out of 7,968 24%
Number with an unused LUT: 2,518 out of 7,968 31%
Number of fully used LUT-FF pairs: 3,516 out of 7,968 44%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
......@@ -66,7 +66,7 @@ IO Utilization:
Number of LOCed IOBs: 188 out of 188 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 67 out of 116 57%
Number of RAMB16BWERs: 68 out of 116 58%
Number of RAMB8BWERs: 2 out of 232 1%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
......@@ -109,42 +109,41 @@ Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 14 secs
Finished initial Timing Analysis. REAL time: 15 secs
Starting initial Timing Analysis. REAL time: 17 secs
Finished initial Timing Analysis. REAL time: 18 secs
WARNING:Par:288 - The signal aux_buttons_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal aux_buttons_i<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VC_RDY<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VC_RDY<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal TX_ERROR_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal P_WR_REQ<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal P_WR_REQ<1>_IBUF has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 43474 unrouted; REAL time: 16 secs
Phase 1 : 45135 unrouted; REAL time: 19 secs
Phase 2 : 33345 unrouted; REAL time: 21 secs
Phase 2 : 34792 unrouted; REAL time: 24 secs
Phase 3 : 13108 unrouted; REAL time: 47 secs
Phase 3 : 14548 unrouted; REAL time: 51 secs
Phase 4 : 13126 unrouted; (Setup:0, Hold:4589, Component Switching Limit:0) REAL time: 51 secs
Phase 4 : 14581 unrouted; (Setup:0, Hold:1455, Component Switching Limit:0) REAL time: 56 secs
Updating file: spec_top_fmc_adc_100Ms.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:4455, Component Switching Limit:0) REAL time: 1 mins 28 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:1455, Component Switching Limit:0) REAL time: 1 mins 38 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:4455, Component Switching Limit:0) REAL time: 1 mins 28 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:1455, Component Switching Limit:0) REAL time: 1 mins 38 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:4455, Component Switching Limit:0) REAL time: 1 mins 28 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:1455, Component Switching Limit:0) REAL time: 1 mins 38 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:4455, Component Switching Limit:0) REAL time: 1 mins 28 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:1455, Component Switching Limit:0) REAL time: 1 mins 38 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 29 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 39 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 32 secs
Total REAL time to Router completion: 1 mins 32 secs
Total CPU time to Router completion: 1 mins 34 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 42 secs
Total REAL time to Router completion: 1 mins 42 secs
Total CPU time to Router completion: 1 mins 42 secs
Partition Implementation Status
-------------------------------
......@@ -162,19 +161,19 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_125 | BUFGMUX_X2Y2| No | 1276 | 0.067 | 1.278 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/sys_ | | | | | |
| clk | BUFGMUX_X2Y12| No | 641 | 0.187 | 1.398 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_fmc_adc_100Ms_co | | | | | |
| re/fs_clk | BUFGMUX_X2Y4| No | 155 | 0.237 | 1.473 |
| sys_clk_125 | BUFGMUX_X2Y2| No | 1312 | 0.068 | 1.279 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl/cmp_ddr | | | | | |
|3_ctrl_wrapper/gen_s | | | | | |
|pec_bank3_64b_32b.cm | | | | | |
|p_ddr3_ctrl/c3_mcb_d | | | | | |
| rp_clk | BUFGMUX_X3Y13| No | 78 | 0.048 | 1.285 |
| rp_clk | BUFGMUX_X3Y13| No | 80 | 0.070 | 1.285 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/sys_ | | | | | |
| clk | BUFGMUX_X2Y12| No | 692 | 0.187 | 1.398 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_fmc_adc_100Ms_co | | | | | |
| re/fs_clk | BUFGMUX_X2Y4| No | 163 | 0.251 | 1.473 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/io_c | | | | | |
| lk | Local| | 41 | 0.064 | 1.562 |
......@@ -290,12 +289,12 @@ Asterisk (*) preceding a constraint indicates it was not met.
k_2x_180" TS_SYS_CLK5 / 2 PHASE 0 | | | | |
.75 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_ | SETUP | 0.034ns| 7.966ns| 0| 0
clk_125_buf" TS_clk20_vcxo_i / 6.25 | HOLD | 0.326ns| | 0| 0
TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_ | SETUP | 0.032ns| 7.968ns| 0| 0
clk_125_buf" TS_clk20_vcxo_i / 6.25 | HOLD | 0.354ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.047ns| 4.953ns| 0| 0
1_0 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.082ns| | 0| 0
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.038ns| 4.962ns| 0| 0
1_0 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.060ns| | 0| 0
core_cmp_clk_in_rx_pllout_x1_0" T | | | | |
S_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 | | | | |
PHASE 1.25 ns HIGH 50% | | | | |
......@@ -303,7 +302,7 @@ Asterisk (*) preceding a constraint indicates it was not met.
TS_adc_dco_n_i = PERIOD TIMEGRP "adc_dco_ | MINLOWPULSE | 0.364ns| 1.636ns| 0| 0
n_i" 2 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_100Ms_core_fs_clk_buf = PE | SETUP | 0.306ns| 7.694ns| 0| 0
TS_cmp_fmc_adc_100Ms_core_fs_clk_buf = PE | SETUP | 0.271ns| 7.729ns| 0| 0
RIOD TIMEGRP "cmp_fmc_adc_100Ms_c | HOLD | 0.399ns| | 0| 0
ore_fs_clk_buf" TS_adc_dco_n_i / 0.25 HIG | | | | |
H 50% | | | | |
......@@ -334,20 +333,20 @@ Asterisk (*) preceding a constraint indicates it was not met.
TS_clk20_vcxo_i = PERIOD TIMEGRP "clk20_v | MINLOWPULSE | 30.000ns| 20.000ns| 0| 0
cxo_i_grp" 50 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | SETUP | 3.924ns| 8.075ns| 0| 0
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | HOLD | 0.240ns| | 0| 0
TS_p2l_clkn = PERIOD TIMEGRP "p2l_clkn_gr | MINPERIOD | 4.075ns| 0.925ns| 0| 0
p" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_p2l_clkp = PERIOD TIMEGRP "p2l_clkp_gr | MINPERIOD | 4.075ns| 0.925ns| 0| 0
p" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | SETUP | 4.593ns| 7.406ns| 0| 0
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | HOLD | 0.388ns| | 0| 0
nfrastructure_inst_mcb_drp_clk_bufg_in_0 | | | | |
= PERIOD TIMEGRP "cmp_ddr | | | | |
_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank | | | | |
3_64b_32b_cmp_ddr3_ctrl_memc3_infrastruct | | | | |
ure_inst_mcb_drp_clk_bufg_in_0" T | | | | |
S_ddr_clk_buf / 0.25 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_p2l_clkn = PERIOD TIMEGRP "p2l_clkn_gr | MINPERIOD | 4.075ns| 0.925ns| 0| 0
p" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_p2l_clkp = PERIOD TIMEGRP "p2l_clkp_gr | MINPERIOD | 4.075ns| 0.925ns| 0| 0
p" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | MINPERIOD | 10.270ns| 1.730ns| 0| 0
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | | | | |
......@@ -402,12 +401,12 @@ Derived Constraints for TS_p2l_clkn
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_p2l_clkn | 5.000ns| 0.925ns| 4.953ns| 0| 0| 0| 29020|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.953ns| 0| 0| 0| 29020|
|TS_p2l_clkn | 5.000ns| 0.925ns| 4.962ns| 0| 0| 0| 29035|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.962ns| 0| 0| 0| 29035|
| buf_P_clk_0 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| _rx_pllout_xs_int_0 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.953ns| N/A| 0| 0| 29020| 0|
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.962ns| N/A| 0| 0| 29035| 0|
| _rx_pllout_x1_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
......@@ -417,10 +416,10 @@ Derived Constraints for TS_clk20_vcxo_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk20_vcxo_i | 50.000ns| 20.000ns| 49.967ns| 0| 0| 0| 399507|
| TS_sys_clk_125_buf | 8.000ns| 7.966ns| N/A| 0| 0| 389107| 0|
|TS_clk20_vcxo_i | 50.000ns| 20.000ns| 49.967ns| 0| 0| 0| 402700|
| TS_sys_clk_125_buf | 8.000ns| 7.968ns| N/A| 0| 0| 392300| 0|
| TS_ddr_clk_buf | 3.000ns| 2.572ns| 2.998ns| 0| 0| 0| 10400|
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl| 12.000ns| 8.075ns| N/A| 0| 0| 10400| 0|
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl| 12.000ns| 7.406ns| N/A| 0| 0| 10400| 0|
| _wrapper_gen_spec_bank3_64b_3| | | | | | | |
| 2b_cmp_ddr3_ctrl_memc3_infras| | | | | | | |
| tructure_inst_mcb_drp_clk_buf| | | | | | | |
......@@ -462,8 +461,8 @@ Derived Constraints for TS_adc_dco_n_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_adc_dco_n_i | 2.000ns| 1.636ns| 1.923ns| 0| 0| 0| 18373|
| TS_cmp_fmc_adc_100Ms_core_fs_c| 8.000ns| 7.694ns| N/A| 0| 0| 18373| 0|
|TS_adc_dco_n_i | 2.000ns| 1.636ns| 1.932ns| 0| 0| 0| 18373|
| TS_cmp_fmc_adc_100Ms_core_fs_c| 8.000ns| 7.729ns| N/A| 0| 0| 18373| 0|
| lk_buf | | | | | | | |
| TS_cmp_fmc_adc_100Ms_core_serd| 1.000ns| N/A| N/A| 0| 0| 0| 0|
| es_clk | | | | | | | |
......@@ -481,19 +480,19 @@ Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 7 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:Par:283 - There are 6 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 1 mins 35 secs
Total CPU time to PAR completion: 1 mins 37 secs
Total REAL time to PAR completion: 1 mins 45 secs
Total CPU time to PAR completion: 1 mins 45 secs
Peak Memory Usage: 340 MB
Peak Memory Usage: 347 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 9
Number of warning messages: 8
Number of info messages: 1
Writing design to file spec_top_fmc_adc_100Ms.ncd
......
hdl/spec/syn/spec_top_fmc_adc_100Ms.syr
View file @ 2f92c67d
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/spec_top_fmc_adc_100Ms.twr
View file @ 2f92c67d
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/spec_top_fmc_adc_100Ms_map.mrp
View file @ 2f92c67d
......@@ -11,23 +11,23 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Fri Aug 3 16:35:35 2012
Mapped Date : Thu Mar 7 18:46:02 2013
Design Summary
--------------
Number of errors: 0
Number of warnings: 8
Slice Logic Utilization:
Number of Slice Registers: 6,824 out of 54,576 12%
Number used as Flip Flops: 6,824
Number of Slice Registers: 6,805 out of 54,576 12%
Number used as Flip Flops: 6,805
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,460 out of 27,288 20%
Number used as logic: 4,929 out of 27,288 18%
Number using O6 output only: 3,109
Number using O5 output only: 279
Number using O5 and O6: 1,541
Number of Slice LUTs: 5,450 out of 27,288 19%
Number used as logic: 5,169 out of 27,288 18%
Number using O6 output only: 3,262
Number using O5 output only: 281
Number using O5 and O6: 1,626
Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1%
Number used as Dual Port RAM: 0
......@@ -36,21 +36,21 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 529
Number with same-slice register load: 518
Number used exclusively as route-thrus: 279
Number with same-slice register load: 268
Number with same-slice carry load: 11
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,365 out of 6,822 34%
Number of occupied Slices: 2,618 out of 6,822 38%
Nummber of MUXCYs used: 1,424 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,523
Number with an unused Flip Flop: 1,673 out of 7,523 22%
Number with an unused LUT: 2,063 out of 7,523 27%
Number of fully used LUT-FF pairs: 3,787 out of 7,523 50%
Number of unique control sets: 261
Number of LUT Flip Flop pairs used: 7,968
Number with an unused Flip Flop: 1,934 out of 7,968 24%
Number with an unused LUT: 2,518 out of 7,968 31%
Number of fully used LUT-FF pairs: 3,516 out of 7,968 44%
Number of unique control sets: 260
Number of slice register sites lost
to control set restrictions: 686 out of 54,576 1%
to control set restrictions: 673 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
......@@ -63,7 +63,7 @@ IO Utilization:
Number of LOCed IOBs: 188 out of 188 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 67 out of 116 57%
Number of RAMB16BWERs: 68 out of 116 58%
Number of RAMB8BWERs: 2 out of 232 1%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
......@@ -100,11 +100,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.76
Average Fanout of Non-Clock Nets: 3.79
Peak Memory Usage: 413 MB
Total REAL time to MAP completion: 4 mins 48 secs
Total CPU time to MAP completion (all processors): 4 mins 50 secs
Peak Memory Usage: 417 MB
Total REAL time to MAP completion: 4 mins 50 secs
Total CPU time to MAP completion (all processors): 4 mins 52 secs
Table of Contents
-----------------
......@@ -162,10 +162,10 @@ INFO:Map:284 - Map is running with the multi-threading option on. Map currently
INFO:LIT:243 - Logical network
cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3
_infrastructure_inst/rst0_sync_r<24> has no load.
INFO:LIT:395 - The above info message is repeated 9 more times for the following
INFO:LIT:395 - The above info message is repeated 8 more times for the following
(max. 5 shown):
N648,
N650,
N754,
N756,
aux_buttons_i<1>_IBUF,
aux_buttons_i<0>_IBUF,
P_WR_REQ<1>_IBUF
......
hdl/spec/wb_gen/carrier_csr.h
View file @ 2f92c67d
......@@ -3,7 +3,7 @@
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Wed Nov 23 09:30:44 2011
* Created : Mon Mar 11 17:11:09 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -51,10 +51,6 @@
#define CARRIER_CSR_CARRIER_TYPE_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define CARRIER_CSR_CARRIER_TYPE_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Bitstream type */
/* definitions for register: Bitstream date */
/* definitions for register: Status */
/* definitions for field: FMC presence in reg: Status */
......@@ -95,13 +91,9 @@
PACKED struct CARRIER_CSR_WB {
/* [0x0]: REG Carrier type and PCB version */
uint32_t CARRIER;
/* [0x4]: REG Bitstream type */
uint32_t BITSTREAM_TYPE;
/* [0x8]: REG Bitstream date */
uint32_t BITSTREAM_DATE;
/* [0xc]: REG Status */
/* [0x4]: REG Status */
uint32_t STAT;
/* [0x10]: REG Control */
/* [0x8]: REG Control */
uint32_t CTRL;
};
......
hdl/spec/wb_gen/carrier_csr.htm
View file @ 2f92c67d
......@@ -35,10 +35,8 @@
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">Carrier type and PCB version</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Bitstream type</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">Bitstream date</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">Status</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">Control</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Status</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">Control</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -83,40 +81,6 @@ CARRIER
REG
</td>
<td >
<A href="#BITSTREAM_TYPE">Bitstream type</a>
</td>
<td class="td_code">
carrier_csr_bitstream_type
</td>
<td class="td_code">
BITSTREAM_TYPE
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x2
</td>
<td >
REG
</td>
<td >
<A href="#BITSTREAM_DATE">Bitstream date</a>
</td>
<td class="td_code">
carrier_csr_bitstream_date
</td>
<td class="td_code">
BITSTREAM_DATE
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x3
</td>
<td >
REG
</td>
<td >
<A href="#STAT">Status</a>
</td>
<td class="td_code">
......@@ -128,7 +92,7 @@ STAT
</tr>
<tr class="tr_odd">
<td class="td_code">
0x4
0x2
</td>
<td >
REG
......@@ -186,7 +150,7 @@ carrier_csr_carrier_pcb_rev_i[3:0]
&rArr;
</td>
<td class="td_pblock_left">
wb_addr_i[2:0]
wb_addr_i[1:0]
</td>
<td class="td_sym_center">
......@@ -243,7 +207,7 @@ wb_cyc_i
</td>
<td class="td_pblock_right">
<b>Bitstream type:</b>
<b>Status:</b>
</td>
<td class="td_arrow_right">
......@@ -258,108 +222,6 @@ wb_sel_i[3:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_bitstream_type_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_stb_i
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_we_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Bitstream date:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_ack_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_bitstream_date_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Status:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_stat_fmc_pres_i
......@@ -370,10 +232,10 @@ carrier_csr_stat_fmc_pres_i
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_stb_i
</td>
<td class="td_sym_center">
......@@ -387,10 +249,10 @@ carrier_csr_stat_p2l_pll_lck_i
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_we_i
</td>
<td class="td_sym_center">
......@@ -404,10 +266,10 @@ carrier_csr_stat_sys_pll_lck_i
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_ack_o
</td>
<td class="td_sym_center">
......@@ -805,17 +667,17 @@ RESERVED
<li><b>
TYPE
</b>[<i>read-only</i>]: Carrier type
<br>Carrier type identifier
<br>Carrier type identifier<br>1 = SPEC<br>2 = SVEC<br>3 = VFC<br>4 = SPEXI
</ul>
<a name="BITSTREAM_TYPE"></a>
<h3><a name="sect_3_2">3.2. Bitstream type</a></h3>
<a name="STAT"></a>
<h3><a name="sect_3_2">3.2. Status</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
carrier_csr_bitstream_type
carrier_csr_stat
</td>
</tr>
<tr>
......@@ -831,7 +693,7 @@ carrier_csr_bitstream_type
<b>C prefix: </b>
</td>
<td class="td_code">
BITSTREAM_TYPE
STAT
</td>
</tr>
<tr>
......@@ -872,7 +734,7 @@ BITSTREAM_TYPE
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BITSTREAM_TYPE[31:24]
RESERVED[27:20]
</td>
<td >
......@@ -926,7 +788,7 @@ BITSTREAM_TYPE[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BITSTREAM_TYPE[23:16]
RESERVED[19:12]
</td>
<td >
......@@ -980,7 +842,7 @@ BITSTREAM_TYPE[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BITSTREAM_TYPE[15:8]
RESERVED[11:4]
</td>
<td >
......@@ -1033,20 +895,20 @@ BITSTREAM_TYPE[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BITSTREAM_TYPE[7:0]
<td style="border: solid 1px black;" colspan=4 class="td_field">
RESERVED[3:0]
</td>
<td >
<td style="border: solid 1px black;" colspan=1 class="td_field">
DDR3_CAL_DONE
</td>
<td >
<td style="border: solid 1px black;" colspan=1 class="td_field">
SYS_PLL_LCK
</td>
<td >
<td style="border: solid 1px black;" colspan=1 class="td_field">
P2L_PLL_LCK
</td>
<td >
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC_PRES
</td>
<td >
......@@ -1061,19 +923,35 @@ BITSTREAM_TYPE[7:0]
</table>
<ul>
<li><b>
BITSTREAM_TYPE
</b>[<i>read-only</i>]: Bitstream type
<br>Bitstream (firmware) type, unsigned 32-bit number.
FMC_PRES
</b>[<i>read-only</i>]: FMC presence
<br>0: FMC slot is populated<br>1: FMC slot is not populated.
<li><b>
P2L_PLL_LCK
</b>[<i>read-only</i>]: GN4142 core P2L PLL status
<br>0: not locked<br>1: locked.
<li><b>
SYS_PLL_LCK
</b>[<i>read-only</i>]: System clock PLL status
<br>0: not locked<br>1: locked.
<li><b>
DDR3_CAL_DONE
</b>[<i>read-only</i>]: DDR3 calibration status
<br>0: not done<br>1: done.
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's.
</ul>
<a name="BITSTREAM_DATE"></a>
<h3><a name="sect_3_3">3.3. Bitstream date</a></h3>
<a name="CTRL"></a>
<h3><a name="sect_3_3">3.3. Control</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
carrier_csr_bitstream_date
carrier_csr_ctrl
</td>
</tr>
<tr>
......@@ -1089,7 +967,7 @@ carrier_csr_bitstream_date
<b>C prefix: </b>
</td>
<td class="td_code">
BITSTREAM_DATE
CTRL
</td>
</tr>
<tr>
......@@ -1130,538 +1008,6 @@ BITSTREAM_DATE
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BITSTREAM_DATE[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BITSTREAM_DATE[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BITSTREAM_DATE[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BITSTREAM_DATE[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
BITSTREAM_DATE
</b>[<i>read-only</i>]: Bitstream date
<br>Bitstream generation date, unsigned 32-bit UTC time.
</ul>
<a name="STAT"></a>
<h3><a name="sect_3_4">3.4. Status</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
carrier_csr_stat
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x3
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
STAT
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0xc
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[27:20]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[19:12]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[11:4]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=4 class="td_field">
RESERVED[3:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DDR3_CAL_DONE
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
SYS_PLL_LCK
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
P2L_PLL_LCK
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC_PRES
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
FMC_PRES
</b>[<i>read-only</i>]: FMC presence
<br>0: FMC slot is populated<br>1: FMC slot is not populated.
<li><b>
P2L_PLL_LCK
</b>[<i>read-only</i>]: GN4142 core P2L PLL status
<br>0: not locked<br>1: locked.
<li><b>
SYS_PLL_LCK
</b>[<i>read-only</i>]: System clock PLL status
<br>0: not locked<br>1: locked.
<li><b>
DDR3_CAL_DONE
</b>[<i>read-only</i>]: DDR3 calibration status
<br>0: not done<br>1: done.
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's.
</ul>
<a name="CTRL"></a>
<h3><a name="sect_3_5">3.5. Control</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
carrier_csr_ctrl
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
CTRL
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x10
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[28:21]
</td>
<td >
......
hdl/spec/wb_gen/carrier_csr.wb
View file @ 2f92c67d
......@@ -31,7 +31,7 @@ peripheral {
field {
name = "Carrier type";
description = "Carrier type identifier";
description = "Carrier type identifier\n1 = SPEC\n2 = SVEC\n3 = VFC\n4 = SPEXI";
prefix = "type";
type = SLV;
size = 16;
......@@ -40,34 +40,6 @@ peripheral {
};
};
reg {
name = "Bitstream type";
prefix = "bitstream_type";
field {
name = "Bitstream type";
description = "Bitstream (firmware) type, unsigned 32-bit number.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Bitstream date";
prefix = "bitstream_date";
field {
name = "Bitstream date";
description = "Bitstream generation date, unsigned 32-bit UTC time.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Status";
prefix = "stat";
......
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