... | ... | @@ -41,21 +41,21 @@ |
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<td align="center">0x01200</td>
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<td>Carrier CSR</td>
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<td>PLL, DDR status, LED control, etc...</td>
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<td>[Registers](https://www.ohwr.org/project/fmc-adc-100m14b4cha/commits/spec-fmc-adc-v2.0/hdl/spec/wb_gen/carrier_csr.htm)</td>
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<td>[Registers](https://www.ohwr.org/project/fmc-adc-100m14b4cha-gw/commits/spec-fmc-adc-v2.0/hdl/spec/wb_gen/carrier_csr.htm)</td>
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<td>Available</td>
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</tr>
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<tr class="even">
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<td align="center">0x01300</td>
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<td>Interrupt controller</td>
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<td>Enable mask, irq source</td>
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<td>[Registers](https://www.ohwr.org/project/fmc-adc-100m14b4cha/commits/spec-fmc-adc-v2.0/hdl/spec/wb_gen/irq_controller_regs.htm)</td>
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<td>[Registers](https://www.ohwr.org/project/fmc-adc-100m14b4cha-gw/commits/spec-fmc-adc-v2.0/hdl/spec/wb_gen/irq_controller_regs.htm)</td>
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<td>Available</td>
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</tr>
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<tr class="odd">
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<td align="center">0x02000</td>
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<td>Time-tag core</td>
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<td>Trigger, acq time-tags</td>
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<td>[Registers](https://www.ohwr.org/project/fmc-adc-100m14b4cha/commits/spec-fmc-adc-v2.0/hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.htm)</td>
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<td>[Registers](https://www.ohwr.org/project/fmc-adc-100m14b4cha-gw/commits/spec-fmc-adc-v2.0/hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.htm)</td>
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<td>Available</td>
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</tr>
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<tr class="even">
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... | ... | @@ -90,7 +90,7 @@ |
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<td align="center">0x05300</td>
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<td>Mezzanine ADC core CSR</td>
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<td>ACQ state machine, input range, trigger, etc...</td>
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<td>[Registers](https://www.ohwr.org/project/fmc-adc-100m14b4cha/commits/spec-fmc-adc-v2.0/hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm)</td>
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<td>[Registers](https://www.ohwr.org/project/fmc-adc-100m14b4cha-gw/commits/spec-fmc-adc-v2.0/hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm)</td>
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<td>Available</td>
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</tr>
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<tr class="odd">
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... | ... | |