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## Memory map for spec-fmc-adc-v2.0
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*BAR0 (1MB):**
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<table>
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<thead>
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<tr class="header">
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<th align="center">Wishbone Cores</th>
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</tr>
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</thead>
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<tbody>
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<tr class="odd">
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<td align="center">* SDB version, offset (bytes) *</td>
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<td><b> Description </b></td>
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<td><b> Peripherals </b></td>
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<td><b> Internal mapping </b></td>
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<td><b> Status </b></td>
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</tr>
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<tr class="even">
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<td align="center">0x00000</td>
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<td>SDB header</td>
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<td>[SDB specification](https://www.ohwr.org/project/fmc-adc-100m14b4cha/uploads/cdab05f8c4ebbbdb83a44957f19668db/sdb-1.0.pdf)</td>
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<td>[SDB records](SdbRecords)</td>
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<td>Available</td>
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</tr>
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<tr class="odd">
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<td align="center">0x01000</td>
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<td>DMA Controller</td>
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<td>DMA config. and status</td>
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<td>[Registers](http://svn.ohwr.org/gn4124-core/trunk/documentation/specifications/func_spec_GN4124_core.pdf)</td>
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<td>Available</td>
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</tr>
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<tr class="even">
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<td align="center">0x01100</td>
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<td>Carrier 1-wire master</td>
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<td>Thermometer + unique ID [DS18B20](http://datasheets.maxim-ic.com/en/ds/DS18B20.pdf)</td>
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<td>[Registers](http://opencores.org/websvn,filedetails?repname=sockit_owm&path=%2Fsockit_owm%2Ftrunk%2Fdoc%2Fsockit_owr.pdf)</td>
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<td>Available</td>
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</tr>
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<tr class="odd">
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<td align="center">0x01200</td>
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<td>Carrier CSR</td>
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<td>PLL, DDR status, LED control, etc...</td>
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<td>[Registers](https://www.ohwr.org/project/fmc-adc-100m14b4cha/commits/spec-fmc-adc-v2.0/hdl/spec/wb_gen/carrier_csr.htm)</td>
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<td>Available</td>
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</tr>
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<tr class="even">
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<td align="center">0x01300</td>
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<td>Interrupt controller</td>
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<td>Enable mask, irq source</td>
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<td>[Registers](https://www.ohwr.org/project/fmc-adc-100m14b4cha/commits/spec-fmc-adc-v2.0/hdl/spec/wb_gen/irq_controller_regs.htm)</td>
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<td>Available</td>
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</tr>
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<tr class="odd">
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<td align="center">0x02000</td>
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<td>Time-tag core</td>
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<td>Trigger, acq time-tags</td>
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<td>[Registers](https://www.ohwr.org/project/fmc-adc-100m14b4cha/commits/spec-fmc-adc-v2.0/hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.htm)</td>
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<td>Available</td>
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</tr>
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<tr class="even">
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<td align="center">0x04000</td>
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<td>Bridge SDB header</td>
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<td>[SDB specification](https://www.ohwr.org/project/fmc-adc-100m14b4cha/uploads/cdab05f8c4ebbbdb83a44957f19668db/sdb-1.0.pdf)</td>
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<td>[SDB records](SdbRecords)</td>
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<td>Available</td>
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</tr>
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<tr class="odd">
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<td align="center">0x05000</td>
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<td>Mezzanine system management I2C master</td>
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<td>0x50) EEPROM (FMC standard) [24AA64T](http://ww1.microchip.com/downloads/en/DeviceDoc/21189S.pdf)</td>
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<td>[Registers](http://opencores.org/websvn,filedetails?repname=i2c&path=%2Fi2c%2Ftrunk%2Fdoc%2Fi2c_specs.pdf)</td>
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<td>Available</td>
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</tr>
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<tr class="even">
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<td align="center">0x05100</td>
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<td>Mezzanine SPI master</td>
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<td>0) ADC <a href="http://cds.linear.com/docs/Datasheet/21754314fa.pdf">LTC2174</a>, 1->4) DAC (for DC offset) [MAX5442](http://datasheets.maxim-ic.com/en/ds/MAX5441-MAX5444.pdf)</td>
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<td>[Registers](http://opencores.org/websvn,filedetails?repname=spi&path=%2Fspi%2Ftrunk%2Fdoc%2Fspi.pdf)</td>
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<td>Available</td>
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</tr>
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<tr class="odd">
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<td align="center">0x05200</td>
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<td>Mezzanine I2C master</td>
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<td>0x55) Oscillator (sampling clock) [Si570](http://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf)</td>
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<td>[Registers](http://opencores.org/websvn,filedetails?repname=i2c&path=%2Fi2c%2Ftrunk%2Fdoc%2Fi2c_specs.pdf)</td>
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<td>Available</td>
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</tr>
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<tr class="even">
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<td align="center">0x05300</td>
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<td>Mezzanine ADC core CSR</td>
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<td>ACQ state machine, input range, trigger, etc...</td>
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<td>[Registers](https://www.ohwr.org/project/fmc-adc-100m14b4cha/commits/spec-fmc-adc-v2.0/hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm)</td>
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<td>Available</td>
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</tr>
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<tr class="odd">
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<td align="center">0x05400</td>
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<td>Mezzanine 1-wire master</td>
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<td>Thermometer + unique ID [DS18B20](http://datasheets.maxim-ic.com/en/ds/DS18B20.pdf)</td>
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<td>[Registers](http://opencores.org/websvn,filedetails?repname=sockit_owm&path=%2Fsockit_owm%2Ftrunk%2Fdoc%2Fsockit_owr.pdf)</td>
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<td>Available</td>
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</tr>
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</tbody>
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</table>
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