... | @@ -105,15 +105,15 @@ Specifications |
... | @@ -105,15 +105,15 @@ Specifications |
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<http://edms.cern.ch/nav/EDA-03288-V1-0>
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<http://edms.cern.ch/nav/EDA-03288-V1-0>
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- V2 pre-series (10 produced)
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- V2 pre-series (10 produced)
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<http://edms.cern.ch/nav/EDA-03288-V2-0>
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<http://edms.cern.ch/nav/EDA-03288-V2-0>
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- V3 series (25 produced)
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<http://edms.cern.ch/nav/EDA-03288-V3-0>
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- Gateware:
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- Gateware:
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- [See this project's
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- [See this project's repository](https://www.ohwr.org/project/fasec)
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repository](https://www.ohwr.org/project/fasec/tree/master)
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- tcl-script for Vivado 2018.1 project creation available
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- tcl-script for Vivado 2016.2 project creation available in the
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fmcs\_xadc\_wrc branch commit:3baafa0a
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- Embedded Linux distribution:
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- Embedded Linux distribution:
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- For now based on Xilinx' PetaLinux, contact me for access to the
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- Based on Xilinx' PetaLinux 2018.1, see the [readme](README.md)
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private repository
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- Petalinux itself is based on OE/Yocto, with an active community
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- Once based on Buildroot/Yocto, will be shared here
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- custom device-tree and kernel patch for the Ethernet PHY are the most important
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### Design documents after review (March 2016)
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### Design documents after review (March 2016)
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... | @@ -166,11 +166,11 @@ Unchanged: |
... | @@ -166,11 +166,11 @@ Unchanged: |
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|25-07-2016|Main components validated: Zynq PS & PL, DDR3, power supplies and sequencer|
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|25-07-2016|Main components validated: Zynq PS & PL, DDR3, power supplies and sequencer|
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|14-08-2017|Full board validated in operation, implement 2nd iteration schematics & PCB|
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|14-08-2017|Full board validated in operation, implement 2nd iteration schematics & PCB|
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|11-09-2017|Pre-series production ordered (10x)|
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|11-09-2017|Pre-series production ordered (10x)|
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|18-12-2018|Pre-series boards (10x) received. Mid-2018 possibly an additional 40-50 boards will be produced.|
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|18-12-2017|Pre-series boards (10x) received.|
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|08-02-2019|Series boards (25x) received|
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-----
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-----
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11 January 2018
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09 April 2019
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