... | ... | @@ -99,7 +99,14 @@ Specifications |
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- Hardware: <http://edms.cern.ch/nav/EDA-03288-V1-0>
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- Gateware:
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- [See this project's
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repository](https://www.ohwr.org/project/fasec/tree/master)
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- tcl-script for Vivado 2016.2 project creation available in the
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fmcs\_xadc\_wrc branch commit:3baafa0a
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- Embedded Linux distribution:
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- For now based on Xilinx' PetaLinux, contact me for access to the
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private repository
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- Once based on Buildroot/Yocto, will be shared here
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### Design documents after review (March 2016)
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... | ... | @@ -179,11 +186,11 @@ Unchanged: |
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<td>Main components validated: Zynq PS & PL, DDR3, power supplies and sequencer</td>
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</tr>
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<tr class="even">
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<td>29-08-2016</td>
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<td><em>Full board validated, implement 2nd iteration schematics & PCB</em></td>
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<td>14-04-2017</td>
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<td><em>Full board validated in operation, implement 2nd iteration schematics & PCB</em></td>
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</tr>
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<tr class="odd">
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<td>12-09-2016</td>
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<td>12-06-2017</td>
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<td><em>Order pre-series production (10x)</em></td>
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</tr>
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</tbody>
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