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## Main Features
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- XC7Z030 controller, SoC with Kintex-7 logic (called PL, i.e.
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Programmable Logic) and Dual ARM® Cortex™-A9 MPCore at 1 GHz (called
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Programmable Logic) and Dual ARM Cortex-A9 MPCore at 1 GHz (called
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PS, i.e. Processing System)
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- Two Low-Pin Count FMC slots
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- FMC1 connectivity: Vadj fixed to 2.5V, 34 differential pairs, 1
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### <s>Design documents for review (February 2016)</s>
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- \-[Block diagram](https://www.ohwr.org/project/fasec/wikis/Documents/Design-block-diagram-)
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- \-[Schematics v0.4 and Altium
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- [Block diagram](https://www.ohwr.org/project/fasec/wikis/Documents/Design-block-diagram-)
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- [Schematics v0.4 and Altium
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project](https://www.ohwr.org/project/fasec/wikis/Documents/Design-draft-schematics-)
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- \-[Power rail calculations](https://www.ohwr.org/project/fasec/wikis/Documents/Design-power-calculations-)
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- [Power rail calculations](https://www.ohwr.org/project/fasec/wikis/Documents/Design-power-calculations-)
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-----
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