... | ... | @@ -17,35 +17,25 @@ MiddelWare (CMW). Additionally there is DDR3L memory, clocking resources |
|
|
and support the White Rabbit timing and control network. Stand-alone
|
|
|
board for use in a 'pizza-box'.
|
|
|
|
|
|
*TEMPLATE, PLEASE
|
|
|
MODIFY**
|
|
|
|
|
|
[![](/project/white-rabbit/uploads/11578355de03b7cc74a366b23b508c48/svectop_s.png)](/project/white-rabbit/uploads/0eeb5b430351eca8a4e76a5af3892c2c/svectop_l.png)
|
|
|
*SVEC V1 production board** - [block
|
|
|
diagram](https://www.ohwr.org/project/svec/uploads/e234fa371e49b0d8f0311cdd236df19c/Block.png)
|
|
|
*TEMPLATE, PLEASE MODIFY**
|
|
|
|
|
|
## Main Features
|
|
|
|
|
|
- VME64x interface
|
|
|
- XC7Z030 controller, SoC with Kintex-7 logic (called PL, i.e.
|
|
|
Programmable Logic) and Dual ARM® Cortex™-A9 MPCore at 1 GHz (called
|
|
|
PS, i.e. Processing System)
|
|
|
- Two Low-Pin Count FMC slots
|
|
|
- Vadj fixed to 2.5V
|
|
|
- No dedicated clock signals from Carrier to FMC (as only
|
|
|
available on HPC pins and use LPC)
|
|
|
- FMC connectivity: all 34 differential pairs connected, 1 GTP
|
|
|
transceiver with clock, 2 clock pairs, JTAG, I2C
|
|
|
- Xilinx FPGAs
|
|
|
- Application FPGA: Spartan-6 XC6SLX150T-3FGG900C
|
|
|
- Direct connection to all resources such as VME64x, memories
|
|
|
and FMC connectors
|
|
|
- System FPGA: Spartan-6 XC6SLX9-2FTG256C
|
|
|
- Provides VME bootloader, early oscillator/PLL config
|
|
|
- Configuration Flash memory for both Main FPGA and
|
|
|
Application FPGA configuration
|
|
|
- FMC1 connectivity: Vadj fixed to 2.5V, 34 differential pairs, 1
|
|
|
GTP transceiver with clock, 2 clock pairs, JTAG, I2C
|
|
|
- FMC2 connectivity: Vadj fixed to 1.8V, 34 differential pairs,
|
|
|
JTAG, I2C
|
|
|
- FPGA configuration
|
|
|
- From SPI flash or via VME
|
|
|
- From QSPI flash, Ethernet (through U-Boot bootloader) or MicroSD
|
|
|
card
|
|
|
- Clocking resources
|
|
|
- 1x 10-280 MHz I2C Programmable XO Oscillator, starts up at 100
|
|
|
MHz (Silicon Labs Si570, freely usable)
|
|
|
- 1x 33.33 MHz fixed oscillator, SoC main clock (clock
|
|
|
distribution to PL possible)
|
|
|
- 1x 125 MHz fixed oscillator for the FPGA fabric
|
|
|
- 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662,
|
|
|
used by [White Rabbit PTP
|
|
|
core](https://www.ohwr.org/wr-cores/wikis/Wrpc-core))
|
... | ... | @@ -56,43 +46,28 @@ diagram](https://www.ohwr.org/project/svec/uploads/e234fa371e49b0d8f0311cdd236df |
|
|
configuration, Fout=125 MHz, used by [White Rabbit PTP
|
|
|
core](https://www.ohwr.org/wr-cores/wikis/Wrpc-core))
|
|
|
- On-board memories
|
|
|
- 2x 256 MByte (2 Gbit) DDR3 (16-bit bus, MT41J128M16JT-125)
|
|
|
- 1x 128 Mbit SPI flash for FPGA firmware storage (M25P128-VME6GB)
|
|
|
- 64kbit EEPROM connected for storing application parameters
|
|
|
(24AA64T-I/MC)
|
|
|
- 1x I2C configuration EEPROM (24LC64)
|
|
|
- 2x 512 MByte (4 Gbit) DDR3L (MT41K256M16HA-125:E)
|
|
|
- 2x 128 Mbit QSPI flash for FPGA bitstream and Linux kernel &
|
|
|
root file system storage (S25FL128SAGMFIR01)
|
|
|
- Miscellaneous
|
|
|
- On-board thermometer IC (DS18B20U+)
|
|
|
- Unique 64-bit identifier (DS18B20U+)
|
|
|
- UCD90120ARGC power controller (programmable over JTAG) to survey
|
|
|
power rails and manage power-on and power-off sequence
|
|
|
- Xilinx-style JTAG connector
|
|
|
- 2x hexadecimal switches (for settings selection)
|
|
|
- UART over a Micro-USB connector (FT232RL)
|
|
|
- Front panel
|
|
|
- 1x SFP port ([White
|
|
|
Rabbit](https://www.ohwr.org/project/white-rabbit/wikis/)
|
|
|
compatible)
|
|
|
- 4x LEMO/SMC programmable I/Os capable of driving 3.3V @ 50 ohm
|
|
|
- 2x mini displayPort connectors for high-speed serial GTP links
|
|
|
(not for video)
|
|
|
- 8x Programmable LED
|
|
|
- Reset push button
|
|
|
- 2x LEMO/SMC inputs (5V)
|
|
|
- 2x LEMO/SMC outputs capable of driving 3.3V @ 50 ohm
|
|
|
- 1x mini displayPort connector for high-speed serial card-to-card
|
|
|
GTP link
|
|
|
- 8x Programmable LED (4 by PL, 4 by PL)
|
|
|
- POR Reset push button
|
|
|
- Internal connectors
|
|
|
- VME P2 connector provides access to a Rear Transition Module
|
|
|
(compatible to
|
|
|
[VFC](https://www.ohwr.org/project/fmc-vme-carrier/wiki))
|
|
|
- 40 user defined single ended (Vcco=2.5V) signals (or 20 LVDS
|
|
|
pairs) connected to the Application FPGA
|
|
|
- 2x 125 MHz LVDS clocks provided to the RTM
|
|
|
- Xilinx-style JTAG connector
|
|
|
- Internal mini USB 2.0 High Speed connector for stand-alone
|
|
|
applications (CP2103)
|
|
|
- Optional features, check with vendor
|
|
|
- Internal 2 x SATA connector for stand-alone PCI Express
|
|
|
connectivity (clock + data)
|
|
|
- Internal 4 x UFL connectors with low-jitter clock for FMC cards
|
|
|
- Internal additional USB 2.0 on 4-pin header (FT2232HL)
|
|
|
- Battery for secure storage of FPGA configuration data
|
|
|
- Stand-alone features
|
|
|
- External supply connector (3.3V, 5V) on internal SATA
|
|
|
connector
|
|
|
- PCIe interface on internal SATA connector
|
|
|
- Back panel
|
|
|
- 2x 100 Mbit Ethernet RJ45 ports (1 interface, switched)
|
|
|
- 10-layer PCB
|
|
|
|
|
|
-----
|
... | ... | @@ -115,9 +90,8 @@ diagram](https://www.ohwr.org/project/svec/uploads/e234fa371e49b0d8f0311cdd236df |
|
|
|
|
|
- Hardware: v3.0 -
|
|
|
[EDA-02530-V3-0](https://edms.cern.ch/nav/EDA-02530-V3-0)
|
|
|
- Gateware: v3.0 - [Gateware release 3.0](Gateware-Release-3-0)
|
|
|
- Linux driver: see [Software support for
|
|
|
SVEC](https://www.ohwr.org/project/svec-sw/wiki) Project
|
|
|
- Gateware:
|
|
|
- Embedded Linux distribution: see \!/project/embedded-linux
|
|
|
|
|
|
*All Gateware releases:** See the [Releases](Releases) page.
|
|
|
|
... | ... | @@ -145,20 +119,28 @@ diagram](https://www.ohwr.org/project/svec/uploads/e234fa371e49b0d8f0311cdd236df |
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>12-02-2015</td>
|
|
|
<td>First version general description and functional requirements specification.</td>
|
|
|
<td>Start of specification as part of the FIDS project.</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>03-02-2016</td>
|
|
|
<td>Schematics ready for review (v0.4), all data uploaded.</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>10-02-2016</td>
|
|
|
<td>TE-ABT & BE-CO reviews finished</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>31-08-2015</td>
|
|
|
<td>General description and functional requirements specification ready (v0.4).</td>
|
|
|
<td>15-02-2016</td>
|
|
|
<td>Schematics transfer to CERN's Design Office for PCB routing</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>28-01-2016</td>
|
|
|
<td>Schematics ready for review (v0.3).</td>
|
|
|
<td>15-04-2016</td>
|
|
|
<td>First prototype available for testing</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
|
|
|
-----
|
|
|
|
|
|
29 January 2016
|
|
|
03 Februarty 2016
|
|
|
|