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## Project description
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## Project description
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A carrier for two low pin count FPGA Mezzanine Cards (VITA 57), analog
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This card is a carrier for two low pin count FPGA Mezzanine Cards (VITA
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inputs and fail-safe functionality. It has memory and clocking resources
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57) with additional 200 kSPS bipolar analog inputs, Ethernet
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and supports the White Rabbit timing and control network. Stand-alone
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connectivity and fail-safe functionality. The card has been developed
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board for use in a 'pizza-box'.
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within CERN's [TE-ABT
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group](http://te-dep.web.cern.ch/content/accelerator-beam-transfer-group-abt)
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for the Fast Interlocks Detection System (FIDS). It has memory and
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clocking resources and supports the White Rabbit timing and control
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network. Stand-alone board for use in a 'pizza-box'.
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*TEMPLATE, PLEASE
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*TEMPLATE, PLEASE
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MODIFY**
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MODIFY**
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