... | @@ -11,13 +11,13 @@ for the Fast Interlocks Detection System (FIDS) project. |
... | @@ -11,13 +11,13 @@ for the Fast Interlocks Detection System (FIDS) project. |
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The main controller is a System-on-a-Chip from Xilinx, the Zynq XCZ030
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The main controller is a System-on-a-Chip from Xilinx, the Zynq XCZ030
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that consists of two silicon ARM cores and FPGA fabric. The idea is to
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that consists of two silicon ARM cores and FPGA fabric. The idea is to
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implement fast interlocking logic (\<100ns) in the FPGA while the
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implement fast interlocking logic (\<100ns reaction time, 1 ns
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processor, running Embedded GNU/Linux, runs user applications to control
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resolution measurements) in the FPGA while the processor, running
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deterministically the equipment and communicate with other devices and
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Embedded GNU/Linux, runs user applications to control deterministically
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CERN's Controls MiddleWare (CMW). Additionally there is DDR3L memory,
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the equipment and communicate with other devices and CERN's Controls
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clocking resources and support the White Rabbit timing and control
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MiddleWare (CMW). Additionally there is DDR3L memory, clocking resources
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network. Stand-alone board for use in a 19" rack 1U crate (aka
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and support the White Rabbit timing and control network. Stand-alone
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pizza-box).
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board for use in a 19" rack 1U crate (aka pizza-box).
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h2. Design draft documents for review (February 2016)
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h2. Design draft documents for review (February 2016)
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- [Block diagram](https://www.ohwr.org/project/fasec/wikis/Documents/Design-block-diagram)
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- [Block diagram](https://www.ohwr.org/project/fasec/wikis/Documents/Design-block-diagram)
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